| .. | .. |
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| 13 | 13 | #include <linux/perf_event.h> |
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| 14 | 14 | #include <linux/platform_device.h> |
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| 15 | 15 | |
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| 16 | +#include <asm/core.h> |
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| 16 | 17 | #include <asm/processor.h> |
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| 17 | 18 | #include <asm/stacktrace.h> |
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| 18 | 19 | |
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| 20 | +#define XTENSA_HWVERSION_RG_2015_0 260000 |
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| 21 | + |
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| 22 | +#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RG_2015_0 |
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| 23 | +#define XTENSA_PMU_ERI_BASE 0x00101000 |
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| 24 | +#else |
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| 25 | +#define XTENSA_PMU_ERI_BASE 0x00001000 |
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| 26 | +#endif |
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| 27 | + |
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| 19 | 28 | /* Global control/status for all perf counters */ |
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| 20 | | -#define XTENSA_PMU_PMG 0x1000 |
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| 29 | +#define XTENSA_PMU_PMG XTENSA_PMU_ERI_BASE |
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| 21 | 30 | /* Perf counter values */ |
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| 22 | | -#define XTENSA_PMU_PM(i) (0x1080 + (i) * 4) |
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| 31 | +#define XTENSA_PMU_PM(i) (XTENSA_PMU_ERI_BASE + 0x80 + (i) * 4) |
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| 23 | 32 | /* Perf counter control registers */ |
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| 24 | | -#define XTENSA_PMU_PMCTRL(i) (0x1100 + (i) * 4) |
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| 33 | +#define XTENSA_PMU_PMCTRL(i) (XTENSA_PMU_ERI_BASE + 0x100 + (i) * 4) |
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| 25 | 34 | /* Perf counter status registers */ |
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| 26 | | -#define XTENSA_PMU_PMSTAT(i) (0x1180 + (i) * 4) |
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| 35 | +#define XTENSA_PMU_PMSTAT(i) (XTENSA_PMU_ERI_BASE + 0x180 + (i) * 4) |
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| 27 | 36 | |
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| 28 | 37 | #define XTENSA_PMU_PMG_PMEN 0x1 |
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| 29 | 38 | |
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