重命名 AX88772C_eeprom/asix.c 为 asix_mac.c

hc

2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353

 kernel/arch/mips/mm/sc-mips.c
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@@ -12,7 +12,6 @@
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 #include <asm/bcache.h>
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 #include <asm/cacheops.h>
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 #include <asm/page.h>
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-#include <asm/pgtable.h>
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 #include <asm/mmu_context.h>
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 #include <asm/r4kcache.h>
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 #include <asm/mips-cps.h>
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@@ -147,7 +146,7 @@
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 	return 1;
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 }
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-static int __init mips_sc_probe_cm3(void)
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+static int mips_sc_probe_cm3(void)
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 {
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 	struct cpuinfo_mips *c = &current_cpu_data;
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 	unsigned long cfg = read_gcr_l2_config();
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@@ -181,7 +180,7 @@
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 	return 0;
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 }
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-static inline int __init mips_sc_probe(void)
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+static inline int mips_sc_probe(void)
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 {
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 	struct cpuinfo_mips *c = &current_cpu_data;
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 	unsigned int config1, config2;
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@@ -194,9 +193,10 @@
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 		return mips_sc_probe_cm3();
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 	/* Ignore anything but MIPSxx processors */
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-	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
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-			      MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
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-			      MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)))
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+	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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+			      MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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+			      MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
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+			      MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)))
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 		return 0;
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 	/* Does this MIPS32/MIPS64 CPU have a config2 register? */
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@@ -221,13 +221,28 @@
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 	else
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 		return 0;
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-	/*
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-	 * According to config2 it would be 5-ways, but that is contradicted
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-	 * by all documentation.
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-	 */
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-	if (current_cpu_type() == CPU_JZRISC &&
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-				mips_machtype == MACH_INGENIC_JZ4770)
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-		c->scache.ways = 4;
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+	if (current_cpu_type() == CPU_XBURST) {
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+		switch (mips_machtype) {
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+		/*
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+		 * According to config2 it would be 5-ways, but that is
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+		 * contradicted by all documentation.
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+		 */
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+		case MACH_INGENIC_JZ4770:
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+		case MACH_INGENIC_JZ4775:
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+			c->scache.ways = 4;
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+			break;
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+
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+		/*
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+		 * According to config2 it would be 5-ways and 512-sets,
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+		 * but that is contradicted by all documentation.
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+		 */
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+		case MACH_INGENIC_X1000:
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+		case MACH_INGENIC_X1000E:
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+			c->scache.sets = 256;
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+			c->scache.ways = 4;
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+			break;
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+		}
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+	}
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 	c->scache.waysize = c->scache.sets * c->scache.linesz;
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 	c->scache.waybit = __ffs(c->scache.waysize);