重命名 AX88772C_eeprom/asix.c 为 asix_mac.c

hc

2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353

 kernel/arch/mips/mm/c-tx39.c
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@@ -17,7 +17,6 @@
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 #include <asm/cacheops.h>
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 #include <asm/page.h>
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-#include <asm/pgtable.h>
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 #include <asm/mmu_context.h>
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 #include <asm/isadep.h>
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 #include <asm/io.h>
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@@ -169,8 +168,6 @@
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 {
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 	int exec = vma->vm_flags & VM_EXEC;
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 	struct mm_struct *mm = vma->vm_mm;
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-	pgd_t *pgdp;
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-	pud_t *pudp;
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 	pmd_t *pmdp;
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 	pte_t *ptep;
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@@ -182,10 +179,8 @@
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 		return;
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 	page &= PAGE_MASK;
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-	pgdp = pgd_offset(mm, page);
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-	pudp = pud_offset(pgdp, page);
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-	pmdp = pmd_offset(pudp, page);
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-	ptep = pte_offset(pmdp, page);
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+	pmdp = pmd_off(mm, page);
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+	ptep = pte_offset_kernel(pmdp, page);
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 	/*
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 	 * If the page isn't marked valid, the page cannot possibly be
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@@ -290,25 +285,6 @@
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 	}
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 }
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-static void tx39_flush_cache_sigtramp(unsigned long addr)
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-{
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-	unsigned long ic_lsize = current_cpu_data.icache.linesz;
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-	unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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-	unsigned long config;
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-	unsigned long flags;
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-
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-	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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-
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-	/* disable icache (set ICE#) */
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-	local_irq_save(flags);
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-	config = read_c0_conf();
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-	write_c0_conf(config & ~TX39_CONF_ICE);
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-	TX39_STOP_STREAMING();
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-	protected_flush_icache_line(addr & ~(ic_lsize - 1));
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-	write_c0_conf(config);
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-	local_irq_restore(flags);
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-}
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-
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 static __init void tx39_probe_cache(void)
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 {
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 	unsigned long config;
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@@ -368,7 +344,6 @@
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 		flush_icache_range	= (void *) tx39h_flush_icache_all;
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 		local_flush_icache_range = (void *) tx39h_flush_icache_all;
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-		flush_cache_sigtramp	= (void *) tx39h_flush_icache_all;
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 		local_flush_data_cache_page	= (void *) tx39h_flush_icache_all;
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 		flush_data_cache_page	= (void *) tx39h_flush_icache_all;
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@@ -397,7 +372,6 @@
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 		__flush_kernel_vmap_range = tx39_flush_kernel_vmap_range;
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-		flush_cache_sigtramp = tx39_flush_cache_sigtramp;
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 		local_flush_data_cache_page = local_tx39_flush_data_cache_page;
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 		flush_data_cache_page = tx39_flush_data_cache_page;
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@@ -429,9 +403,9 @@
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 	current_cpu_data.icache.waybit = 0;
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 	current_cpu_data.dcache.waybit = 0;
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-	printk("Primary instruction cache %ldkB, linesize %d bytes\n",
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+	pr_info("Primary instruction cache %ldkB, linesize %d bytes\n",
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 		icache_size >> 10, current_cpu_data.icache.linesz);
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-	printk("Primary data cache %ldkB, linesize %d bytes\n",
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+	pr_info("Primary data cache %ldkB, linesize %d bytes\n",
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 		dcache_size >> 10, current_cpu_data.dcache.linesz);
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 	build_clear_page();