.. | .. |
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5 | 5 | #include <asm/cpu-features.h> |
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6 | 6 | #include <asm/mipsregs.h> |
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7 | 7 | |
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8 | | -/* |
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9 | | - * MIPS doesn't need any special per-pte or per-vma handling, except |
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10 | | - * we need to flush cache for area to be unmapped. |
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11 | | - */ |
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12 | | -#define tlb_start_vma(tlb, vma) \ |
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13 | | - do { \ |
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14 | | - if (!tlb->fullmm) \ |
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15 | | - flush_cache_range(vma, vma->vm_start, vma->vm_end); \ |
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16 | | - } while (0) |
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17 | | -#define tlb_end_vma(tlb, vma) do { } while (0) |
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18 | | -#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) |
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19 | | - |
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20 | | -/* |
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21 | | - * .. because we flush the whole mm when it fills up. |
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22 | | - */ |
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23 | | -#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) |
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24 | | - |
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25 | 8 | #define _UNIQUE_ENTRYHI(base, idx) \ |
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26 | 9 | (((base) + ((idx) << (PAGE_SHIFT + 1))) | \ |
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27 | 10 | (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) |
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