重命名 AX88772C_eeprom/asix.c 为 asix_mac.c

hc

2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353

 kernel/arch/mips/include/asm/switch_to.h
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@@ -42,7 +42,7 @@
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  * inline to try to keep the overhead down. If we have been forced to run on
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  * a "CPU" with an FPU because of a previous high level of FP computation,
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  * but did not actually use the FPU during the most recent time-slice (CU1
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- * isn't set), we undo the restriction on cpus_allowed.
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+ * isn't set), we undo the restriction on cpus_mask.
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  *
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  * We're not calling set_cpus_allowed() here, because we have no need to
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  * force prompt migration - we're already switching the current CPU to a
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@@ -57,7 +57,7 @@
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 	    test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&		\
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 	    (!(KSTK_STATUS(prev) & ST0_CU1))) {				\
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 		clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);		\
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-		prev->cpus_allowed = prev->thread.user_cpus_allowed;	\
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+		prev->cpus_mask = prev->thread.user_cpus_allowed;	\
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 	}								\
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 	next->thread.emulated_fp = 0;					\
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 } while(0)
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@@ -67,11 +67,11 @@
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 #endif
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 /*
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- * Clear LLBit during context switches on MIPSr6 such that eretnc can be used
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+ * Clear LLBit during context switches on MIPSr5+ such that eretnc can be used
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  * unconditionally when returning to userland in entry.S.
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  */
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-#define __clear_r6_hw_ll_bit() do {					\
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-	if (cpu_has_mips_r6)						\
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+#define __clear_r5_hw_ll_bit() do {					\
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+	if (cpu_has_mips_r5 || cpu_has_mips_r6)				\
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 		write_c0_lladdr(0);					\
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 } while (0)
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@@ -84,7 +84,8 @@
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  * Check FCSR for any unmasked exceptions pending set with `ptrace',
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  * clear them and send a signal.
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  */
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-#define __sanitize_fcr31(next)						\
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+#ifdef CONFIG_MIPS_FP_SUPPORT
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+# define __sanitize_fcr31(next)						\
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 do {									\
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 	unsigned long fcr31 = mask_fcr31_x(next->thread.fpu.fcr31);	\
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 	void __user *pc;						\
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@@ -95,6 +96,9 @@
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 		force_fcr31_sig(fcr31, pc, next);			\
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 	}								\
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 } while (0)
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+#else
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+# define __sanitize_fcr31(next)
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+#endif
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 /*
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  * For newly created kernel threads switch_to() will return to
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@@ -113,6 +117,8 @@
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 		__restore_dsp(next);					\
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 	}								\
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 	if (cop2_present) {						\
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+		u32 status = read_c0_status();				\
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+									\
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 		set_c0_status(ST0_CU2);					\
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 		if ((KSTK_STATUS(prev) & ST0_CU2)) {			\
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 			if (cop2_lazy_restore)				\
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@@ -123,9 +129,9 @@
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 		    !cop2_lazy_restore) {				\
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 			cop2_restore(next);				\
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 		}							\
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-		clear_c0_status(ST0_CU2);				\
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+		write_c0_status(status);				\
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 	}								\
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-	__clear_r6_hw_ll_bit();						\
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+	__clear_r5_hw_ll_bit();						\
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 	__clear_software_ll_bit();					\
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 	if (cpu_has_userlocal)						\
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 		write_c0_userlocal(task_thread_info(next)->tp_value);	\