.. | .. |
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9 | 9 | #ifndef __ASM_LLSC_H |
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10 | 10 | #define __ASM_LLSC_H |
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11 | 11 | |
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| 12 | +#include <asm/isa-rev.h> |
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| 13 | + |
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12 | 14 | #if _MIPS_SZLONG == 32 |
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13 | | -#define SZLONG_LOG 5 |
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14 | | -#define SZLONG_MASK 31UL |
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15 | 15 | #define __LL "ll " |
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16 | 16 | #define __SC "sc " |
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17 | 17 | #define __INS "ins " |
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18 | 18 | #define __EXT "ext " |
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19 | 19 | #elif _MIPS_SZLONG == 64 |
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20 | | -#define SZLONG_LOG 6 |
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21 | | -#define SZLONG_MASK 63UL |
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22 | 20 | #define __LL "lld " |
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23 | 21 | #define __SC "scd " |
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24 | 22 | #define __INS "dins " |
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25 | 23 | #define __EXT "dext " |
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26 | 24 | #endif |
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27 | 25 | |
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| 26 | +/* |
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| 27 | + * Using a branch-likely instruction to check the result of an sc instruction |
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| 28 | + * works around a bug present in R10000 CPUs prior to revision 3.0 that could |
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| 29 | + * cause ll-sc sequences to execute non-atomically. |
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| 30 | + */ |
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| 31 | +#ifdef CONFIG_WAR_R10000_LLSC |
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| 32 | +# define __SC_BEQZ "beqzl " |
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| 33 | +#elif MIPS_ISA_REV >= 6 |
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| 34 | +# define __SC_BEQZ "beqzc " |
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| 35 | +#else |
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| 36 | +# define __SC_BEQZ "beqz " |
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| 37 | +#endif |
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| 38 | + |
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28 | 39 | #endif /* __ASM_LLSC_H */ |
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