重命名 AX88772C_eeprom/asix.c 为 asix_mac.c

hc

2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353

 kernel/arch/arm64/include/asm/mmu.h
..
..
@@ -1,90 +1,65 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (C) 2012 ARM Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #ifndef __ASM_MMU_H
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 #define __ASM_MMU_H
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+
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+#include <asm/cputype.h>
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9
 
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 #define MMCF_AARCH32	0x1	/* mm context flag for AArch32 executables */
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 #define USER_ASID_BIT	48
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 #define USER_ASID_FLAG	(UL(1) << USER_ASID_BIT)
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 #define TTBR_ASID_MASK	(UL(0xffff) << 48)
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14
 
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-#define BP_HARDEN_EL2_SLOTS 4
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-
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 #ifndef __ASSEMBLY__
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+
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+#include <linux/refcount.h>
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 typedef struct {
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 	atomic64_t	id;
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+#ifdef CONFIG_COMPAT
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+	void		*sigpage;
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+#endif
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+	refcount_t	pinned;
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 	void		*vdso;
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 	unsigned long	flags;
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 } mm_context_t;
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 /*
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- * This macro is only used by the TLBI code, which cannot race with an
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- * ASID change and therefore doesn't need to reload the counter using
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- * atomic64_read.
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+ * We use atomic64_read() here because the ASID for an 'mm_struct' can
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+ * be reallocated when scheduling one of its threads following a
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+ * rollover event (see new_context() and flush_context()). In this case,
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+ * a concurrent TLBI (e.g. via try_to_unmap_one() and ptep_clear_flush())
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+ * may use a stale ASID. This is fine in principle as the new ASID is
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+ * guaranteed to be clean in the TLB, but the TLBI routines have to take
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+ * care to handle the following race:
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+ *
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+ *    CPU 0                    CPU 1                          CPU 2
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+ *
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+ *    // ptep_clear_flush(mm)
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+ *    xchg_relaxed(pte, 0)
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+ *    DSB ISHST
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+ *    old = ASID(mm)
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+ *         |                                                  <rollover>
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+ *         |                   new = new_context(mm)
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+ *         \-----------------> atomic_set(mm->context.id, new)
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+ *                             cpu_switch_mm(mm)
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+ *                             // Hardware walk of pte using new ASID
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+ *    TLBI(old)
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+ *
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+ * In this scenario, the barrier on CPU 0 and the dependency on CPU 1
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+ * ensure that the page-table walker on CPU 1 *must* see the invalid PTE
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+ * written by CPU 0.
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  */
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-#define ASID(mm)	((mm)->context.id.counter & 0xffff)
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+#define ASID(mm)	(atomic64_read(&(mm)->context.id) & 0xffff)
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 static inline bool arm64_kernel_unmapped_at_el0(void)
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 {
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-	return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) &&
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-	       cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0);
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+	return cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0);
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 }
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-typedef void (*bp_hardening_cb_t)(void);
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-
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-struct bp_hardening_data {
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-	int			hyp_vectors_slot;
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-	bp_hardening_cb_t	fn;
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-};
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-
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-#if (defined(CONFIG_HARDEN_BRANCH_PREDICTOR) ||	\
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-     defined(CONFIG_HARDEN_EL2_VECTORS))
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-extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[];
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-extern atomic_t arm64_el2_vector_last_slot;
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-#endif  /* CONFIG_HARDEN_BRANCH_PREDICTOR || CONFIG_HARDEN_EL2_VECTORS */
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-
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-#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
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-DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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-
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-static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
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-{
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-	return this_cpu_ptr(&bp_hardening_data);
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-}
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-
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-static inline void arm64_apply_bp_hardening(void)
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-{
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-	struct bp_hardening_data *d;
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-
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-	if (!cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR))
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-		return;
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-
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-	d = arm64_get_bp_hardening_data();
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-	if (d->fn)
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-		d->fn();
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-}
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-#else
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-static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void)
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-{
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-	return NULL;
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-}
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-
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-static inline void arm64_apply_bp_hardening(void)	{ }
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-#endif	/* CONFIG_HARDEN_BRANCH_PREDICTOR */
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-
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+extern void arm64_memblock_init(void);
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 extern void paging_init(void);
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 extern void bootmem_init(void);
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 extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
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@@ -94,6 +69,10 @@
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 			       pgprot_t prot, bool page_mappings_only);
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 extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot);
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 extern void mark_linear_text_alias_ro(void);
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+extern bool kaslr_requires_kpti(void);
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+
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+#define INIT_MM_CONTEXT(name)	\
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+	.pgd = init_pg_dir,
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 #endif	/* !__ASSEMBLY__ */
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 #endif