~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,7 @@
8	8
9	9	#include <dt-bindings/gpio/gpio.h>
10	10	#include <dt-bindings/pinctrl/rockchip.h>
	11	+#include <dt-bindings/display/media-bus-format.h>
11	12	#include "rk3568.dtsi"
12	13	#include "rk3568-evb.dtsi"
13	14
..	..	@@ -17,7 +18,8 @@
17	18
18	19	rk_headset: rk-headset {
19	20	compatible = "rockchip_headset";
20		- headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
	21	+ headset_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>;
	22	+ spk_ctl_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;//AMP_SD_GPIO4_C2_3V3
21	23	pinctrl-names = "default";
22	24	pinctrl-0 = <&hp_det>;
23	25	};
..	..	@@ -32,15 +34,6 @@
32	34	vin-supply = <&vcc3v3_sys>;
33	35	};
34	36
35		- vcc3v3_vga: vcc3v3-vga {
36		- compatible = "regulator-fixed";
37		- regulator-name = "vcc3v3_vga";
38		- regulator-always-on;
39		- regulator-boot-on;
40		- gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
41		- enable-active-high;
42		- vin-supply = <&vcc3v3_sys>;
43		- };
44	37
45	38	pcie30_avdd0v9: pcie30-avdd0v9 {
46	39	compatible = "regulator-fixed";
..	..	@@ -67,7 +60,9 @@
67	60	regulator-name = "vcc3v3_pcie";
68	61	regulator-min-microvolt = <3300000>;
69	62	regulator-max-microvolt = <3300000>;
	63	+ regulator-always-on;
70	64	enable-active-high;
	65	+ regulator-boot-on;
71	66	gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
72	67	startup-delay-us = <5000>;
73	68	vin-supply = <&dc_12v>;
..	..	@@ -82,7 +77,7 @@
82	77	regulator-max-microvolt = <3300000>;
83	78	vin-supply = <&vcc5v0_sys>;
84	79	};
85		-
	80	+#if 0
86	81	vcc_camera: vcc-camera-regulator {
87	82	compatible = "regulator-fixed";
88	83	gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
..	..	@@ -92,43 +87,196 @@
92	87	enable-active-high;
93	88	regulator-always-on;
94	89	regulator-boot-on;
95		-
96	90	};
	91	+#endif
97	92
	93	+ leds: leds {
	94	+ compatible = "gpio-leds";
	95	+ sig_led: sig_led {
	96	+ gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
	97	+ default-state = "on";
	98	+ };
	99	+ };
	100	+
	101	+ leds: leds {
	102	+ compatible = "gpio-leds";
	103	+ err_led: err_led {
	104	+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
	105	+ default-state = "on";
	106	+ };
	107	+ };
	108	+
	109	+
	110	+ ndj_io_init {
	111	+ compatible = "nk_io_control";
	112	+ pinctrl-names = "default";
	113	+ pinctrl-0 = <&nk_io_gpio>;
	114	+
	115	+ //gpio_op0 = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
	116	+
	117	+ vcc_5v {
	118	+ gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
	119	+ gpio_function = <0>;
	120	+ };
	121	+
	122	+ vcc_12v {
	123	+ gpio_num = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
	124	+ gpio_function = <0>;
	125	+ };
	126	+
	127	+ vcc_3.3v {
	128	+ gpio_num = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
	129	+ gpio_function = <0>;
	130	+ };
	131	+
	132	+ ax88772_rst {
	133	+ gpio_num = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; //AX88772_RST_GPIO3_B5_3V3
	134	+ gpio_function = <3>;
	135	+ };
	136	+
	137	+ ax88631_rst {
	138	+ gpio_num = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; //AX88772_RST_GPIO3_B6_3V3
	139	+ gpio_function = <3>;
	140	+ };
	141	+
	142	+ hub_host3 {
	143	+ gpio_num = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
	144	+ gpio_function = <0>;
	145	+ };
	146	+
	147	+ wake_4g {
	148	+ gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; //4G_WAKEUP_GPIO01_B1_3V3
	149	+ gpio_function = <0>;
	150	+ };
	151	+
	152	+ air_mode_4g {
	153	+ gpio_num = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; //4G_AIR_MODE_GPIO01_B0_3V3
	154	+ gpio_function = <0>;
	155	+ };
	156	+
	157	+ reset_4g {
	158	+ gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; //4G_RST_GPIO01_B2_3V3
	159	+ gpio_function = <3>;
	160	+ };
	161	+
	162	+ en_4g {
	163	+ gpio_num = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
	164	+ gpio_function = <0>;
	165	+ };
	166	+
	167	+ //gpio99 {
	168	+ // gpio_num = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;//HP_EN_GPIO3_A6_3V3
	169	+ // gpio_function = <1>;
	170	+ //};
	171	+
	172	+ wifi_power_en {
	173	+ gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
	174	+ gpio_function = <0>;
	175	+ };
	176	+ #if 0
	177	+ do1 {
	178	+ gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
	179	+ gpio_function = <0>;
	180	+ };
	181	+
	182	+ do2 {
	183	+ gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
	184	+ gpio_function = <0>;
	185	+ };
	186	+
	187	+ do3 {
	188	+ gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
	189	+ gpio_function = <0>;
	190	+ };
	191	+
	192	+ do4 {
	193	+ gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
	194	+ gpio_function = <0>;
	195	+ };
	196	+
	197	+ do5 {
	198	+ gpio_num = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>;
	199	+ gpio_function = <0>;
	200	+ };
	201	+
	202	+ do6 {
	203	+ gpio_num = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>;
	204	+ gpio_function = <0>;
	205	+ };
	206	+
	207	+ do7 {
	208	+ gpio_num = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
	209	+ gpio_function = <0>;
	210	+ };
	211	+
	212	+ di1 {
	213	+ gpio_num = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
	214	+ gpio_function = <1>;
	215	+ };
	216	+ #endif
	217	+ };
	218	+#if 0
98	219	nk_io_init {
99	220	compatible = "nk_io_control";
100		- hub_host2_5v_gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; //USB_HOST_PWREN_H_GPIO0_A6
101		- usb_en_oc_gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; //USB_EN_OC_GPIO0_A5
102		- lcd_bk_en_gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
103		- lcd_pwblk_gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
104		- vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
	221	+// vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
105	222	hub_host2_5V_rest_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
106	223	hub_host3_5v_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
107		-// hub_host3_5V_rest_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
108	224	vcc_5v_io = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
109	225	vcc_12v_io = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
110	226	en_4g_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
111	227	reset_4g_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; //4G_RST_GPIO01_B2_3V3
112	228	air_mode_4g_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; //4G_AIR_MODE_GPIO01_B0_3V3
113	229	wake_4g_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; //4G_WAKEUP_GPIO01_B1_3V3
114		-
115		- edp_enable_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
116		- edp_gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; //7511_GPIO0-GPIO3_D2
117		- edp_gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; //7511_GPIO1-GPIO3_D3
118		- edp_gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; //7511_GPIO2-GPIO3_D4
119		- edp_gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; //7511_GPIO3-GPIO3_D5
120		- edp_reset = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
121		-// tp_reset = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
122		-// vddio_mipi = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
123		-
124		- wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
125		-
126		- // pinctrl-names = "default";
127		-// pinctrl-0 = <&nk_io_gpio>;
128		- nodka_lvds = <9>;
	230	+ hp_en_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;//HP_EN_GPIO3_A6_3V3
	231	+// spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3
	232	+ wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
	233	+// pcie_power_en_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;//PCIE_PWREN_H_GPIO0_D4
	234	+ pinctrl-names = "default";
	235	+ pinctrl-0 = <&nk_io_gpio>;
129	236	};
	237	+#endif
	238	+ panel: panel {
	239	+ compatible = "simple-panel";
	240	+ backlight = <&backlight>;
	241	+ power-supply = <&vcc3v3_lcd0_n>;
	242	+ enable-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; //LCD0_VDD_H_GPIO2_D4
	243	+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
	244	+ edp-bl-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
	245	+ edp-bl-en = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
	246	+ bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
	247	+ bpc = <8>;
	248	+ prepare-delay-ms = <200>;
	249	+ enable-delay-ms = <20>;
	250	+ lvds-gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; //7511_GPIO0-GPIO3_D2
	251	+ lvds-gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; //7511_GPIO1-GPIO3_D3
	252	+ lvds-gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; //7511_GPIO2-GPIO3_D4
	253	+ lvds-gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //7511_GPIO3-GPIO3_D5
	254	+ nodka-lvds = <15>;
130	255
131		-
	256	+ display-timings {
	257	+ native-mode = <&timing>;
	258	+ timing: timing {
	259	+ clock-frequency = <72500000>;
	260	+ hactive = <1280>;
	261	+ vactive = <800>;
	262	+ hfront-porch = <70>;
	263	+ hsync-len = <2>;
	264	+ hback-porch = <88>;
	265	+ vfront-porch = <7>;
	266	+ vsync-len = <4>;
	267	+ vback-porch = <17>;
	268	+ hsync-active = <21>;
	269	+ vsync-active = <0>;
	270	+ de-active = <0>;
	271	+ pixelclk-active = <0>;
	272	+ };
	273	+ };
	274	+ ports {
	275	+ panel_in_lvds: endpoint {
	276	+ remote-endpoint = <&lvds_out>;
	277	+ };
	278	+ };
	279	+ };
132	280	};
133	281
134	282	&combphy0_us {
..	..	@@ -144,11 +292,11 @@
144	292	};
145	293
146	294	&csi2_dphy_hw {
147		- status = "okay";
	295	+ status = "disabled";
148	296	};
149	297
150	298	&csi2_dphy0 {
151		- status = "okay";
	299	+ status = "disabled";
152	300
153	301	ports {
154	302	#address-cells = <1>;
..	..	@@ -191,8 +339,12 @@
191	339	* video_phy0 needs to be enabled
192	340	* when dsi0 is enabled
193	341	*/
	342	+&video_phy0 {
	343	+ status = "disabled";
	344	+};
	345	+
194	346	&dsi0 {
195		- status = "okay";
	347	+ status = "disabled";
196	348	};
197	349
198	350	&dsi0_in_vp0 {
..	..	@@ -200,7 +352,7 @@
200	352	};
201	353
202	354	&dsi0_in_vp1 {
203		- status = "okay";
	355	+ status = "disabled";
204	356	};
205	357
206	358	&dsi0_panel {
..	..	@@ -211,6 +363,10 @@
211	363	* video_phy1 needs to be enabled
212	364	* when dsi1 is enabled
213	365	*/
	366	+
	367	+&video_phy1 {
	368	+ status = "disabled";
	369	+};
214	370	&dsi1 {
215	371	status = "disabled";
216	372	};
..	..	@@ -224,31 +380,117 @@
224	380	};
225	381
226	382	&dsi1_panel {
227		- power-supply = <&vcc3v3_lcd1_n>;
	383	+// power-supply = <&vcc3v3_lcd1_n>; //MIPI_3V3EN_GPIO3_A3_d_3V3
	384	+ vddio-mipi = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; //MIPI_EN_1V8_GPIO3_A4_d_3V3
	385	+ reset-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>; //MIPI_RST_L_GPIO3_C7
	386	+ vcc-5v-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //VCC5_IO_EN_GPIO1_A4_3V3
	387	+ pinctrl-names = "default";
	388	+ pinctrl-0 = <&lcd1_rst_gpio>;
228	389	};
229	390
	391	+&route_dsi1 {
	392	+ status = "disabled";
	393	+ connect = <&vp1_out_dsi1>;
	394	+};
	395	+
	396	+
	397	+/*
	398	+* edp_start
	399	+*/
	400	+
230	401	&edp {
231		- hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
232		- status = "okay";
	402	+ force-hpd;
	403	+ status = "disabled";
233	404	};
234	405
235	406	&edp_phy {
236		- status = "okay";
	407	+ status = "disabled";
237	408	};
238	409
239	410	&edp_in_vp0 {
240		- status = "okay";
	411	+ status = "disabled";
241	412	};
242	413
243	414	&edp_in_vp1 {
	415	+ status = "disabled";
	416	+
	417	+};
	418	+
	419	+&route_edp {
	420	+ status = "disabled";
	421	+ connect = <&vp1_out_edp>;
	422	+};
	423	+
	424	+&route_edp {
244	425	status = "disabled";
245	426	};
	427	+
	428	+&lvds {
	429	+ status = "disabled";
	430	+ ports {
	431	+ port@1 {
	432	+ reg = <1>;
	433	+ lvds_out:endpoint {
	434	+ remote-endpoint = <&panel_in_lvds>;
	435	+ };
	436	+ };
	437	+ };
	438	+};
	439	+
	440	+&route_lvds{
	441	+ status = "okay";
	442	+ connect = <&vp1_out_lvds>;
	443	+};
	444	+
	445	+&lvds_in_vp1 {
	446	+ status = "disabled";
	447	+};
	448	+
	449	+/*
	450	+* edp_end
	451	+*/
	452	+
	453	+/*
	454	+* Hdmi_start
	455	+*/
	456	+
	457	+&hdmi {
	458	+ status = "okay";
	459	+ rockchip,phy-table =
	460	+ <92812500 0x8009 0x0000 0x0270>,
	461	+ <165000000 0x800b 0x0000 0x026d>,
	462	+ <185625000 0x800b 0x0000 0x01ed>,
	463	+ <297000000 0x800b 0x0000 0x01ad>,
	464	+ <594000000 0x8029 0x0000 0x0088>,
	465	+ <000000000 0x0000 0x0000 0x0000>;
	466	+};
	467	+
	468	+&route_hdmi {
	469	+ status = "okay";
	470	+ connect = <&vp0_out_hdmi>;
	471	+};
	472	+
	473	+&hdmi_in_vp0 {
	474	+ status = "okay";
	475	+};
	476	+
	477	+&hdmi_in_vp1 {
	478	+ status = "disabled";
	479	+};
	480	+
	481	+&hdmi_sound {
	482	+ status = "okay";
	483	+};
	484	+
	485	+/*
	486	+ * Hdmi_END
	487	+*/
246	488
247	489	&gmac0 {
248	490	phy-mode = "rgmii";
249	491	clock_in_out = "output";
250	492
251		- snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
	493	+ snps,reset-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
252	494	snps,reset-active-low;
253	495	/* Reset time is 20ms, 100ms for rtl8211f */
254	496	snps,reset-delays-us = <0 20000 100000>;
..	..	@@ -268,7 +510,9 @@
268	510	rx_delay = <0x2f>;
269	511
270	512	phy-handle = <&rgmii_phy0>;
	513	+
271	514	status = "disabled";
	515	+
272	516	};
273	517
274	518	&gmac1 {
..	..	@@ -302,9 +546,7 @@
302	546	* power-supply should switche to vcc3v3_lcd1_n
303	547	* when mipi panel is connected to dsi1.
304	548	*/
305		-&gt1x {
306		- power-supply = <&vcc3v3_lcd0_n>;
307		-};
	549	+
308	550
309	551	&i2c3 {
310	552	status = "okay";
..	..	@@ -320,13 +562,10 @@
320	562	compatible = "nk_mcu";
321	563	reg = <0x15>;
322	564	};
323		-
324		-
325		-
326	565	};
327	566
328	567	&i2c4 {
329		- status = "okay";
	568	+ status = "disabled";
330	569	gc8034: gc8034@37 {
331	570	compatible = "galaxycore,gc8034";
332	571	status = "okay";
..	..	@@ -338,7 +577,6 @@
338	577	reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>;
339	578	pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>;
340	579	rockchip,grf = <&grf>;
341		- power-domains = <&power RK3568_PD_VI>;
342	580	rockchip,camera-module-index = <0>;
343	581	rockchip,camera-module-facing = "back";
344	582	rockchip,camera-module-name = "RK-CMK-8M-2-v1";
..	..	@@ -372,7 +610,7 @@
372	610	};
373	611	};
374	612	ov5695: ov5695@36 {
375		- status = "okay";
	613	+ status = "disabled";
376	614	compatible = "ovti,ov5695";
377	615	reg = <0x36>;
378	616	clocks = <&cru CLK_CIF_OUT>;
..	..	@@ -395,6 +633,19 @@
395	633	};
396	634	};
397	635
	636	+&i2c5 {
	637	+ status = "okay";
	638	+
	639	+ hym8563: hym8563@51 {
	640	+ compatible = "haoyu,hym8563";
	641	+ reg = <0x51>;
	642	+ #clock-cells = <0>;
	643	+ clock-frequency = <32768>;
	644	+ clock-output-names = "xin32k";
	645	+ /* rtc_int is not connected */
	646	+ };
	647	+};
	648	+
398	649	&mdio0 {
399	650	rgmii_phy0: phy@0 {
400	651	compatible = "ethernet-phy-ieee802.3-c22";
..	..	@@ -409,73 +660,98 @@
409	660	};
410	661	};
411	662
412		-&video_phy0 {
413		- status = "okay";
414		-};
415	663
416		-&video_phy1 {
	664	+
	665	+&pcie30phy {
417	666	status = "disabled";
418	667	};
419	668
420		-&pcie30phy {
421		- status = "okay";
422		-};
423		-
424		-&pcie3x2 {
425		- reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
	669	+&pcie2x1 {
	670	+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
426	671	vpcie3v3-supply = <&vcc3v3_pcie>;
427	672	status = "okay";
428	673	};
429	674
430	675	&pinctrl {
431		- cam {
432		- camera_pwr: camera-pwr {
433		- rockchip,pins =
434		- /* camera power en */
435		- <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
436		- };
437		- };
	676	+// cam {
	677	+// camera_pwr: camera-pwr {
	678	+// rockchip,pins =
	679	+// /* camera power en */
	680	+// <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
	681	+// };
	682	+// };
438	683	headphone {
439	684	hp_det: hp-det {
440		- rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
	685	+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>,
	686	+ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
441	687	};
442	688	};
443	689
444	690	wireless-wlan {
445	691	wifi_host_wake_irq: wifi-host-wake-irq {
446		- rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>;
	692	+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
447	693	};
448	694	};
449	695
450	696	wireless-bluetooth {
451		- uart8_gpios: uart8-gpios {
452		- rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
	697	+ uart1_gpios: uart1-gpios {
	698	+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
453	699	};
454	700	};
455		-
456		- nk_io_gpio: nk_io_gpio_col{
457		- rockchip,pins =
458		- <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
459		- <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
460		- <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
461		- <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
462		- <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>,
463		- <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
464		- <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
465		- <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
	701	+
	702	+ lcd1 {
	703	+ lcd1_rst_gpio: lcd1-rst-gpio {
	704	+ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
	705	+ };
	706	+ };
	707	+
	708	+ nk_io_init{
	709	+ nk_io_gpio: nk-io-gpio{
	710	+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
	711	+ <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
	712	+ <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
	713	+ <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
	714	+ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
	715	+ <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
	716	+ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>,
	717	+ <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>,
	718	+ <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
	719	+ <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
	720	+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
	721	+ <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
	722	+ <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
	723	+ <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>,
	724	+ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
	725	+ <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>,
	726	+ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
	727	+ <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
	728	+ <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>,
	729	+ <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B0_u_3V3 DO1 8
	730	+ <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B3_u_3V3 DO2 11
	731	+ <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B4_u_3V3 DO3 12
	732	+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B5_u_3V3 DO4 13
	733	+ <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_B6_u_3V3 DO5 14
	734	+
	735	+ <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C0_d_3V3 DI1 16
	736	+ <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C1_d_3V3 DI2 17
	737	+ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C2_d_3V3 DI3 18
	738	+ <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C3_d_3V3 DI4 19
	739	+ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,//GPIO0_C5_d_3V3 DI5 21
	740	+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
	741	+ };
466	742	};
467	743	};
468	744
469	745	&rkisp {
470		- status = "okay";
	746	+ status = "disabled";
471	747	};
472	748
473	749	&rkisp_mmu {
474		- status = "okay";
	750	+ status = "disabled";
475	751	};
476	752
477	753	&rkisp_vir0 {
478		- status = "okay";
	754	+ status = "disabled";
479	755
480	756	port {
481	757	#address-cells = <1>;
..	..	@@ -488,34 +764,30 @@
488	764	};
489	765	};
490	766
491		-&route_dsi0 {
492		- status = "okay";
493		- connect = <&vp1_out_dsi0>;
494		-};
495	767
496		-&route_edp {
497		- status = "okay";
498		- connect = <&vp0_out_edp>;
499		-};
500	768
501	769	&sata2 {
502	770	status = "okay";
503	771	};
504	772
505	773	&sdmmc2 {
506		- max-frequency = <150000000>;
507		- supports-sdio;
508		- bus-width = <4>;
509		- disable-wp;
510		- cap-sd-highspeed;
511		- cap-sdio-irq;
512		- keep-power-in-suspend;
513		- mmc-pwrseq = <&sdio_pwrseq>;
514		- non-removable;
515		- pinctrl-names = "default";
516		- pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
517		- sd-uhs-sdr104;
518		- status = "okay";
	774	+ status = "disabled";
	775	+};
	776	+
	777	+&sdmmc1 {
	778	+ max-frequency = <150000000>;
	779	+ supports-sdio;
	780	+ bus-width = <4>;
	781	+ disable-wp;
	782	+ cap-sd-highspeed;
	783	+ cap-sdio-irq;
	784	+ keep-power-in-suspend;
	785	+ mmc-pwrseq = <&sdio_pwrseq>;
	786	+ non-removable;
	787	+ pinctrl-names = "default";
	788	+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
	789	+ sd-uhs-sdr104;
	790	+ status = "okay";
519	791	};
520	792
521	793	&spdif_8ch {
..	..	@@ -530,15 +802,6 @@
530	802	pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>;
531	803	};
532	804
533		-&vcc3v3_lcd0_n {
534		- gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
535		- enable-active-high;
536		-};
537		-
538		-&vcc3v3_lcd1_n {
539		- gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
540		- enable-active-high;
541		-};
542	805
543	806	&wireless_wlan {
544	807	pinctrl-names = "default";
..	..	@@ -551,12 +814,53 @@
551	814	clocks = <&rk809 1>;
552	815	clock-names = "ext_clock";
553	816	//wifi-bt-power-toggle;
554		- uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
	817	+ uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
555	818	pinctrl-names = "default", "rts_gpio";
556		- pinctrl-0 = <&uart8m0_rtsn>;
557		- pinctrl-1 = <&uart8_gpios>;
558		- BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
559		- BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
560		- BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
	819	+ pinctrl-0 = <&uart1m0_rtsn>;
	820	+ pinctrl-1 = <&uart1_gpios>;
	821	+ BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
	822	+ BT,wake_gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
	823	+ BT,wake_host_irq = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
	824	+ status = "disabled";
	825	+};
	826	+
	827	+&uart0 {
	828	+ status = "disabled";
	829	+};
	830	+
	831	+&uart1 {
	832	+ pinctrl-names = "default";
	833	+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
	834	+ status = "disabled";
	835	+};
	836	+
	837	+&uart3 {
561	838	status = "okay";
	839	+ pinctrl-0 = <&uart3m1_xfer>;
	840	+};
	841	+
	842	+&uart4 {
	843	+ status = "disabled";
	844	+ pinctrl-0 = <&uart4m1_xfer>;
	845	+};
	846	+
	847	+&uart5 {
	848	+ status = "okay";
	849	+ pinctrl-0 = <&uart5m1_xfer>;
	850	+};
	851	+
	852	+
	853	+&uart7 {
	854	+ status = "okay";
	855	+ pinctrl-0 = <&uart7m1_xfer>;
	856	+};
	857	+
	858	+&uart8 {
	859	+ status = "disabled";
	860	+ pinctrl-0 = <&uart8m1_xfer>;
	861	+};
	862	+
	863	+&uart9 {
	864	+ status = "disabled";
	865	+ pinctrl-0 = <&uart9m1_xfer>;
562	866	};