.. | .. |
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5 | 5 | * Device Tree file for Marvell Armada AP806. |
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6 | 6 | */ |
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7 | 7 | |
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8 | | -#include <dt-bindings/interrupt-controller/arm-gic.h> |
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9 | | - |
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10 | | -/dts-v1/; |
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| 8 | +#define AP_NAME ap806 |
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| 9 | +#include "armada-ap80x.dtsi" |
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11 | 10 | |
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12 | 11 | / { |
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13 | 12 | model = "Marvell Armada AP806"; |
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14 | 13 | compatible = "marvell,armada-ap806"; |
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15 | | - #address-cells = <2>; |
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16 | | - #size-cells = <2>; |
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| 14 | +}; |
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17 | 15 | |
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18 | | - aliases { |
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19 | | - serial0 = &uart0; |
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20 | | - serial1 = &uart1; |
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21 | | - gpio0 = &ap_gpio; |
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22 | | - spi0 = &spi0; |
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| 16 | +&ap_syscon0 { |
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| 17 | + ap_clk: clock { |
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| 18 | + compatible = "marvell,ap806-clock"; |
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| 19 | + #clock-cells = <1>; |
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23 | 20 | }; |
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| 21 | +}; |
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24 | 22 | |
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25 | | - psci { |
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26 | | - compatible = "arm,psci-0.2"; |
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27 | | - method = "smc"; |
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28 | | - }; |
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29 | | - |
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30 | | - reserved-memory { |
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31 | | - #address-cells = <2>; |
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32 | | - #size-cells = <2>; |
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33 | | - ranges; |
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34 | | - |
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35 | | - /* |
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36 | | - * This area matches the mapping done with a |
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37 | | - * mainline U-Boot, and should be updated by the |
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38 | | - * bootloader. |
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39 | | - */ |
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40 | | - |
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41 | | - psci-area@4000000 { |
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42 | | - reg = <0x0 0x4000000 0x0 0x200000>; |
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43 | | - no-map; |
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44 | | - }; |
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45 | | - }; |
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46 | | - |
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47 | | - ap806 { |
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48 | | - #address-cells = <2>; |
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49 | | - #size-cells = <2>; |
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50 | | - compatible = "simple-bus"; |
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51 | | - interrupt-parent = <&gic>; |
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52 | | - ranges; |
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53 | | - |
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54 | | - config-space@f0000000 { |
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55 | | - #address-cells = <1>; |
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56 | | - #size-cells = <1>; |
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57 | | - compatible = "simple-bus"; |
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58 | | - ranges = <0x0 0x0 0xf0000000 0x1000000>; |
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59 | | - |
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60 | | - gic: interrupt-controller@210000 { |
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61 | | - compatible = "arm,gic-400"; |
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62 | | - #interrupt-cells = <3>; |
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63 | | - #address-cells = <1>; |
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64 | | - #size-cells = <1>; |
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65 | | - ranges; |
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66 | | - interrupt-controller; |
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67 | | - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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68 | | - reg = <0x210000 0x10000>, |
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69 | | - <0x220000 0x20000>, |
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70 | | - <0x240000 0x20000>, |
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71 | | - <0x260000 0x20000>; |
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72 | | - |
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73 | | - gic_v2m0: v2m@280000 { |
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74 | | - compatible = "arm,gic-v2m-frame"; |
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75 | | - msi-controller; |
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76 | | - reg = <0x280000 0x1000>; |
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77 | | - arm,msi-base-spi = <160>; |
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78 | | - arm,msi-num-spis = <32>; |
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79 | | - }; |
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80 | | - gic_v2m1: v2m@290000 { |
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81 | | - compatible = "arm,gic-v2m-frame"; |
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82 | | - msi-controller; |
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83 | | - reg = <0x290000 0x1000>; |
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84 | | - arm,msi-base-spi = <192>; |
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85 | | - arm,msi-num-spis = <32>; |
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86 | | - }; |
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87 | | - gic_v2m2: v2m@2a0000 { |
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88 | | - compatible = "arm,gic-v2m-frame"; |
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89 | | - msi-controller; |
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90 | | - reg = <0x2a0000 0x1000>; |
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91 | | - arm,msi-base-spi = <224>; |
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92 | | - arm,msi-num-spis = <32>; |
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93 | | - }; |
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94 | | - gic_v2m3: v2m@2b0000 { |
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95 | | - compatible = "arm,gic-v2m-frame"; |
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96 | | - msi-controller; |
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97 | | - reg = <0x2b0000 0x1000>; |
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98 | | - arm,msi-base-spi = <256>; |
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99 | | - arm,msi-num-spis = <32>; |
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100 | | - }; |
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101 | | - }; |
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102 | | - |
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103 | | - timer { |
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104 | | - compatible = "arm,armv8-timer"; |
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105 | | - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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106 | | - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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107 | | - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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108 | | - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
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109 | | - }; |
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110 | | - |
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111 | | - pmu { |
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112 | | - compatible = "arm,cortex-a72-pmu"; |
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113 | | - interrupt-parent = <&pic>; |
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114 | | - interrupts = <17>; |
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115 | | - }; |
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116 | | - |
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117 | | - odmi: odmi@300000 { |
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118 | | - compatible = "marvell,odmi-controller"; |
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119 | | - interrupt-controller; |
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120 | | - msi-controller; |
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121 | | - marvell,odmi-frames = <4>; |
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122 | | - reg = <0x300000 0x4000>, |
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123 | | - <0x304000 0x4000>, |
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124 | | - <0x308000 0x4000>, |
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125 | | - <0x30C000 0x4000>; |
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126 | | - marvell,spi-base = <128>, <136>, <144>, <152>; |
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127 | | - }; |
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128 | | - |
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129 | | - gicp: gicp@3f0040 { |
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130 | | - compatible = "marvell,ap806-gicp"; |
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131 | | - reg = <0x3f0040 0x10>; |
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132 | | - marvell,spi-ranges = <64 64>, <288 64>; |
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133 | | - msi-controller; |
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134 | | - }; |
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135 | | - |
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136 | | - pic: interrupt-controller@3f0100 { |
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137 | | - compatible = "marvell,armada-8k-pic"; |
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138 | | - reg = <0x3f0100 0x10>; |
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139 | | - #interrupt-cells = <1>; |
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140 | | - interrupt-controller; |
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141 | | - interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; |
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142 | | - }; |
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143 | | - |
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144 | | - xor@400000 { |
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145 | | - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; |
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146 | | - reg = <0x400000 0x1000>, |
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147 | | - <0x410000 0x1000>; |
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148 | | - msi-parent = <&gic_v2m0>; |
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149 | | - clocks = <&ap_clk 3>; |
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150 | | - dma-coherent; |
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151 | | - }; |
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152 | | - |
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153 | | - xor@420000 { |
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154 | | - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; |
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155 | | - reg = <0x420000 0x1000>, |
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156 | | - <0x430000 0x1000>; |
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157 | | - msi-parent = <&gic_v2m0>; |
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158 | | - clocks = <&ap_clk 3>; |
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159 | | - dma-coherent; |
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160 | | - }; |
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161 | | - |
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162 | | - xor@440000 { |
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163 | | - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; |
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164 | | - reg = <0x440000 0x1000>, |
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165 | | - <0x450000 0x1000>; |
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166 | | - msi-parent = <&gic_v2m0>; |
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167 | | - clocks = <&ap_clk 3>; |
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168 | | - dma-coherent; |
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169 | | - }; |
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170 | | - |
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171 | | - xor@460000 { |
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172 | | - compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; |
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173 | | - reg = <0x460000 0x1000>, |
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174 | | - <0x470000 0x1000>; |
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175 | | - msi-parent = <&gic_v2m0>; |
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176 | | - clocks = <&ap_clk 3>; |
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177 | | - dma-coherent; |
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178 | | - }; |
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179 | | - |
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180 | | - spi0: spi@510600 { |
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181 | | - compatible = "marvell,armada-380-spi"; |
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182 | | - reg = <0x510600 0x50>; |
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183 | | - #address-cells = <1>; |
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184 | | - #size-cells = <0>; |
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185 | | - interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
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186 | | - clocks = <&ap_clk 3>; |
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187 | | - status = "disabled"; |
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188 | | - }; |
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189 | | - |
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190 | | - i2c0: i2c@511000 { |
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191 | | - compatible = "marvell,mv78230-i2c"; |
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192 | | - reg = <0x511000 0x20>; |
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193 | | - #address-cells = <1>; |
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194 | | - #size-cells = <0>; |
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195 | | - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
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196 | | - timeout-ms = <1000>; |
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197 | | - clocks = <&ap_clk 3>; |
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198 | | - status = "disabled"; |
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199 | | - }; |
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200 | | - |
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201 | | - uart0: serial@512000 { |
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202 | | - compatible = "snps,dw-apb-uart"; |
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203 | | - reg = <0x512000 0x100>; |
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204 | | - reg-shift = <2>; |
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205 | | - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
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206 | | - reg-io-width = <1>; |
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207 | | - clocks = <&ap_clk 3>; |
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208 | | - status = "disabled"; |
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209 | | - }; |
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210 | | - |
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211 | | - uart1: serial@512100 { |
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212 | | - compatible = "snps,dw-apb-uart"; |
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213 | | - reg = <0x512100 0x100>; |
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214 | | - reg-shift = <2>; |
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215 | | - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
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216 | | - reg-io-width = <1>; |
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217 | | - clocks = <&ap_clk 3>; |
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218 | | - status = "disabled"; |
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219 | | - |
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220 | | - }; |
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221 | | - |
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222 | | - watchdog: watchdog@610000 { |
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223 | | - compatible = "arm,sbsa-gwdt"; |
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224 | | - reg = <0x610000 0x1000>, <0x600000 0x1000>; |
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225 | | - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
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226 | | - }; |
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227 | | - |
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228 | | - ap_sdhci0: sdhci@6e0000 { |
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229 | | - compatible = "marvell,armada-ap806-sdhci"; |
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230 | | - reg = <0x6e0000 0x300>; |
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231 | | - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
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232 | | - clock-names = "core"; |
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233 | | - clocks = <&ap_clk 4>; |
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234 | | - dma-coherent; |
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235 | | - marvell,xenon-phy-slow-mode; |
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236 | | - status = "disabled"; |
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237 | | - }; |
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238 | | - |
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239 | | - ap_syscon: system-controller@6f4000 { |
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240 | | - compatible = "syscon", "simple-mfd"; |
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241 | | - reg = <0x6f4000 0x2000>; |
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242 | | - |
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243 | | - ap_clk: clock { |
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244 | | - compatible = "marvell,ap806-clock"; |
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245 | | - #clock-cells = <1>; |
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246 | | - }; |
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247 | | - |
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248 | | - ap_pinctrl: pinctrl { |
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249 | | - compatible = "marvell,ap806-pinctrl"; |
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250 | | - |
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251 | | - uart0_pins: uart0-pins { |
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252 | | - marvell,pins = "mpp11", "mpp19"; |
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253 | | - marvell,function = "uart0"; |
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254 | | - }; |
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255 | | - }; |
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256 | | - |
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257 | | - ap_gpio: gpio@1040 { |
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258 | | - compatible = "marvell,armada-8k-gpio"; |
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259 | | - offset = <0x1040>; |
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260 | | - ngpios = <20>; |
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261 | | - gpio-controller; |
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262 | | - #gpio-cells = <2>; |
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263 | | - gpio-ranges = <&ap_pinctrl 0 0 20>; |
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264 | | - }; |
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265 | | - }; |
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266 | | - |
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267 | | - ap_thermal: thermal@6f808c { |
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268 | | - compatible = "marvell,armada-ap806-thermal"; |
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269 | | - reg = <0x6f808c 0x4>, |
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270 | | - <0x6f8084 0x8>; |
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271 | | - }; |
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272 | | - }; |
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| 23 | +&ap_syscon1 { |
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| 24 | + cpu_clk: clock-cpu@278 { |
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| 25 | + compatible = "marvell,ap806-cpu-clock"; |
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| 26 | + clocks = <&ap_clk 0>, <&ap_clk 1>; |
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| 27 | + #clock-cells = <1>; |
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| 28 | + reg = <0x278 0xa30>; |
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273 | 29 | }; |
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274 | 30 | }; |
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