.. | .. |
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15 | 15 | #address-cells = <1>; |
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16 | 16 | #size-cells = <0>; |
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17 | 17 | |
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18 | | - cpu@0 { |
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| 18 | + cpu0: cpu@0 { |
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19 | 19 | device_type = "cpu"; |
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20 | | - compatible = "arm,cortex-a72", "arm,armv8"; |
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| 20 | + compatible = "arm,cortex-a72"; |
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21 | 21 | reg = <0x000>; |
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22 | 22 | enable-method = "psci"; |
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| 23 | + #cooling-cells = <2>; |
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| 24 | + clocks = <&cpu_clk 0>; |
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| 25 | + i-cache-size = <0xc000>; |
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| 26 | + i-cache-line-size = <64>; |
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| 27 | + i-cache-sets = <256>; |
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| 28 | + d-cache-size = <0x8000>; |
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| 29 | + d-cache-line-size = <64>; |
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| 30 | + d-cache-sets = <256>; |
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| 31 | + next-level-cache = <&l2>; |
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23 | 32 | }; |
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24 | | - cpu@1 { |
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| 33 | + cpu1: cpu@1 { |
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25 | 34 | device_type = "cpu"; |
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26 | | - compatible = "arm,cortex-a72", "arm,armv8"; |
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| 35 | + compatible = "arm,cortex-a72"; |
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27 | 36 | reg = <0x001>; |
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28 | 37 | enable-method = "psci"; |
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| 38 | + #cooling-cells = <2>; |
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| 39 | + clocks = <&cpu_clk 0>; |
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| 40 | + i-cache-size = <0xc000>; |
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| 41 | + i-cache-line-size = <64>; |
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| 42 | + i-cache-sets = <256>; |
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| 43 | + d-cache-size = <0x8000>; |
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| 44 | + d-cache-line-size = <64>; |
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| 45 | + d-cache-sets = <256>; |
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| 46 | + next-level-cache = <&l2>; |
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29 | 47 | }; |
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| 48 | + |
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| 49 | + l2: l2-cache { |
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| 50 | + compatible = "cache"; |
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| 51 | + cache-size = <0x80000>; |
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| 52 | + cache-line-size = <64>; |
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| 53 | + cache-sets = <512>; |
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| 54 | + }; |
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| 55 | + }; |
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| 56 | + |
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| 57 | + thermal-zones { |
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| 58 | + /delete-node/ ap-thermal-cpu2; |
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| 59 | + /delete-node/ ap-thermal-cpu3; |
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30 | 60 | }; |
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31 | 61 | }; |
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