重命名 AX88772C_eeprom/asix.c 为 asix_mac.c

hc

2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353

 kernel/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
..
..
@@ -19,44 +19,44 @@
19
19
 /*
20
20
  * Instantiate the master CP110
21
21
  */
22
-#define CP110_NAME		cp0
23
-#define CP110_BASE		f2000000
24
-#define CP110_PCIE_IO_BASE	0xf9000000
25
-#define CP110_PCIE_MEM_BASE	0xf6000000
26
-#define CP110_PCIE0_BASE	f2600000
27
-#define CP110_PCIE1_BASE	f2620000
28
-#define CP110_PCIE2_BASE	f2640000
22
+#define CP11X_NAME		cp0
23
+#define CP11X_BASE		f2000000
24
+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
26
+#define CP11X_PCIE0_BASE	f2600000
27
+#define CP11X_PCIE1_BASE	f2620000
28
+#define CP11X_PCIE2_BASE	f2640000
29
29
 
30
30
 #include "armada-cp110.dtsi"
31
31
 
32
-#undef CP110_NAME
33
-#undef CP110_BASE
34
-#undef CP110_PCIE_IO_BASE
35
-#undef CP110_PCIE_MEM_BASE
36
-#undef CP110_PCIE0_BASE
37
-#undef CP110_PCIE1_BASE
38
-#undef CP110_PCIE2_BASE
32
+#undef CP11X_NAME
33
+#undef CP11X_BASE
34
+#undef CP11X_PCIEx_MEM_BASE
35
+#undef CP11X_PCIEx_MEM_SIZE
36
+#undef CP11X_PCIE0_BASE
37
+#undef CP11X_PCIE1_BASE
38
+#undef CP11X_PCIE2_BASE
39
39
 
40
40
 /*
41
41
  * Instantiate the slave CP110
42
42
  */
43
-#define CP110_NAME		cp1
44
-#define CP110_BASE		f4000000
45
-#define CP110_PCIE_IO_BASE	0xfd000000
46
-#define CP110_PCIE_MEM_BASE	0xfa000000
47
-#define CP110_PCIE0_BASE	f4600000
48
-#define CP110_PCIE1_BASE	f4620000
49
-#define CP110_PCIE2_BASE	f4640000
43
+#define CP11X_NAME		cp1
44
+#define CP11X_BASE		f4000000
45
+#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
47
+#define CP11X_PCIE0_BASE	f4600000
48
+#define CP11X_PCIE1_BASE	f4620000
49
+#define CP11X_PCIE2_BASE	f4640000
50
50
 
51
51
 #include "armada-cp110.dtsi"
52
52
 
53
-#undef CP110_NAME
54
-#undef CP110_BASE
55
-#undef CP110_PCIE_IO_BASE
56
-#undef CP110_PCIE_MEM_BASE
57
-#undef CP110_PCIE0_BASE
58
-#undef CP110_PCIE1_BASE
59
-#undef CP110_PCIE2_BASE
53
+#undef CP11X_NAME
54
+#undef CP11X_BASE
55
+#undef CP11X_PCIEx_MEM_BASE
56
+#undef CP11X_PCIEx_MEM_SIZE
57
+#undef CP11X_PCIE0_BASE
58
+#undef CP11X_PCIE1_BASE
59
+#undef CP11X_PCIE2_BASE
60
60
 
61
61
 /* The 80x0 has two CP blocks, but uses only one block from each. */
62
62
 &cp1_gpio1 {