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2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353 
 kernel/arch/arm64/boot/dts/hisilicon/hi6220-coresight.dtsi
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * dtsi file for Hisilicon Hi6220 coresight
34  *
....@@ -5,37 +6,28 @@
56  *
67  * Author: Pengcheng Li <lipengcheng8@huawei.com>
78  *         Leo Yan <leo.yan@linaro.org>
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License version 2 as
11
- * publishhed by the Free Software Foundation.
12
- *
139  */
1410 
1511 / {
1612 	soc {
1713 		funnel@f6401000 {
18
-			compatible = "arm,coresight-funnel", "arm,primecell";
14
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1915 			reg = <0 0xf6401000 0 0x1000>;
2016 			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
2117 			clock-names = "apb_pclk";
2218 
23
-			ports {
24
-				#address-cells = <1>;
25
-				#size-cells = <0>;
26
-
27
-				port@0 {
28
-					reg = <0>;
19
+			out-ports {
20
+				port {
2921 					soc_funnel_out: endpoint {
3022 						remote-endpoint =
3123 							<&etf_in>;
3224 					};
3325 				};
26
+			};
3427 
35
-				port@1 {
36
-					reg = <0>;
28
+			in-ports {
29
+				port {
3730 					soc_funnel_in: endpoint {
38
-						slave-mode;
3931 						remote-endpoint =
4032 							<&acpu_funnel_out>;
4133 					};
....@@ -49,21 +41,17 @@
4941 			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
5042 			clock-names = "apb_pclk";
5143 
52
-			ports {
53
-				#address-cells = <1>;
54
-				#size-cells = <0>;
55
-
56
-				port@0 {
57
-					reg = <0>;
44
+			in-ports {
45
+				port {
5846 					etf_in: endpoint {
59
-						slave-mode;
6047 						remote-endpoint =
6148 							<&soc_funnel_out>;
6249 					};
6350 				};
51
+			};
6452 
65
-				port@1 {
66
-					reg = <0>;
53
+			out-ports {
54
+				port {
6755 					etf_out: endpoint {
6856 						remote-endpoint =
6957 							<&replicator_in>;
....@@ -73,24 +61,24 @@
7361 		};
7462 
7563 		replicator {
76
-			compatible = "arm,coresight-replicator";
64
+			compatible = "arm,coresight-static-replicator";
7765 			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
7866 			clock-names = "apb_pclk";
7967 
80
-			ports {
81
-				#address-cells = <1>;
82
-				#size-cells = <0>;
83
-
84
-				port@0 {
85
-					reg = <0>;
68
+			in-ports {
69
+				port {
8670 					replicator_in: endpoint {
87
-						slave-mode;
8871 						remote-endpoint =
8972 							<&etf_out>;
9073 					};
9174 				};
75
+			};
9276 
93
-				port@1 {
77
+			out-ports {
78
+				#address-cells = <1>;
79
+				#size-cells = <0>;
80
+
81
+				port@0 {
9482 					reg = <0>;
9583 					replicator_out0: endpoint {
9684 						remote-endpoint =
....@@ -98,7 +86,7 @@
9886 					};
9987 				};
10088 
101
-				port@2 {
89
+				port@1 {
10290 					reg = <1>;
10391 					replicator_out1: endpoint {
10492 						remote-endpoint =
....@@ -114,14 +102,9 @@
114102 			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
115103 			clock-names = "apb_pclk";
116104 
117
-			ports {
118
-				#address-cells = <1>;
119
-				#size-cells = <0>;
120
-
121
-				port@0 {
122
-					reg = <0>;
105
+			in-ports {
106
+				port {
123107 					etr_in: endpoint {
124
-						slave-mode;
125108 						remote-endpoint =
126109 							<&replicator_out0>;
127110 					};
....@@ -135,14 +118,9 @@
135118 			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
136119 			clock-names = "apb_pclk";
137120 
138
-			ports {
139
-				#address-cells = <1>;
140
-				#size-cells = <0>;
141
-
142
-				port@0 {
143
-					reg = <0>;
121
+			in-ports {
122
+				port {
144123 					tpiu_in: endpoint {
145
-						slave-mode;
146124 						remote-endpoint =
147125 							<&replicator_out1>;
148126 					};
....@@ -151,90 +129,83 @@
151129 		};
152130 
153131 		funnel@f6501000 {
154
-			compatible = "arm,coresight-funnel", "arm,primecell";
132
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
155133 			reg = <0 0xf6501000 0 0x1000>;
156134 			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
157135 			clock-names = "apb_pclk";
158136 
159
-			ports {
160
-				#address-cells = <1>;
161
-				#size-cells = <0>;
162
-
163
-				port@0 {
164
-					reg = <0>;
137
+			out-ports {
138
+				port {
165139 					acpu_funnel_out: endpoint {
166140 						remote-endpoint =
167141 							<&soc_funnel_in>;
168142 					};
169143 				};
144
+			};
170145 
171
-				port@1 {
146
+			in-ports {
147
+				#address-cells = <1>;
148
+				#size-cells = <0>;
149
+
150
+				port@0 {
172151 					reg = <0>;
173152 					acpu_funnel_in0: endpoint {
174
-						slave-mode;
175153 						remote-endpoint =
176154 							<&etm0_out>;
177155 					};
178156 				};
179157 
180
-				port@2 {
158
+				port@1 {
181159 					reg = <1>;
182160 					acpu_funnel_in1: endpoint {
183
-						slave-mode;
184161 						remote-endpoint =
185162 							<&etm1_out>;
186163 					};
187164 				};
188165 
189
-				port@3 {
166
+				port@2 {
190167 					reg = <2>;
191168 					acpu_funnel_in2: endpoint {
192
-						slave-mode;
193169 						remote-endpoint =
194170 							<&etm2_out>;
195171 					};
196172 				};
197173 
198
-				port@4 {
174
+				port@3 {
199175 					reg = <3>;
200176 					acpu_funnel_in3: endpoint {
201
-						slave-mode;
202177 						remote-endpoint =
203178 							<&etm3_out>;
204179 					};
205180 				};
206181 
207
-				port@5 {
182
+				port@4 {
208183 					reg = <4>;
209184 					acpu_funnel_in4: endpoint {
210
-						slave-mode;
211185 						remote-endpoint =
212186 							<&etm4_out>;
213187 					};
214188 				};
215189 
216
-				port@6 {
190
+				port@5 {
217191 					reg = <5>;
218192 					acpu_funnel_in5: endpoint {
219
-						slave-mode;
220193 						remote-endpoint =
221194 							<&etm5_out>;
222195 					};
223196 				};
224197 
225
-				port@7 {
198
+				port@6 {
226199 					reg = <6>;
227200 					acpu_funnel_in6: endpoint {
228
-						slave-mode;
229201 						remote-endpoint =
230202 							<&etm6_out>;
231203 					};
232204 				};
233205 
234
-				port@8 {
206
+				port@7 {
235207 					reg = <7>;
236208 					acpu_funnel_in7: endpoint {
237
-						slave-mode;
238209 						remote-endpoint =
239210 							<&etm7_out>;
240211 					};
....@@ -242,7 +213,7 @@
242213 			};
243214 		};
244215 
245
-		etm@f659c000 {
216
+		etm0: etm@f659c000 {
246217 			compatible = "arm,coresight-etm4x", "arm,primecell";
247218 			reg = <0 0xf659c000 0 0x1000>;
248219 
....@@ -251,15 +222,17 @@
251222 
252223 			cpu = <&cpu0>;
253224 
254
-			port {
255
-				etm0_out: endpoint {
256
-					remote-endpoint =
257
-						<&acpu_funnel_in0>;
225
+			out-ports {
226
+				port {
227
+					etm0_out: endpoint {
228
+						remote-endpoint =
229
+							<&acpu_funnel_in0>;
230
+					};
258231 				};
259232 			};
260233 		};
261234 
262
-		etm@f659d000 {
235
+		etm1: etm@f659d000 {
263236 			compatible = "arm,coresight-etm4x", "arm,primecell";
264237 			reg = <0 0xf659d000 0 0x1000>;
265238 
....@@ -268,15 +241,17 @@
268241 
269242 			cpu = <&cpu1>;
270243 
271
-			port {
272
-				etm1_out: endpoint {
273
-					remote-endpoint =
274
-						<&acpu_funnel_in1>;
244
+			out-ports {
245
+				port {
246
+					etm1_out: endpoint {
247
+						remote-endpoint =
248
+							<&acpu_funnel_in1>;
249
+					};
275250 				};
276251 			};
277252 		};
278253 
279
-		etm@f659e000 {
254
+		etm2: etm@f659e000 {
280255 			compatible = "arm,coresight-etm4x", "arm,primecell";
281256 			reg = <0 0xf659e000 0 0x1000>;
282257 
....@@ -285,15 +260,17 @@
285260 
286261 			cpu = <&cpu2>;
287262 
288
-			port {
289
-				etm2_out: endpoint {
290
-					remote-endpoint =
291
-						<&acpu_funnel_in2>;
263
+			out-ports {
264
+				port {
265
+					etm2_out: endpoint {
266
+						remote-endpoint =
267
+							<&acpu_funnel_in2>;
268
+					};
292269 				};
293270 			};
294271 		};
295272 
296
-		etm@f659f000 {
273
+		etm3: etm@f659f000 {
297274 			compatible = "arm,coresight-etm4x", "arm,primecell";
298275 			reg = <0 0xf659f000 0 0x1000>;
299276 
....@@ -302,15 +279,17 @@
302279 
303280 			cpu = <&cpu3>;
304281 
305
-			port {
306
-				etm3_out: endpoint {
307
-					remote-endpoint =
308
-						<&acpu_funnel_in3>;
282
+			out-ports {
283
+				port {
284
+					etm3_out: endpoint {
285
+						remote-endpoint =
286
+							<&acpu_funnel_in3>;
287
+					};
309288 				};
310289 			};
311290 		};
312291 
313
-		etm@f65dc000 {
292
+		etm4: etm@f65dc000 {
314293 			compatible = "arm,coresight-etm4x", "arm,primecell";
315294 			reg = <0 0xf65dc000 0 0x1000>;
316295 
....@@ -319,15 +298,17 @@
319298 
320299 			cpu = <&cpu4>;
321300 
322
-			port {
323
-				etm4_out: endpoint {
324
-					remote-endpoint =
325
-						<&acpu_funnel_in4>;
301
+			out-ports {
302
+				port {
303
+					etm4_out: endpoint {
304
+						remote-endpoint =
305
+							<&acpu_funnel_in4>;
306
+					};
326307 				};
327308 			};
328309 		};
329310 
330
-		etm@f65dd000 {
311
+		etm5: etm@f65dd000 {
331312 			compatible = "arm,coresight-etm4x", "arm,primecell";
332313 			reg = <0 0xf65dd000 0 0x1000>;
333314 
....@@ -336,15 +317,17 @@
336317 
337318 			cpu = <&cpu5>;
338319 
339
-			port {
340
-				etm5_out: endpoint {
341
-					remote-endpoint =
342
-						<&acpu_funnel_in5>;
320
+			out-ports {
321
+				port {
322
+					etm5_out: endpoint {
323
+						remote-endpoint =
324
+							<&acpu_funnel_in5>;
325
+					};
343326 				};
344327 			};
345328 		};
346329 
347
-		etm@f65de000 {
330
+		etm6: etm@f65de000 {
348331 			compatible = "arm,coresight-etm4x", "arm,primecell";
349332 			reg = <0 0xf65de000 0 0x1000>;
350333 
....@@ -353,15 +336,17 @@
353336 
354337 			cpu = <&cpu6>;
355338 
356
-			port {
357
-				etm6_out: endpoint {
358
-					remote-endpoint =
359
-						<&acpu_funnel_in6>;
339
+			out-ports {
340
+				port {
341
+					etm6_out: endpoint {
342
+						remote-endpoint =
343
+							<&acpu_funnel_in6>;
344
+					};
360345 				};
361346 			};
362347 		};
363348 
364
-		etm@f65df000 {
349
+		etm7: etm@f65df000 {
365350 			compatible = "arm,coresight-etm4x", "arm,primecell";
366351 			reg = <0 0xf65df000 0 0x1000>;
367352 
....@@ -370,12 +355,128 @@
370355 
371356 			cpu = <&cpu7>;
372357 
373
-			port {
374
-				etm7_out: endpoint {
375
-					remote-endpoint =
376
-						<&acpu_funnel_in7>;
358
+			out-ports {
359
+				port {
360
+					etm7_out: endpoint {
361
+						remote-endpoint =
362
+							<&acpu_funnel_in7>;
363
+					};
377364 				};
378365 			};
379366 		};
367
+
368
+		/* System CTIs */
369
+		/* CTI 0 - TMC and TPIU connections */
370
+		cti@f6403000 {
371
+			compatible = "arm,coresight-cti", "arm,primecell";
372
+			reg = <0 0xf6403000 0 0x1000>;
373
+
374
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
375
+			clock-names = "apb_pclk";
376
+		};
377
+
378
+		/* CTI - CPU-0 */
379
+		cti@f6598000 {
380
+			compatible = "arm,coresight-cti-v8-arch",
381
+				     "arm,coresight-cti", "arm,primecell";
382
+			reg = <0 0xf6598000 0 0x1000>;
383
+
384
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
385
+			clock-names = "apb_pclk";
386
+
387
+			cpu = <&cpu0>;
388
+			arm,cs-dev-assoc = <&etm0>;
389
+		};
390
+
391
+		/* CTI - CPU-1 */
392
+		cti@f6599000 {
393
+			compatible = "arm,coresight-cti-v8-arch",
394
+				     "arm,coresight-cti", "arm,primecell";
395
+			reg = <0 0xf6599000 0 0x1000>;
396
+
397
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
398
+			clock-names = "apb_pclk";
399
+
400
+			cpu = <&cpu1>;
401
+			arm,cs-dev-assoc = <&etm1>;
402
+		};
403
+
404
+		/* CTI - CPU-2 */
405
+		cti@f659a000 {
406
+			compatible = "arm,coresight-cti-v8-arch",
407
+				     "arm,coresight-cti", "arm,primecell";
408
+			reg = <0 0xf659a000 0 0x1000>;
409
+
410
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
411
+			clock-names = "apb_pclk";
412
+
413
+			cpu = <&cpu2>;
414
+			arm,cs-dev-assoc = <&etm2>;
415
+		};
416
+
417
+		/* CTI - CPU-3 */
418
+		cti@f659b000 {
419
+			compatible = "arm,coresight-cti-v8-arch",
420
+				     "arm,coresight-cti", "arm,primecell";
421
+			reg = <0 0xf659b000 0 0x1000>;
422
+
423
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
424
+			clock-names = "apb_pclk";
425
+
426
+			cpu = <&cpu3>;
427
+			arm,cs-dev-assoc = <&etm3>;
428
+		};
429
+
430
+		/* CTI - CPU-4 */
431
+		cti@f65d8000 {
432
+			compatible = "arm,coresight-cti-v8-arch",
433
+				     "arm,coresight-cti", "arm,primecell";
434
+			reg = <0 0xf65d8000 0 0x1000>;
435
+
436
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
437
+			clock-names = "apb_pclk";
438
+
439
+			cpu = <&cpu4>;
440
+			arm,cs-dev-assoc = <&etm4>;
441
+		};
442
+
443
+		/* CTI - CPU-5 */
444
+		cti@f65d9000 {
445
+			compatible = "arm,coresight-cti-v8-arch",
446
+				     "arm,coresight-cti", "arm,primecell";
447
+			reg = <0 0xf65d9000 0 0x1000>;
448
+
449
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
450
+			clock-names = "apb_pclk";
451
+
452
+			cpu = <&cpu5>;
453
+			arm,cs-dev-assoc = <&etm5>;
454
+		};
455
+
456
+		/* CTI - CPU-6 */
457
+		cti@f65da000 {
458
+			compatible = "arm,coresight-cti-v8-arch",
459
+				     "arm,coresight-cti", "arm,primecell";
460
+			reg = <0 0xf65da000 0 0x1000>;
461
+
462
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
463
+			clock-names = "apb_pclk";
464
+
465
+			cpu = <&cpu6>;
466
+			arm,cs-dev-assoc = <&etm6>;
467
+		};
468
+
469
+		/* CTI - CPU-7 */
470
+		cti@f65db000 {
471
+			compatible = "arm,coresight-cti-v8-arch",
472
+				     "arm,coresight-cti", "arm,primecell";
473
+			reg = <0 0xf65db000 0 0x1000>;
474
+
475
+			clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
476
+			clock-names = "apb_pclk";
477
+
478
+			cpu = <&cpu7>;
479
+			arm,cs-dev-assoc = <&etm7>;
480
+		};
380481 	};
381482 };