forked from ~ljy/RK356X_SDK_RELEASE
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2024-09-20 a36159eec6ca17402b0e146b86efaf76568dc353 
 kernel/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
....@@ -3,13 +3,14 @@
33  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
44  */
55 
6
-#include <dt-bindings/gpio/gpio.h>
7
-#include <dt-bindings/interrupt-controller/irq.h>
8
-#include <dt-bindings/interrupt-controller/arm-gic.h>
6
+#include <dt-bindings/clock/axg-aoclkc.h>
97 #include <dt-bindings/clock/axg-audio-clkc.h>
108 #include <dt-bindings/clock/axg-clkc.h>
11
-#include <dt-bindings/clock/axg-aoclkc.h>
9
+#include <dt-bindings/gpio/gpio.h>
1210 #include <dt-bindings/gpio/meson-axg-gpio.h>
11
+#include <dt-bindings/interrupt-controller/irq.h>
12
+#include <dt-bindings/interrupt-controller/arm-gic.h>
13
+#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
1314 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
1415 
1516 / {
....@@ -18,6 +19,111 @@
1819 	interrupt-parent = <&gic>;
1920 	#address-cells = <2>;
2021 	#size-cells = <2>;
22
+
23
+	tdmif_a: audio-controller-0 {
24
+		compatible = "amlogic,axg-tdm-iface";
25
+		#sound-dai-cells = <0>;
26
+		sound-name-prefix = "TDM_A";
27
+		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
28
+			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
29
+			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
30
+		clock-names = "mclk", "sclk", "lrclk";
31
+		status = "disabled";
32
+	};
33
+
34
+	tdmif_b: audio-controller-1 {
35
+		compatible = "amlogic,axg-tdm-iface";
36
+		#sound-dai-cells = <0>;
37
+		sound-name-prefix = "TDM_B";
38
+		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
39
+			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
40
+			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
41
+		clock-names = "mclk", "sclk", "lrclk";
42
+		status = "disabled";
43
+	};
44
+
45
+	tdmif_c: audio-controller-2 {
46
+		compatible = "amlogic,axg-tdm-iface";
47
+		#sound-dai-cells = <0>;
48
+		sound-name-prefix = "TDM_C";
49
+		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
50
+			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
51
+			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
52
+		clock-names = "mclk", "sclk", "lrclk";
53
+		status = "disabled";
54
+	};
55
+
56
+	arm-pmu {
57
+		compatible = "arm,cortex-a53-pmu";
58
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
59
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
60
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
61
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
62
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
63
+	};
64
+
65
+	cpus {
66
+		#address-cells = <0x2>;
67
+		#size-cells = <0x0>;
68
+
69
+		cpu0: cpu@0 {
70
+			device_type = "cpu";
71
+			compatible = "arm,cortex-a53";
72
+			reg = <0x0 0x0>;
73
+			enable-method = "psci";
74
+			next-level-cache = <&l2>;
75
+			clocks = <&scpi_dvfs 0>;
76
+		};
77
+
78
+		cpu1: cpu@1 {
79
+			device_type = "cpu";
80
+			compatible = "arm,cortex-a53";
81
+			reg = <0x0 0x1>;
82
+			enable-method = "psci";
83
+			next-level-cache = <&l2>;
84
+			clocks = <&scpi_dvfs 0>;
85
+		};
86
+
87
+		cpu2: cpu@2 {
88
+			device_type = "cpu";
89
+			compatible = "arm,cortex-a53";
90
+			reg = <0x0 0x2>;
91
+			enable-method = "psci";
92
+			next-level-cache = <&l2>;
93
+			clocks = <&scpi_dvfs 0>;
94
+		};
95
+
96
+		cpu3: cpu@3 {
97
+			device_type = "cpu";
98
+			compatible = "arm,cortex-a53";
99
+			reg = <0x0 0x3>;
100
+			enable-method = "psci";
101
+			next-level-cache = <&l2>;
102
+			clocks = <&scpi_dvfs 0>;
103
+		};
104
+
105
+		l2: l2-cache0 {
106
+			compatible = "cache";
107
+		};
108
+	};
109
+
110
+	sm: secure-monitor {
111
+		compatible = "amlogic,meson-gxbb-sm";
112
+	};
113
+
114
+	efuse: efuse {
115
+		compatible = "amlogic,meson-gxbb-efuse";
116
+		clocks = <&clkc CLKID_EFUSE>;
117
+		#address-cells = <1>;
118
+		#size-cells = <1>;
119
+		read-only;
120
+		secure-monitor = <&sm>;
121
+	};
122
+
123
+	psci {
124
+		compatible = "arm,psci-1.0";
125
+		method = "smc";
126
+	};
21127 
22128 	reserved-memory {
23129 		#address-cells = <2>;
....@@ -37,118 +143,26 @@
37143 		};
38144 	};
39145 
40
-	cpus {
41
-		#address-cells = <0x2>;
42
-		#size-cells = <0x0>;
146
+	scpi {
147
+		compatible = "arm,scpi-pre-1.0";
148
+		mboxes = <&mailbox 1 &mailbox 2>;
149
+		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
43150 
44
-		cpu0: cpu@0 {
45
-			device_type = "cpu";
46
-			compatible = "arm,cortex-a53", "arm,armv8";
47
-			reg = <0x0 0x0>;
48
-			enable-method = "psci";
49
-			next-level-cache = <&l2>;
151
+		scpi_clocks: clocks {
152
+			compatible = "arm,scpi-clocks";
153
+
154
+			scpi_dvfs: clocks-0 {
155
+				compatible = "arm,scpi-dvfs-clocks";
156
+				#clock-cells = <1>;
157
+				clock-indices = <0>;
158
+				clock-output-names = "vcpu";
159
+			};
50160 		};
51161 
52
-		cpu1: cpu@1 {
53
-			device_type = "cpu";
54
-			compatible = "arm,cortex-a53", "arm,armv8";
55
-			reg = <0x0 0x1>;
56
-			enable-method = "psci";
57
-			next-level-cache = <&l2>;
162
+		scpi_sensors: sensors {
163
+			compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
164
+			#thermal-sensor-cells = <1>;
58165 		};
59
-
60
-		cpu2: cpu@2 {
61
-			device_type = "cpu";
62
-			compatible = "arm,cortex-a53", "arm,armv8";
63
-			reg = <0x0 0x2>;
64
-			enable-method = "psci";
65
-			next-level-cache = <&l2>;
66
-		};
67
-
68
-		cpu3: cpu@3 {
69
-			device_type = "cpu";
70
-			compatible = "arm,cortex-a53", "arm,armv8";
71
-			reg = <0x0 0x3>;
72
-			enable-method = "psci";
73
-			next-level-cache = <&l2>;
74
-		};
75
-
76
-		l2: l2-cache0 {
77
-			compatible = "cache";
78
-		};
79
-	};
80
-
81
-	arm-pmu {
82
-		compatible = "arm,cortex-a53-pmu";
83
-		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
84
-			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
85
-			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
86
-			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
87
-		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88
-	};
89
-
90
-	psci {
91
-		compatible = "arm,psci-1.0";
92
-		method = "smc";
93
-	};
94
-
95
-	tdmif_a: audio-controller@0 {
96
-		compatible = "amlogic,axg-tdm-iface";
97
-		#sound-dai-cells = <0>;
98
-		sound-name-prefix = "TDM_A";
99
-		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
100
-			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
101
-			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
102
-		clock-names = "mclk", "sclk", "lrclk";
103
-		status = "disabled";
104
-	};
105
-
106
-	tdmif_b: audio-controller@1 {
107
-		compatible = "amlogic,axg-tdm-iface";
108
-		#sound-dai-cells = <0>;
109
-		sound-name-prefix = "TDM_B";
110
-		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
111
-			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
112
-			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
113
-		clock-names = "mclk", "sclk", "lrclk";
114
-		status = "disabled";
115
-	};
116
-
117
-	tdmif_c: audio-controller@2 {
118
-		compatible = "amlogic,axg-tdm-iface";
119
-		#sound-dai-cells = <0>;
120
-		sound-name-prefix = "TDM_C";
121
-		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
122
-			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
123
-			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
124
-		clock-names = "mclk", "sclk", "lrclk";
125
-		status = "disabled";
126
-	};
127
-
128
-	timer {
129
-		compatible = "arm,armv8-timer";
130
-		interrupts = <GIC_PPI 13
131
-			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
132
-			     <GIC_PPI 14
133
-			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
134
-			     <GIC_PPI 11
135
-			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
136
-			     <GIC_PPI 10
137
-			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
138
-	};
139
-
140
-	xtal: xtal-clk {
141
-		compatible = "fixed-clock";
142
-		clock-frequency = <24000000>;
143
-		clock-output-names = "xtal";
144
-		#clock-cells = <0>;
145
-	};
146
-
147
-	ao_alt_xtal: ao_alt_xtal-clk {
148
-		compatible = "fixed-clock";
149
-		clock-frequency = <32000000>;
150
-		clock-output-names = "ao_alt_xtal";
151
-		#clock-cells = <0>;
152166 	};
153167 
154168 	soc {
....@@ -157,36 +171,1002 @@
157171 		#size-cells = <2>;
158172 		ranges;
159173 
160
-		apb: apb@ffe00000 {
161
-			compatible = "simple-bus";
162
-			reg = <0x0 0xffe00000 0x0 0x200000>;
174
+		usb: usb@ffe09080 {
175
+			compatible = "amlogic,meson-axg-usb-ctrl";
176
+			reg = <0x0 0xffe09080 0x0 0x20>;
177
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
163178 			#address-cells = <2>;
164179 			#size-cells = <2>;
165
-			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
180
+			ranges;
166181 
167
-			sd_emmc_b: sd@5000 {
168
-				compatible = "amlogic,meson-axg-mmc";
169
-				reg = <0x0 0x5000 0x0 0x800>;
170
-				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
171
-				status = "disabled";
172
-				clocks = <&clkc CLKID_SD_EMMC_B>,
173
-					<&clkc CLKID_SD_EMMC_B_CLK0>,
174
-					<&clkc CLKID_FCLK_DIV2>;
175
-				clock-names = "core", "clkin0", "clkin1";
176
-				resets = <&reset RESET_SD_EMMC_B>;
182
+			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
183
+			clock-names = "usb_ctrl", "ddr";
184
+			resets = <&reset RESET_USB_OTG>;
185
+
186
+			dr_mode = "otg";
187
+
188
+			phys = <&usb2_phy1>;
189
+			phy-names = "usb2-phy1";
190
+
191
+			dwc2: usb@ff400000 {
192
+				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
193
+				reg = <0x0 0xff400000 0x0 0x40000>;
194
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
195
+				clocks = <&clkc CLKID_USB1>;
196
+				clock-names = "otg";
197
+				phys = <&usb2_phy1>;
198
+				dr_mode = "peripheral";
199
+				g-rx-fifo-size = <192>;
200
+				g-np-tx-fifo-size = <128>;
201
+				g-tx-fifo-size = <128 128 16 16 16>;
177202 			};
178203 
179
-			sd_emmc_c: mmc@7000 {
180
-				compatible = "amlogic,meson-axg-mmc";
181
-				reg = <0x0 0x7000 0x0 0x800>;
182
-				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
183
-				status = "disabled";
184
-				clocks = <&clkc CLKID_SD_EMMC_C>,
185
-					<&clkc CLKID_SD_EMMC_C_CLK0>,
186
-					<&clkc CLKID_FCLK_DIV2>;
187
-				clock-names = "core", "clkin0", "clkin1";
188
-				resets = <&reset RESET_SD_EMMC_C>;
204
+			dwc3: usb@ff500000 {
205
+				compatible = "snps,dwc3";
206
+				reg = <0x0 0xff500000 0x0 0x100000>;
207
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
208
+				dr_mode = "host";
209
+				maximum-speed = "high-speed";
210
+				snps,dis_u2_susphy_quirk;
189211 			};
212
+		};
213
+
214
+		ethmac: ethernet@ff3f0000 {
215
+			compatible = "amlogic,meson-axg-dwmac",
216
+				     "snps,dwmac-3.70a",
217
+				     "snps,dwmac";
218
+			reg = <0x0 0xff3f0000 0x0 0x10000>,
219
+			      <0x0 0xff634540 0x0 0x8>;
220
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
221
+			interrupt-names = "macirq";
222
+			clocks = <&clkc CLKID_ETH>,
223
+				 <&clkc CLKID_FCLK_DIV2>,
224
+				 <&clkc CLKID_MPLL2>,
225
+				 <&clkc CLKID_FCLK_DIV2>;
226
+			clock-names = "stmmaceth", "clkin0", "clkin1",
227
+				      "timing-adjustment";
228
+			rx-fifo-depth = <4096>;
229
+			tx-fifo-depth = <2048>;
230
+			status = "disabled";
231
+		};
232
+
233
+		pdm: audio-controller@ff632000 {
234
+			compatible = "amlogic,axg-pdm";
235
+			reg = <0x0 0xff632000 0x0 0x34>;
236
+			#sound-dai-cells = <0>;
237
+			sound-name-prefix = "PDM";
238
+			clocks = <&clkc_audio AUD_CLKID_PDM>,
239
+				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
240
+				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
241
+			clock-names = "pclk", "dclk", "sysclk";
242
+			status = "disabled";
243
+		};
244
+
245
+		periphs: bus@ff634000 {
246
+			compatible = "simple-bus";
247
+			reg = <0x0 0xff634000 0x0 0x2000>;
248
+			#address-cells = <2>;
249
+			#size-cells = <2>;
250
+			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
251
+
252
+			hwrng: rng@18 {
253
+				compatible = "amlogic,meson-rng";
254
+				reg = <0x0 0x18 0x0 0x4>;
255
+				clocks = <&clkc CLKID_RNG0>;
256
+				clock-names = "core";
257
+			};
258
+
259
+			pinctrl_periphs: pinctrl@480 {
260
+				compatible = "amlogic,meson-axg-periphs-pinctrl";
261
+				#address-cells = <2>;
262
+				#size-cells = <2>;
263
+				ranges;
264
+
265
+				gpio: bank@480 {
266
+					reg = <0x0 0x00480 0x0 0x40>,
267
+					      <0x0 0x004e8 0x0 0x14>,
268
+					      <0x0 0x00520 0x0 0x14>,
269
+					      <0x0 0x00430 0x0 0x3c>;
270
+					reg-names = "mux", "pull", "pull-enable", "gpio";
271
+					gpio-controller;
272
+					#gpio-cells = <2>;
273
+					gpio-ranges = <&pinctrl_periphs 0 0 86>;
274
+				};
275
+
276
+				i2c0_pins: i2c0 {
277
+					mux {
278
+						groups = "i2c0_sck",
279
+							 "i2c0_sda";
280
+						function = "i2c0";
281
+						bias-disable;
282
+					};
283
+				};
284
+
285
+				i2c1_x_pins: i2c1_x {
286
+					mux {
287
+						groups = "i2c1_sck_x",
288
+							 "i2c1_sda_x";
289
+						function = "i2c1";
290
+						bias-disable;
291
+					};
292
+				};
293
+
294
+				i2c1_z_pins: i2c1_z {
295
+					mux {
296
+						groups = "i2c1_sck_z",
297
+							 "i2c1_sda_z";
298
+						function = "i2c1";
299
+						bias-disable;
300
+					};
301
+				};
302
+
303
+				i2c2_a_pins: i2c2_a {
304
+					mux {
305
+						groups = "i2c2_sck_a",
306
+							 "i2c2_sda_a";
307
+						function = "i2c2";
308
+						bias-disable;
309
+					};
310
+				};
311
+
312
+				i2c2_x_pins: i2c2_x {
313
+					mux {
314
+						groups = "i2c2_sck_x",
315
+							 "i2c2_sda_x";
316
+						function = "i2c2";
317
+						bias-disable;
318
+					};
319
+				};
320
+
321
+				i2c3_a6_pins: i2c3_a6 {
322
+					mux {
323
+						groups = "i2c3_sda_a6",
324
+							 "i2c3_sck_a7";
325
+						function = "i2c3";
326
+						bias-disable;
327
+					};
328
+				};
329
+
330
+				i2c3_a12_pins: i2c3_a12 {
331
+					mux {
332
+						groups = "i2c3_sda_a12",
333
+							 "i2c3_sck_a13";
334
+						function = "i2c3";
335
+						bias-disable;
336
+					};
337
+				};
338
+
339
+				i2c3_a19_pins: i2c3_a19 {
340
+					mux {
341
+						groups = "i2c3_sda_a19",
342
+							 "i2c3_sck_a20";
343
+						function = "i2c3";
344
+						bias-disable;
345
+					};
346
+				};
347
+
348
+				emmc_pins: emmc {
349
+					mux-0 {
350
+						groups = "emmc_nand_d0",
351
+							 "emmc_nand_d1",
352
+							 "emmc_nand_d2",
353
+							 "emmc_nand_d3",
354
+							 "emmc_nand_d4",
355
+							 "emmc_nand_d5",
356
+							 "emmc_nand_d6",
357
+							 "emmc_nand_d7",
358
+							 "emmc_cmd";
359
+						function = "emmc";
360
+						bias-pull-up;
361
+					};
362
+
363
+					mux-1 {
364
+						groups = "emmc_clk";
365
+						function = "emmc";
366
+						bias-disable;
367
+					};
368
+				};
369
+
370
+				emmc_ds_pins: emmc_ds {
371
+					mux {
372
+						groups = "emmc_ds";
373
+						function = "emmc";
374
+						bias-pull-down;
375
+					};
376
+				};
377
+
378
+				emmc_clk_gate_pins: emmc_clk_gate {
379
+					mux {
380
+						groups = "BOOT_8";
381
+						function = "gpio_periphs";
382
+						bias-pull-down;
383
+					};
384
+				};
385
+
386
+				eth_rgmii_x_pins: eth-x-rgmii {
387
+					mux {
388
+						groups = "eth_mdio_x",
389
+							 "eth_mdc_x",
390
+							 "eth_rgmii_rx_clk_x",
391
+							 "eth_rx_dv_x",
392
+							 "eth_rxd0_x",
393
+							 "eth_rxd1_x",
394
+							 "eth_rxd2_rgmii",
395
+							 "eth_rxd3_rgmii",
396
+							 "eth_rgmii_tx_clk",
397
+							 "eth_txen_x",
398
+							 "eth_txd0_x",
399
+							 "eth_txd1_x",
400
+							 "eth_txd2_rgmii",
401
+							 "eth_txd3_rgmii";
402
+						function = "eth";
403
+						bias-disable;
404
+					};
405
+				};
406
+
407
+				eth_rgmii_y_pins: eth-y-rgmii {
408
+					mux {
409
+						groups = "eth_mdio_y",
410
+							 "eth_mdc_y",
411
+							 "eth_rgmii_rx_clk_y",
412
+							 "eth_rx_dv_y",
413
+							 "eth_rxd0_y",
414
+							 "eth_rxd1_y",
415
+							 "eth_rxd2_rgmii",
416
+							 "eth_rxd3_rgmii",
417
+							 "eth_rgmii_tx_clk",
418
+							 "eth_txen_y",
419
+							 "eth_txd0_y",
420
+							 "eth_txd1_y",
421
+							 "eth_txd2_rgmii",
422
+							 "eth_txd3_rgmii";
423
+						function = "eth";
424
+						bias-disable;
425
+					};
426
+				};
427
+
428
+				eth_rmii_x_pins: eth-x-rmii {
429
+					mux {
430
+						groups = "eth_mdio_x",
431
+							 "eth_mdc_x",
432
+							 "eth_rgmii_rx_clk_x",
433
+							 "eth_rx_dv_x",
434
+							 "eth_rxd0_x",
435
+							 "eth_rxd1_x",
436
+							 "eth_txen_x",
437
+							 "eth_txd0_x",
438
+							 "eth_txd1_x";
439
+						function = "eth";
440
+						bias-disable;
441
+					};
442
+				};
443
+
444
+				eth_rmii_y_pins: eth-y-rmii {
445
+					mux {
446
+						groups = "eth_mdio_y",
447
+							 "eth_mdc_y",
448
+							 "eth_rgmii_rx_clk_y",
449
+							 "eth_rx_dv_y",
450
+							 "eth_rxd0_y",
451
+							 "eth_rxd1_y",
452
+							 "eth_txen_y",
453
+							 "eth_txd0_y",
454
+							 "eth_txd1_y";
455
+						function = "eth";
456
+						bias-disable;
457
+					};
458
+				};
459
+
460
+				mclk_b_pins: mclk_b {
461
+					mux {
462
+						groups = "mclk_b";
463
+						function = "mclk_b";
464
+						bias-disable;
465
+					};
466
+				};
467
+
468
+				mclk_c_pins: mclk_c {
469
+					mux {
470
+						groups = "mclk_c";
471
+						function = "mclk_c";
472
+						bias-disable;
473
+					};
474
+				};
475
+
476
+				pdm_dclk_a14_pins: pdm_dclk_a14 {
477
+					mux {
478
+						groups = "pdm_dclk_a14";
479
+						function = "pdm";
480
+						bias-disable;
481
+					};
482
+				};
483
+
484
+				pdm_dclk_a19_pins: pdm_dclk_a19 {
485
+					mux {
486
+						groups = "pdm_dclk_a19";
487
+						function = "pdm";
488
+						bias-disable;
489
+					};
490
+				};
491
+
492
+				pdm_din0_pins: pdm_din0 {
493
+					mux {
494
+						groups = "pdm_din0";
495
+						function = "pdm";
496
+						bias-disable;
497
+					};
498
+				};
499
+
500
+				pdm_din1_pins: pdm_din1 {
501
+					mux {
502
+						groups = "pdm_din1";
503
+						function = "pdm";
504
+						bias-disable;
505
+					};
506
+				};
507
+
508
+				pdm_din2_pins: pdm_din2 {
509
+					mux {
510
+						groups = "pdm_din2";
511
+						function = "pdm";
512
+						bias-disable;
513
+					};
514
+				};
515
+
516
+				pdm_din3_pins: pdm_din3 {
517
+					mux {
518
+						groups = "pdm_din3";
519
+						function = "pdm";
520
+						bias-disable;
521
+					};
522
+				};
523
+
524
+				pwm_a_a_pins: pwm_a_a {
525
+					mux {
526
+						groups = "pwm_a_a";
527
+						function = "pwm_a";
528
+						bias-disable;
529
+					};
530
+				};
531
+
532
+				pwm_a_x18_pins: pwm_a_x18 {
533
+					mux {
534
+						groups = "pwm_a_x18";
535
+						function = "pwm_a";
536
+						bias-disable;
537
+					};
538
+				};
539
+
540
+				pwm_a_x20_pins: pwm_a_x20 {
541
+					mux {
542
+						groups = "pwm_a_x20";
543
+						function = "pwm_a";
544
+						bias-disable;
545
+					};
546
+				};
547
+
548
+				pwm_a_z_pins: pwm_a_z {
549
+					mux {
550
+						groups = "pwm_a_z";
551
+						function = "pwm_a";
552
+						bias-disable;
553
+					};
554
+				};
555
+
556
+				pwm_b_a_pins: pwm_b_a {
557
+					mux {
558
+						groups = "pwm_b_a";
559
+						function = "pwm_b";
560
+						bias-disable;
561
+					};
562
+				};
563
+
564
+				pwm_b_x_pins: pwm_b_x {
565
+					mux {
566
+						groups = "pwm_b_x";
567
+						function = "pwm_b";
568
+						bias-disable;
569
+					};
570
+				};
571
+
572
+				pwm_b_z_pins: pwm_b_z {
573
+					mux {
574
+						groups = "pwm_b_z";
575
+						function = "pwm_b";
576
+						bias-disable;
577
+					};
578
+				};
579
+
580
+				pwm_c_a_pins: pwm_c_a {
581
+					mux {
582
+						groups = "pwm_c_a";
583
+						function = "pwm_c";
584
+						bias-disable;
585
+					};
586
+				};
587
+
588
+				pwm_c_x10_pins: pwm_c_x10 {
589
+					mux {
590
+						groups = "pwm_c_x10";
591
+						function = "pwm_c";
592
+						bias-disable;
593
+					};
594
+				};
595
+
596
+				pwm_c_x17_pins: pwm_c_x17 {
597
+					mux {
598
+						groups = "pwm_c_x17";
599
+						function = "pwm_c";
600
+						bias-disable;
601
+					};
602
+				};
603
+
604
+				pwm_d_x11_pins: pwm_d_x11 {
605
+					mux {
606
+						groups = "pwm_d_x11";
607
+						function = "pwm_d";
608
+						bias-disable;
609
+					};
610
+				};
611
+
612
+				pwm_d_x16_pins: pwm_d_x16 {
613
+					mux {
614
+						groups = "pwm_d_x16";
615
+						function = "pwm_d";
616
+						bias-disable;
617
+					};
618
+				};
619
+
620
+				sdio_pins: sdio {
621
+					mux-0 {
622
+						groups = "sdio_d0",
623
+							 "sdio_d1",
624
+							 "sdio_d2",
625
+							 "sdio_d3",
626
+							 "sdio_cmd";
627
+						function = "sdio";
628
+						bias-pull-up;
629
+					};
630
+
631
+					mux-1 {
632
+						groups = "sdio_clk";
633
+						function = "sdio";
634
+						bias-disable;
635
+					};
636
+				};
637
+
638
+				sdio_clk_gate_pins: sdio_clk_gate {
639
+					mux {
640
+						groups = "GPIOX_4";
641
+						function = "gpio_periphs";
642
+						bias-pull-down;
643
+					};
644
+				};
645
+
646
+				spdif_in_z_pins: spdif_in_z {
647
+					mux {
648
+						groups = "spdif_in_z";
649
+						function = "spdif_in";
650
+						bias-disable;
651
+					};
652
+				};
653
+
654
+				spdif_in_a1_pins: spdif_in_a1 {
655
+					mux {
656
+						groups = "spdif_in_a1";
657
+						function = "spdif_in";
658
+						bias-disable;
659
+					};
660
+				};
661
+
662
+				spdif_in_a7_pins: spdif_in_a7 {
663
+					mux {
664
+						groups = "spdif_in_a7";
665
+						function = "spdif_in";
666
+						bias-disable;
667
+					};
668
+				};
669
+
670
+				spdif_in_a19_pins: spdif_in_a19 {
671
+					mux {
672
+						groups = "spdif_in_a19";
673
+						function = "spdif_in";
674
+						bias-disable;
675
+					};
676
+				};
677
+
678
+				spdif_in_a20_pins: spdif_in_a20 {
679
+					mux {
680
+						groups = "spdif_in_a20";
681
+						function = "spdif_in";
682
+						bias-disable;
683
+					};
684
+				};
685
+
686
+				spdif_out_a1_pins: spdif_out_a1 {
687
+					mux {
688
+						groups = "spdif_out_a1";
689
+						function = "spdif_out";
690
+						bias-disable;
691
+					};
692
+				};
693
+
694
+				spdif_out_a11_pins: spdif_out_a11 {
695
+					mux {
696
+						groups = "spdif_out_a11";
697
+						function = "spdif_out";
698
+						bias-disable;
699
+					};
700
+				};
701
+
702
+				spdif_out_a19_pins: spdif_out_a19 {
703
+					mux {
704
+						groups = "spdif_out_a19";
705
+						function = "spdif_out";
706
+						bias-disable;
707
+					};
708
+				};
709
+
710
+				spdif_out_a20_pins: spdif_out_a20 {
711
+					mux {
712
+						groups = "spdif_out_a20";
713
+						function = "spdif_out";
714
+						bias-disable;
715
+					};
716
+				};
717
+
718
+				spdif_out_z_pins: spdif_out_z {
719
+					mux {
720
+						groups = "spdif_out_z";
721
+						function = "spdif_out";
722
+						bias-disable;
723
+					};
724
+				};
725
+
726
+				spi0_pins: spi0 {
727
+					mux {
728
+						groups = "spi0_miso",
729
+							 "spi0_mosi",
730
+							 "spi0_clk";
731
+						function = "spi0";
732
+						bias-disable;
733
+					};
734
+				};
735
+
736
+				spi0_ss0_pins: spi0_ss0 {
737
+					mux {
738
+						groups = "spi0_ss0";
739
+						function = "spi0";
740
+						bias-disable;
741
+					};
742
+				};
743
+
744
+				spi0_ss1_pins: spi0_ss1 {
745
+					mux {
746
+						groups = "spi0_ss1";
747
+						function = "spi0";
748
+						bias-disable;
749
+					};
750
+				};
751
+
752
+				spi0_ss2_pins: spi0_ss2 {
753
+					mux {
754
+						groups = "spi0_ss2";
755
+						function = "spi0";
756
+						bias-disable;
757
+					};
758
+				};
759
+
760
+				spi1_a_pins: spi1_a {
761
+					mux {
762
+						groups = "spi1_miso_a",
763
+							 "spi1_mosi_a",
764
+							 "spi1_clk_a";
765
+						function = "spi1";
766
+						bias-disable;
767
+					};
768
+				};
769
+
770
+				spi1_ss0_a_pins: spi1_ss0_a {
771
+					mux {
772
+						groups = "spi1_ss0_a";
773
+						function = "spi1";
774
+						bias-disable;
775
+					};
776
+				};
777
+
778
+				spi1_ss1_pins: spi1_ss1 {
779
+					mux {
780
+						groups = "spi1_ss1";
781
+						function = "spi1";
782
+						bias-disable;
783
+					};
784
+				};
785
+
786
+				spi1_x_pins: spi1_x {
787
+					mux {
788
+						groups = "spi1_miso_x",
789
+							 "spi1_mosi_x",
790
+							 "spi1_clk_x";
791
+						function = "spi1";
792
+						bias-disable;
793
+					};
794
+				};
795
+
796
+				spi1_ss0_x_pins: spi1_ss0_x {
797
+					mux {
798
+						groups = "spi1_ss0_x";
799
+						function = "spi1";
800
+						bias-disable;
801
+					};
802
+				};
803
+
804
+				tdma_din0_pins: tdma_din0 {
805
+					mux {
806
+						groups = "tdma_din0";
807
+						function = "tdma";
808
+						bias-disable;
809
+					};
810
+				};
811
+
812
+				tdma_dout0_x14_pins: tdma_dout0_x14 {
813
+					mux {
814
+						groups = "tdma_dout0_x14";
815
+						function = "tdma";
816
+						bias-disable;
817
+					};
818
+				};
819
+
820
+				tdma_dout0_x15_pins: tdma_dout0_x15 {
821
+					mux {
822
+						groups = "tdma_dout0_x15";
823
+						function = "tdma";
824
+						bias-disable;
825
+					};
826
+				};
827
+
828
+				tdma_dout1_pins: tdma_dout1 {
829
+					mux {
830
+						groups = "tdma_dout1";
831
+						function = "tdma";
832
+						bias-disable;
833
+					};
834
+				};
835
+
836
+				tdma_din1_pins: tdma_din1 {
837
+					mux {
838
+						groups = "tdma_din1";
839
+						function = "tdma";
840
+						bias-disable;
841
+					};
842
+				};
843
+
844
+				tdma_fs_pins: tdma_fs {
845
+					mux {
846
+						groups = "tdma_fs";
847
+						function = "tdma";
848
+						bias-disable;
849
+					};
850
+				};
851
+
852
+				tdma_fs_slv_pins: tdma_fs_slv {
853
+					mux {
854
+						groups = "tdma_fs_slv";
855
+						function = "tdma";
856
+						bias-disable;
857
+					};
858
+				};
859
+
860
+				tdma_sclk_pins: tdma_sclk {
861
+					mux {
862
+						groups = "tdma_sclk";
863
+						function = "tdma";
864
+						bias-disable;
865
+					};
866
+				};
867
+
868
+				tdma_sclk_slv_pins: tdma_sclk_slv {
869
+					mux {
870
+						groups = "tdma_sclk_slv";
871
+						function = "tdma";
872
+						bias-disable;
873
+					};
874
+				};
875
+
876
+				tdmb_din0_pins: tdmb_din0 {
877
+					mux {
878
+						groups = "tdmb_din0";
879
+						function = "tdmb";
880
+						bias-disable;
881
+					};
882
+				};
883
+
884
+				tdmb_din1_pins: tdmb_din1 {
885
+					mux {
886
+						groups = "tdmb_din1";
887
+						function = "tdmb";
888
+						bias-disable;
889
+					};
890
+				};
891
+
892
+				tdmb_din2_pins: tdmb_din2 {
893
+					mux {
894
+						groups = "tdmb_din2";
895
+						function = "tdmb";
896
+						bias-disable;
897
+					};
898
+				};
899
+
900
+				tdmb_din3_pins: tdmb_din3 {
901
+					mux {
902
+						groups = "tdmb_din3";
903
+						function = "tdmb";
904
+						bias-disable;
905
+					};
906
+				};
907
+
908
+				tdmb_dout0_pins: tdmb_dout0 {
909
+					mux {
910
+						groups = "tdmb_dout0";
911
+						function = "tdmb";
912
+						bias-disable;
913
+					};
914
+				};
915
+
916
+				tdmb_dout1_pins: tdmb_dout1 {
917
+					mux {
918
+						groups = "tdmb_dout1";
919
+						function = "tdmb";
920
+						bias-disable;
921
+					};
922
+				};
923
+
924
+				tdmb_dout2_pins: tdmb_dout2 {
925
+					mux {
926
+						groups = "tdmb_dout2";
927
+						function = "tdmb";
928
+						bias-disable;
929
+					};
930
+				};
931
+
932
+				tdmb_dout3_pins: tdmb_dout3 {
933
+					mux {
934
+						groups = "tdmb_dout3";
935
+						function = "tdmb";
936
+						bias-disable;
937
+					};
938
+				};
939
+
940
+				tdmb_fs_pins: tdmb_fs {
941
+					mux {
942
+						groups = "tdmb_fs";
943
+						function = "tdmb";
944
+						bias-disable;
945
+					};
946
+				};
947
+
948
+				tdmb_fs_slv_pins: tdmb_fs_slv {
949
+					mux {
950
+						groups = "tdmb_fs_slv";
951
+						function = "tdmb";
952
+						bias-disable;
953
+					};
954
+				};
955
+
956
+				tdmb_sclk_pins: tdmb_sclk {
957
+					mux {
958
+						groups = "tdmb_sclk";
959
+						function = "tdmb";
960
+						bias-disable;
961
+					};
962
+				};
963
+
964
+				tdmb_sclk_slv_pins: tdmb_sclk_slv {
965
+					mux {
966
+						groups = "tdmb_sclk_slv";
967
+						function = "tdmb";
968
+						bias-disable;
969
+					};
970
+				};
971
+
972
+				tdmc_fs_pins: tdmc_fs {
973
+					mux {
974
+						groups = "tdmc_fs";
975
+						function = "tdmc";
976
+						bias-disable;
977
+					};
978
+				};
979
+
980
+				tdmc_fs_slv_pins: tdmc_fs_slv {
981
+					mux {
982
+						groups = "tdmc_fs_slv";
983
+						function = "tdmc";
984
+						bias-disable;
985
+					};
986
+				};
987
+
988
+				tdmc_sclk_pins: tdmc_sclk {
989
+					mux {
990
+						groups = "tdmc_sclk";
991
+						function = "tdmc";
992
+						bias-disable;
993
+					};
994
+				};
995
+
996
+				tdmc_sclk_slv_pins: tdmc_sclk_slv {
997
+					mux {
998
+						groups = "tdmc_sclk_slv";
999
+						function = "tdmc";
1000
+						bias-disable;
1001
+					};
1002
+				};
1003
+
1004
+				tdmc_din0_pins: tdmc_din0 {
1005
+					mux {
1006
+						groups = "tdmc_din0";
1007
+						function = "tdmc";
1008
+						bias-disable;
1009
+					};
1010
+				};
1011
+
1012
+				tdmc_din1_pins: tdmc_din1 {
1013
+					mux {
1014
+						groups = "tdmc_din1";
1015
+						function = "tdmc";
1016
+						bias-disable;
1017
+					};
1018
+				};
1019
+
1020
+				tdmc_din2_pins: tdmc_din2 {
1021
+					mux {
1022
+						groups = "tdmc_din2";
1023
+						function = "tdmc";
1024
+						bias-disable;
1025
+					};
1026
+				};
1027
+
1028
+				tdmc_din3_pins: tdmc_din3 {
1029
+					mux {
1030
+						groups = "tdmc_din3";
1031
+						function = "tdmc";
1032
+						bias-disable;
1033
+					};
1034
+				};
1035
+
1036
+				tdmc_dout0_pins: tdmc_dout0 {
1037
+					mux {
1038
+						groups = "tdmc_dout0";
1039
+						function = "tdmc";
1040
+						bias-disable;
1041
+					};
1042
+				};
1043
+
1044
+				tdmc_dout1_pins: tdmc_dout1 {
1045
+					mux {
1046
+						groups = "tdmc_dout1";
1047
+						function = "tdmc";
1048
+						bias-disable;
1049
+					};
1050
+				};
1051
+
1052
+				tdmc_dout2_pins: tdmc_dout2 {
1053
+					mux {
1054
+						groups = "tdmc_dout2";
1055
+						function = "tdmc";
1056
+						bias-disable;
1057
+					};
1058
+				};
1059
+
1060
+				tdmc_dout3_pins: tdmc_dout3 {
1061
+					mux {
1062
+						groups = "tdmc_dout3";
1063
+						function = "tdmc";
1064
+						bias-disable;
1065
+					};
1066
+				};
1067
+
1068
+				uart_a_pins: uart_a {
1069
+					mux {
1070
+						groups = "uart_tx_a",
1071
+							 "uart_rx_a";
1072
+						function = "uart_a";
1073
+						bias-disable;
1074
+					};
1075
+				};
1076
+
1077
+				uart_a_cts_rts_pins: uart_a_cts_rts {
1078
+					mux {
1079
+						groups = "uart_cts_a",
1080
+							 "uart_rts_a";
1081
+						function = "uart_a";
1082
+						bias-disable;
1083
+					};
1084
+				};
1085
+
1086
+				uart_b_x_pins: uart_b_x {
1087
+					mux {
1088
+						groups = "uart_tx_b_x",
1089
+							 "uart_rx_b_x";
1090
+						function = "uart_b";
1091
+						bias-disable;
1092
+					};
1093
+				};
1094
+
1095
+				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1096
+					mux {
1097
+						groups = "uart_cts_b_x",
1098
+							 "uart_rts_b_x";
1099
+						function = "uart_b";
1100
+						bias-disable;
1101
+					};
1102
+				};
1103
+
1104
+				uart_b_z_pins: uart_b_z {
1105
+					mux {
1106
+						groups = "uart_tx_b_z",
1107
+							 "uart_rx_b_z";
1108
+						function = "uart_b";
1109
+						bias-disable;
1110
+					};
1111
+				};
1112
+
1113
+				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1114
+					mux {
1115
+						groups = "uart_cts_b_z",
1116
+							 "uart_rts_b_z";
1117
+						function = "uart_b";
1118
+						bias-disable;
1119
+					};
1120
+				};
1121
+
1122
+				uart_ao_b_z_pins: uart_ao_b_z {
1123
+					mux {
1124
+						groups = "uart_ao_tx_b_z",
1125
+							 "uart_ao_rx_b_z";
1126
+						function = "uart_ao_b_z";
1127
+						bias-disable;
1128
+					};
1129
+				};
1130
+
1131
+				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1132
+					mux {
1133
+						groups = "uart_ao_cts_b_z",
1134
+							 "uart_ao_rts_b_z";
1135
+						function = "uart_ao_b_z";
1136
+						bias-disable;
1137
+					};
1138
+				};
1139
+			};
1140
+		};
1141
+
1142
+		hiubus: bus@ff63c000 {
1143
+			compatible = "simple-bus";
1144
+			reg = <0x0 0xff63c000 0x0 0x1c00>;
1145
+			#address-cells = <2>;
1146
+			#size-cells = <2>;
1147
+			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1148
+
1149
+			sysctrl: system-controller@0 {
1150
+				compatible = "amlogic,meson-axg-hhi-sysctrl",
1151
+					     "simple-mfd", "syscon";
1152
+				reg = <0 0 0 0x400>;
1153
+
1154
+				clkc: clock-controller {
1155
+					compatible = "amlogic,axg-clkc";
1156
+					#clock-cells = <1>;
1157
+					clocks = <&xtal>;
1158
+					clock-names = "xtal";
1159
+				};
1160
+			};
1161
+		};
1162
+
1163
+		mailbox: mailbox@ff63c404 {
1164
+			compatible = "amlogic,meson-gxbb-mhu";
1165
+			reg = <0 0xff63c404 0 0x4c>;
1166
+			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1167
+				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1168
+				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1169
+			#mbox-cells = <1>;
1901170 		};
1911171 
1921172 		audio: bus@ff642000 {
....@@ -221,6 +1201,78 @@
2211201 					      "mst_in7";
2221202 
2231203 				resets = <&reset RESET_AUDIO>;
1204
+			};
1205
+
1206
+			toddr_a: audio-controller@100 {
1207
+				compatible = "amlogic,axg-toddr";
1208
+				reg = <0x0 0x100 0x0 0x2c>;
1209
+				#sound-dai-cells = <0>;
1210
+				sound-name-prefix = "TODDR_A";
1211
+				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1212
+				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1213
+				resets = <&arb AXG_ARB_TODDR_A>;
1214
+				amlogic,fifo-depth = <512>;
1215
+				status = "disabled";
1216
+			};
1217
+
1218
+			toddr_b: audio-controller@140 {
1219
+				compatible = "amlogic,axg-toddr";
1220
+				reg = <0x0 0x140 0x0 0x2c>;
1221
+				#sound-dai-cells = <0>;
1222
+				sound-name-prefix = "TODDR_B";
1223
+				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1224
+				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1225
+				resets = <&arb AXG_ARB_TODDR_B>;
1226
+				amlogic,fifo-depth = <256>;
1227
+				status = "disabled";
1228
+			};
1229
+
1230
+			toddr_c: audio-controller@180 {
1231
+				compatible = "amlogic,axg-toddr";
1232
+				reg = <0x0 0x180 0x0 0x2c>;
1233
+				#sound-dai-cells = <0>;
1234
+				sound-name-prefix = "TODDR_C";
1235
+				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1236
+				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1237
+				resets = <&arb AXG_ARB_TODDR_C>;
1238
+				amlogic,fifo-depth = <256>;
1239
+				status = "disabled";
1240
+			};
1241
+
1242
+			frddr_a: audio-controller@1c0 {
1243
+				compatible = "amlogic,axg-frddr";
1244
+				reg = <0x0 0x1c0 0x0 0x2c>;
1245
+				#sound-dai-cells = <0>;
1246
+				sound-name-prefix = "FRDDR_A";
1247
+				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1248
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1249
+				resets = <&arb AXG_ARB_FRDDR_A>;
1250
+				amlogic,fifo-depth = <512>;
1251
+				status = "disabled";
1252
+			};
1253
+
1254
+			frddr_b: audio-controller@200 {
1255
+				compatible = "amlogic,axg-frddr";
1256
+				reg = <0x0 0x200 0x0 0x2c>;
1257
+				#sound-dai-cells = <0>;
1258
+				sound-name-prefix = "FRDDR_B";
1259
+				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1260
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1261
+				resets = <&arb AXG_ARB_FRDDR_B>;
1262
+				amlogic,fifo-depth = <256>;
1263
+				status = "disabled";
1264
+			};
1265
+
1266
+			frddr_c: audio-controller@240 {
1267
+				compatible = "amlogic,axg-frddr";
1268
+				reg = <0x0 0x240 0x0 0x2c>;
1269
+				#sound-dai-cells = <0>;
1270
+				sound-name-prefix = "FRDDR_C";
1271
+				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1272
+				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1273
+				resets = <&arb AXG_ARB_FRDDR_C>;
1274
+				amlogic,fifo-depth = <256>;
1275
+				status = "disabled";
2241276 			};
2251277 
2261278 			arb: reset-controller@280 {
....@@ -286,6 +1338,18 @@
2861338 				status = "disabled";
2871339 			};
2881340 
1341
+			spdifin: audio-controller@400 {
1342
+				compatible = "amlogic,axg-spdifin";
1343
+				reg = <0x0 0x400 0x0 0x30>;
1344
+				#sound-dai-cells = <0>;
1345
+				sound-name-prefix = "SPDIFIN";
1346
+				interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1347
+				clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1348
+					 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1349
+				clock-names = "pclk", "refclk";
1350
+				status = "disabled";
1351
+			};
1352
+
2891353 			spdifout: audio-controller@480 {
2901354 				compatible = "amlogic,axg-spdifout";
2911355 				reg = <0x0 0x480 0x0 0x50>;
....@@ -340,6 +1404,218 @@
3401404 			};
3411405 		};
3421406 
1407
+		aobus: bus@ff800000 {
1408
+			compatible = "simple-bus";
1409
+			reg = <0x0 0xff800000 0x0 0x100000>;
1410
+			#address-cells = <2>;
1411
+			#size-cells = <2>;
1412
+			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1413
+
1414
+			sysctrl_AO: sys-ctrl@0 {
1415
+				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1416
+				reg =  <0x0 0x0 0x0 0x100>;
1417
+
1418
+				clkc_AO: clock-controller {
1419
+					compatible = "amlogic,meson-axg-aoclkc";
1420
+					#clock-cells = <1>;
1421
+					#reset-cells = <1>;
1422
+					clocks = <&xtal>, <&clkc CLKID_CLK81>;
1423
+					clock-names = "xtal", "mpeg-clk";
1424
+				};
1425
+			};
1426
+
1427
+			pinctrl_aobus: pinctrl@14 {
1428
+				compatible = "amlogic,meson-axg-aobus-pinctrl";
1429
+				#address-cells = <2>;
1430
+				#size-cells = <2>;
1431
+				ranges;
1432
+
1433
+				gpio_ao: bank@14 {
1434
+					reg = <0x0 0x00014 0x0 0x8>,
1435
+					      <0x0 0x0002c 0x0 0x4>,
1436
+					      <0x0 0x00024 0x0 0x8>;
1437
+					reg-names = "mux", "pull", "gpio";
1438
+					gpio-controller;
1439
+					#gpio-cells = <2>;
1440
+					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1441
+				};
1442
+
1443
+				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1444
+					mux {
1445
+						groups = "i2c_ao_sck_4";
1446
+						function = "i2c_ao";
1447
+						bias-disable;
1448
+					};
1449
+				};
1450
+
1451
+				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1452
+					mux {
1453
+						groups = "i2c_ao_sck_8";
1454
+						function = "i2c_ao";
1455
+						bias-disable;
1456
+					};
1457
+				};
1458
+
1459
+				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1460
+					mux {
1461
+						groups = "i2c_ao_sck_10";
1462
+						function = "i2c_ao";
1463
+						bias-disable;
1464
+					};
1465
+				};
1466
+
1467
+				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1468
+					mux {
1469
+						groups = "i2c_ao_sda_5";
1470
+						function = "i2c_ao";
1471
+						bias-disable;
1472
+					};
1473
+				};
1474
+
1475
+				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1476
+					mux {
1477
+						groups = "i2c_ao_sda_9";
1478
+						function = "i2c_ao";
1479
+						bias-disable;
1480
+					};
1481
+				};
1482
+
1483
+				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1484
+					mux {
1485
+						groups = "i2c_ao_sda_11";
1486
+						function = "i2c_ao";
1487
+						bias-disable;
1488
+					};
1489
+				};
1490
+
1491
+				remote_input_ao_pins: remote_input_ao {
1492
+					mux {
1493
+						groups = "remote_input_ao";
1494
+						function = "remote_input_ao";
1495
+						bias-disable;
1496
+					};
1497
+				};
1498
+
1499
+				uart_ao_a_pins: uart_ao_a {
1500
+					mux {
1501
+						groups = "uart_ao_tx_a",
1502
+							 "uart_ao_rx_a";
1503
+						function = "uart_ao_a";
1504
+						bias-disable;
1505
+					};
1506
+				};
1507
+
1508
+				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1509
+					mux {
1510
+						groups = "uart_ao_cts_a",
1511
+							 "uart_ao_rts_a";
1512
+						function = "uart_ao_a";
1513
+						bias-disable;
1514
+					};
1515
+				};
1516
+
1517
+				uart_ao_b_pins: uart_ao_b {
1518
+					mux {
1519
+						groups = "uart_ao_tx_b",
1520
+							 "uart_ao_rx_b";
1521
+						function = "uart_ao_b";
1522
+						bias-disable;
1523
+					};
1524
+				};
1525
+
1526
+				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1527
+					mux {
1528
+						groups = "uart_ao_cts_b",
1529
+							 "uart_ao_rts_b";
1530
+						function = "uart_ao_b";
1531
+						bias-disable;
1532
+					};
1533
+				};
1534
+			};
1535
+
1536
+			sec_AO: ao-secure@140 {
1537
+				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1538
+				reg = <0x0 0x140 0x0 0x140>;
1539
+				amlogic,has-chip-id;
1540
+			};
1541
+
1542
+			pwm_AO_cd: pwm@2000 {
1543
+				compatible = "amlogic,meson-axg-ao-pwm";
1544
+				reg = <0x0 0x02000  0x0 0x20>;
1545
+				#pwm-cells = <3>;
1546
+				status = "disabled";
1547
+			};
1548
+
1549
+			uart_AO: serial@3000 {
1550
+				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1551
+				reg = <0x0 0x3000 0x0 0x18>;
1552
+				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1553
+				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1554
+				clock-names = "xtal", "pclk", "baud";
1555
+				status = "disabled";
1556
+			};
1557
+
1558
+			uart_AO_B: serial@4000 {
1559
+				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1560
+				reg = <0x0 0x4000 0x0 0x18>;
1561
+				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1562
+				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1563
+				clock-names = "xtal", "pclk", "baud";
1564
+				status = "disabled";
1565
+			};
1566
+
1567
+			i2c_AO: i2c@5000 {
1568
+				compatible = "amlogic,meson-axg-i2c";
1569
+				reg = <0x0 0x05000 0x0 0x20>;
1570
+				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1571
+				clocks = <&clkc CLKID_AO_I2C>;
1572
+				#address-cells = <1>;
1573
+				#size-cells = <0>;
1574
+				status = "disabled";
1575
+			};
1576
+
1577
+			pwm_AO_ab: pwm@7000 {
1578
+				compatible = "amlogic,meson-axg-ao-pwm";
1579
+				reg = <0x0 0x07000 0x0 0x20>;
1580
+				#pwm-cells = <3>;
1581
+				status = "disabled";
1582
+			};
1583
+
1584
+			ir: ir@8000 {
1585
+				compatible = "amlogic,meson-gxbb-ir";
1586
+				reg = <0x0 0x8000 0x0 0x20>;
1587
+				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1588
+				status = "disabled";
1589
+			};
1590
+
1591
+			saradc: adc@9000 {
1592
+				compatible = "amlogic,meson-axg-saradc",
1593
+					"amlogic,meson-saradc";
1594
+				reg = <0x0 0x9000 0x0 0x38>;
1595
+				#io-channel-cells = <1>;
1596
+				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1597
+				clocks = <&xtal>,
1598
+					 <&clkc_AO CLKID_AO_SAR_ADC>,
1599
+					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1600
+					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1601
+				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1602
+				status = "disabled";
1603
+			};
1604
+		};
1605
+
1606
+		gic: interrupt-controller@ffc01000 {
1607
+			compatible = "arm,gic-400";
1608
+			reg = <0x0 0xffc01000 0 0x1000>,
1609
+			      <0x0 0xffc02000 0 0x2000>,
1610
+			      <0x0 0xffc04000 0 0x2000>,
1611
+			      <0x0 0xffc06000 0 0x2000>;
1612
+			interrupt-controller;
1613
+			interrupts = <GIC_PPI 9
1614
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1615
+			#interrupt-cells = <3>;
1616
+			#address-cells = <0>;
1617
+		};
1618
+
3431619 		cbus: bus@ffd00000 {
3441620 			compatible = "simple-bus";
3451621 			reg = <0x0 0xffd00000 0x0 0x25000>;
....@@ -347,13 +1623,25 @@
3471623 			#size-cells = <2>;
3481624 			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
3491625 
1626
+			reset: reset-controller@1004 {
1627
+				compatible = "amlogic,meson-axg-reset";
1628
+				reg = <0x0 0x01004 0x0 0x9c>;
1629
+				#reset-cells = <1>;
1630
+			};
1631
+
3501632 			gpio_intc: interrupt-controller@f080 {
351
-				compatible = "amlogic,meson-gpio-intc";
1633
+				compatible = "amlogic,meson-axg-gpio-intc",
1634
+					     "amlogic,meson-gpio-intc";
3521635 				reg = <0x0 0xf080 0x0 0x10>;
3531636 				interrupt-controller;
3541637 				#interrupt-cells = <2>;
3551638 				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
356
-				status = "disabled";
1639
+			};
1640
+
1641
+			watchdog@f0d0 {
1642
+				compatible = "amlogic,meson-gxbb-wdt";
1643
+				reg = <0x0 0xf0d0 0x0 0x10>;
1644
+				clocks = <&xtal>;
3571645 			};
3581646 
3591647 			pwm_ab: pwm@1b000 {
....@@ -368,12 +1656,6 @@
3681656 				reg = <0x0 0x1a000 0x0 0x20>;
3691657 				#pwm-cells = <3>;
3701658 				status = "disabled";
371
-			};
372
-
373
-			reset: reset-controller@1004 {
374
-				compatible = "amlogic,meson-axg-reset";
375
-				reg = <0x0 0x01004 0x0 0x9c>;
376
-				#reset-cells = <1>;
3771659 			};
3781660 
3791661 			spicc0: spi@13000 {
....@@ -398,20 +1680,15 @@
3981680 				status = "disabled";
3991681 			};
4001682 
401
-			i2c0: i2c@1f000 {
402
-				compatible = "amlogic,meson-axg-i2c";
403
-				reg = <0x0 0x1f000 0x0 0x20>;
404
-				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
405
-				clocks = <&clkc CLKID_I2C>;
406
-				#address-cells = <1>;
407
-				#size-cells = <0>;
408
-				status = "disabled";
1683
+			clk_msr: clock-measure@18000 {
1684
+				compatible = "amlogic,meson-axg-clk-measure";
1685
+				reg = <0x0 0x18000 0x0 0x10>;
4091686 			};
4101687 
411
-			i2c1: i2c@1e000 {
1688
+			i2c3: i2c@1c000 {
4121689 				compatible = "amlogic,meson-axg-i2c";
413
-				reg = <0x0 0x1e000 0x0 0x20>;
414
-				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1690
+				reg = <0x0 0x1c000 0x0 0x20>;
1691
+				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
4151692 				clocks = <&clkc CLKID_I2C>;
4161693 				#address-cells = <1>;
4171694 				#size-cells = <0>;
....@@ -428,23 +1705,24 @@
4281705 				status = "disabled";
4291706 			};
4301707 
431
-			i2c3: i2c@1c000 {
1708
+			i2c1: i2c@1e000 {
4321709 				compatible = "amlogic,meson-axg-i2c";
433
-				reg = <0x0 0x1c000 0x0 0x20>;
434
-				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1710
+				reg = <0x0 0x1e000 0x0 0x20>;
1711
+				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
4351712 				clocks = <&clkc CLKID_I2C>;
4361713 				#address-cells = <1>;
4371714 				#size-cells = <0>;
4381715 				status = "disabled";
4391716 			};
4401717 
441
-			uart_A: serial@24000 {
442
-				compatible = "amlogic,meson-gx-uart";
443
-				reg = <0x0 0x24000 0x0 0x18>;
444
-				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1718
+			i2c0: i2c@1f000 {
1719
+				compatible = "amlogic,meson-axg-i2c";
1720
+				reg = <0x0 0x1f000 0x0 0x20>;
1721
+				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1722
+				clocks = <&clkc CLKID_I2C>;
1723
+				#address-cells = <1>;
1724
+				#size-cells = <0>;
4451725 				status = "disabled";
446
-				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
447
-				clock-names = "xtal", "pclk", "baud";
4481726 			};
4491727 
4501728 			uart_B: serial@23000 {
....@@ -455,1056 +1733,94 @@
4551733 				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
4561734 				clock-names = "xtal", "pclk", "baud";
4571735 			};
458
-		};
4591736 
460
-		ethmac: ethernet@ff3f0000 {
461
-			compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
462
-			reg = <0x0 0xff3f0000 0x0 0x10000
463
-				0x0 0xff634540 0x0 0x8>;
464
-			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
465
-			interrupt-names = "macirq";
466
-			clocks = <&clkc CLKID_ETH>,
467
-				 <&clkc CLKID_FCLK_DIV2>,
468
-				 <&clkc CLKID_MPLL2>;
469
-			clock-names = "stmmaceth", "clkin0", "clkin1";
470
-			status = "disabled";
471
-		};
472
-
473
-		gic: interrupt-controller@ffc01000 {
474
-			compatible = "arm,gic-400";
475
-			reg = <0x0 0xffc01000 0 0x1000>,
476
-			      <0x0 0xffc02000 0 0x2000>,
477
-			      <0x0 0xffc04000 0 0x2000>,
478
-			      <0x0 0xffc06000 0 0x2000>;
479
-			interrupt-controller;
480
-			interrupts = <GIC_PPI 9
481
-				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
482
-			#interrupt-cells = <3>;
483
-			#address-cells = <0>;
484
-		};
485
-
486
-		hiubus: bus@ff63c000 {
487
-			compatible = "simple-bus";
488
-			reg = <0x0 0xff63c000 0x0 0x1c00>;
489
-			#address-cells = <2>;
490
-			#size-cells = <2>;
491
-			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
492
-
493
-			sysctrl: system-controller@0 {
494
-				compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
495
-				reg = <0 0 0 0x400>;
496
-
497
-				clkc: clock-controller {
498
-					compatible = "amlogic,axg-clkc";
499
-					#clock-cells = <1>;
500
-				};
1737
+			uart_A: serial@24000 {
1738
+				compatible = "amlogic,meson-gx-uart";
1739
+				reg = <0x0 0x24000 0x0 0x18>;
1740
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1741
+				status = "disabled";
1742
+				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1743
+				clock-names = "xtal", "pclk", "baud";
5011744 			};
5021745 		};
5031746 
504
-		mailbox: mailbox@ff63dc00 {
505
-			compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
506
-			reg = <0 0xff63dc00 0 0x400>;
507
-			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
508
-				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
509
-				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
510
-			#mbox-cells = <1>;
511
-		};
512
-
513
-		periphs: periphs@ff634000 {
1747
+		apb: bus@ffe00000 {
5141748 			compatible = "simple-bus";
515
-			reg = <0x0 0xff634000 0x0 0x2000>;
1749
+			reg = <0x0 0xffe00000 0x0 0x200000>;
5161750 			#address-cells = <2>;
5171751 			#size-cells = <2>;
518
-			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
1752
+			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
5191753 
520
-			hwrng: rng {
521
-				compatible = "amlogic,meson-rng";
522
-				reg = <0x0 0x18 0x0 0x4>;
523
-				clocks = <&clkc CLKID_RNG0>;
524
-				clock-names = "core";
1754
+			sd_emmc_b: sd@5000 {
1755
+				compatible = "amlogic,meson-axg-mmc";
1756
+				reg = <0x0 0x5000 0x0 0x800>;
1757
+				interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1758
+				status = "disabled";
1759
+				clocks = <&clkc CLKID_SD_EMMC_B>,
1760
+					<&clkc CLKID_SD_EMMC_B_CLK0>,
1761
+					<&clkc CLKID_FCLK_DIV2>;
1762
+				clock-names = "core", "clkin0", "clkin1";
1763
+				resets = <&reset RESET_SD_EMMC_B>;
5251764 			};
5261765 
527
-			pinctrl_periphs: pinctrl@480 {
528
-				compatible = "amlogic,meson-axg-periphs-pinctrl";
529
-				#address-cells = <2>;
530
-				#size-cells = <2>;
531
-				ranges;
1766
+			sd_emmc_c: mmc@7000 {
1767
+				compatible = "amlogic,meson-axg-mmc";
1768
+				reg = <0x0 0x7000 0x0 0x800>;
1769
+				interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
1770
+				status = "disabled";
1771
+				clocks = <&clkc CLKID_SD_EMMC_C>,
1772
+					<&clkc CLKID_SD_EMMC_C_CLK0>,
1773
+					<&clkc CLKID_FCLK_DIV2>;
1774
+				clock-names = "core", "clkin0", "clkin1";
1775
+				resets = <&reset RESET_SD_EMMC_C>;
1776
+			};
5321777 
533
-				gpio: bank@480 {
534
-					reg = <0x0 0x00480 0x0 0x40>,
535
-						<0x0 0x004e8 0x0 0x14>,
536
-						<0x0 0x00520 0x0 0x14>,
537
-						<0x0 0x00430 0x0 0x3c>;
538
-					reg-names = "mux", "pull", "pull-enable", "gpio";
539
-					gpio-controller;
540
-					#gpio-cells = <2>;
541
-					gpio-ranges = <&pinctrl_periphs 0 0 86>;
542
-				};
543
-
544
-				emmc_pins: emmc {
545
-					mux {
546
-						groups = "emmc_nand_d0",
547
-							"emmc_nand_d1",
548
-							"emmc_nand_d2",
549
-							"emmc_nand_d3",
550
-							"emmc_nand_d4",
551
-							"emmc_nand_d5",
552
-							"emmc_nand_d6",
553
-							"emmc_nand_d7",
554
-							"emmc_clk",
555
-							"emmc_cmd",
556
-							"emmc_ds";
557
-						function = "emmc";
558
-					};
559
-				};
560
-
561
-				emmc_clk_gate_pins: emmc_clk_gate {
562
-					mux {
563
-						groups = "BOOT_8";
564
-						function = "gpio_periphs";
565
-					};
566
-					cfg-pull-down {
567
-						pins = "BOOT_8";
568
-						bias-pull-down;
569
-					};
570
-				};
571
-
572
-				sdio_pins: sdio {
573
-					mux {
574
-						groups = "sdio_d0",
575
-							"sdio_d1",
576
-							"sdio_d2",
577
-							"sdio_d3",
578
-							"sdio_cmd",
579
-							"sdio_clk";
580
-						function = "sdio";
581
-					};
582
-				};
583
-
584
-				sdio_clk_gate_pins: sdio_clk_gate {
585
-					mux {
586
-						groups = "GPIOX_4";
587
-						function = "gpio_periphs";
588
-					};
589
-					cfg-pull-down {
590
-						pins = "GPIOX_4";
591
-						bias-pull-down;
592
-					};
593
-				};
594
-
595
-				eth_rmii_x_pins: eth-x-rmii {
596
-					mux {
597
-						groups = "eth_mdio_x",
598
-						       "eth_mdc_x",
599
-						       "eth_rgmii_rx_clk_x",
600
-						       "eth_rx_dv_x",
601
-						       "eth_rxd0_x",
602
-						       "eth_rxd1_x",
603
-						       "eth_txen_x",
604
-						       "eth_txd0_x",
605
-						       "eth_txd1_x";
606
-						function = "eth";
607
-					};
608
-				};
609
-
610
-				eth_rmii_y_pins: eth-y-rmii {
611
-					mux {
612
-						groups = "eth_mdio_y",
613
-						       "eth_mdc_y",
614
-						       "eth_rgmii_rx_clk_y",
615
-						       "eth_rx_dv_y",
616
-						       "eth_rxd0_y",
617
-						       "eth_rxd1_y",
618
-						       "eth_txen_y",
619
-						       "eth_txd0_y",
620
-						       "eth_txd1_y";
621
-						function = "eth";
622
-					};
623
-				};
624
-
625
-				eth_rgmii_x_pins: eth-x-rgmii {
626
-					mux {
627
-						groups = "eth_mdio_x",
628
-						       "eth_mdc_x",
629
-						       "eth_rgmii_rx_clk_x",
630
-						       "eth_rx_dv_x",
631
-						       "eth_rxd0_x",
632
-						       "eth_rxd1_x",
633
-						       "eth_rxd2_rgmii",
634
-						       "eth_rxd3_rgmii",
635
-						       "eth_rgmii_tx_clk",
636
-						       "eth_txen_x",
637
-						       "eth_txd0_x",
638
-						       "eth_txd1_x",
639
-						       "eth_txd2_rgmii",
640
-						       "eth_txd3_rgmii";
641
-						function = "eth";
642
-					};
643
-				};
644
-
645
-				eth_rgmii_y_pins: eth-y-rgmii {
646
-					mux {
647
-						groups = "eth_mdio_y",
648
-						       "eth_mdc_y",
649
-						       "eth_rgmii_rx_clk_y",
650
-						       "eth_rx_dv_y",
651
-						       "eth_rxd0_y",
652
-						       "eth_rxd1_y",
653
-						       "eth_rxd2_rgmii",
654
-						       "eth_rxd3_rgmii",
655
-						       "eth_rgmii_tx_clk",
656
-						       "eth_txen_y",
657
-						       "eth_txd0_y",
658
-						       "eth_txd1_y",
659
-						       "eth_txd2_rgmii",
660
-						       "eth_txd3_rgmii";
661
-						function = "eth";
662
-					};
663
-				};
664
-
665
-				pdm_dclk_a14_pins: pdm_dclk_a14 {
666
-					mux {
667
-						groups = "pdm_dclk_a14";
668
-						function = "pdm";
669
-					};
670
-				};
671
-
672
-				pdm_dclk_a19_pins: pdm_dclk_a19 {
673
-					mux {
674
-						groups = "pdm_dclk_a19";
675
-						function = "pdm";
676
-					};
677
-				};
678
-
679
-				pdm_din0_pins: pdm_din0 {
680
-					mux {
681
-						groups = "pdm_din0";
682
-						function = "pdm";
683
-					};
684
-				};
685
-
686
-				pdm_din1_pins: pdm_din1 {
687
-					mux {
688
-						groups = "pdm_din1";
689
-						function = "pdm";
690
-					};
691
-				};
692
-
693
-				pdm_din2_pins: pdm_din2 {
694
-					mux {
695
-						groups = "pdm_din2";
696
-						function = "pdm";
697
-					};
698
-				};
699
-
700
-				pdm_din3_pins: pdm_din3 {
701
-					mux {
702
-						groups = "pdm_din3";
703
-						function = "pdm";
704
-					};
705
-				};
706
-
707
-				pwm_a_a_pins: pwm_a_a {
708
-					mux {
709
-						groups = "pwm_a_a";
710
-						function = "pwm_a";
711
-					};
712
-				};
713
-
714
-				pwm_a_x18_pins: pwm_a_x18 {
715
-					mux {
716
-						groups = "pwm_a_x18";
717
-						function = "pwm_a";
718
-					};
719
-				};
720
-
721
-				pwm_a_x20_pins: pwm_a_x20 {
722
-					mux {
723
-						groups = "pwm_a_x20";
724
-						function = "pwm_a";
725
-					};
726
-				};
727
-
728
-				pwm_a_z_pins: pwm_a_z {
729
-					mux {
730
-						groups = "pwm_a_z";
731
-						function = "pwm_a";
732
-					};
733
-				};
734
-
735
-				pwm_b_a_pins: pwm_b_a {
736
-					mux {
737
-						groups = "pwm_b_a";
738
-						function = "pwm_b";
739
-					};
740
-				};
741
-
742
-				pwm_b_x_pins: pwm_b_x {
743
-					mux {
744
-						groups = "pwm_b_x";
745
-						function = "pwm_b";
746
-					};
747
-				};
748
-
749
-				pwm_b_z_pins: pwm_b_z {
750
-					mux {
751
-						groups = "pwm_b_z";
752
-						function = "pwm_b";
753
-					};
754
-				};
755
-
756
-				pwm_c_a_pins: pwm_c_a {
757
-					mux {
758
-						groups = "pwm_c_a";
759
-						function = "pwm_c";
760
-					};
761
-				};
762
-
763
-				pwm_c_x10_pins: pwm_c_x10 {
764
-					mux {
765
-						groups = "pwm_c_x10";
766
-						function = "pwm_c";
767
-					};
768
-				};
769
-
770
-				pwm_c_x17_pins: pwm_c_x17 {
771
-					mux {
772
-						groups = "pwm_c_x17";
773
-						function = "pwm_c";
774
-					};
775
-				};
776
-
777
-				pwm_d_x11_pins: pwm_d_x11 {
778
-					mux {
779
-						groups = "pwm_d_x11";
780
-						function = "pwm_d";
781
-					};
782
-				};
783
-
784
-				pwm_d_x16_pins: pwm_d_x16 {
785
-					mux {
786
-						groups = "pwm_d_x16";
787
-						function = "pwm_d";
788
-					};
789
-				};
790
-
791
-				spdif_in_z_pins: spdif_in_z {
792
-					mux {
793
-						groups = "spdif_in_z";
794
-						function = "spdif_in";
795
-					};
796
-				};
797
-
798
-				spdif_in_a1_pins: spdif_in_a1 {
799
-					mux {
800
-						groups = "spdif_in_a1";
801
-						function = "spdif_in";
802
-					};
803
-				};
804
-
805
-				spdif_in_a7_pins: spdif_in_a7 {
806
-					mux {
807
-						groups = "spdif_in_a7";
808
-						function = "spdif_in";
809
-					};
810
-				};
811
-
812
-				spdif_in_a19_pins: spdif_in_a19 {
813
-					mux {
814
-						groups = "spdif_in_a19";
815
-						function = "spdif_in";
816
-					};
817
-				};
818
-
819
-				spdif_in_a20_pins: spdif_in_a20 {
820
-					mux {
821
-						groups = "spdif_in_a20";
822
-						function = "spdif_in";
823
-					};
824
-				};
825
-
826
-				spdif_out_z_pins: spdif_out_z {
827
-					mux {
828
-						groups = "spdif_out_z";
829
-						function = "spdif_out";
830
-					};
831
-				};
832
-
833
-				spdif_out_a1_pins: spdif_out_a1 {
834
-					mux {
835
-						groups = "spdif_out_a1";
836
-						function = "spdif_out";
837
-					};
838
-				};
839
-
840
-				spdif_out_a11_pins: spdif_out_a11 {
841
-					mux {
842
-						groups = "spdif_out_a11";
843
-						function = "spdif_out";
844
-					};
845
-				};
846
-
847
-				spdif_out_a19_pins: spdif_out_a19 {
848
-					mux {
849
-						groups = "spdif_out_a19";
850
-						function = "spdif_out";
851
-					};
852
-				};
853
-
854
-				spdif_out_a20_pins: spdif_out_a20 {
855
-					mux {
856
-						groups = "spdif_out_a20";
857
-						function = "spdif_out";
858
-					};
859
-				};
860
-
861
-				spi0_pins: spi0 {
862
-					mux {
863
-						groups = "spi0_miso",
864
-							"spi0_mosi",
865
-							"spi0_clk";
866
-						function = "spi0";
867
-					};
868
-				};
869
-
870
-				spi0_ss0_pins: spi0_ss0 {
871
-					mux {
872
-						groups = "spi0_ss0";
873
-						function = "spi0";
874
-					};
875
-				};
876
-
877
-				spi0_ss1_pins: spi0_ss1 {
878
-					mux {
879
-						groups = "spi0_ss1";
880
-						function = "spi0";
881
-					};
882
-				};
883
-
884
-				spi0_ss2_pins: spi0_ss2 {
885
-					mux {
886
-						groups = "spi0_ss2";
887
-						function = "spi0";
888
-					};
889
-				};
890
-
891
-
892
-				spi1_a_pins: spi1_a {
893
-					mux {
894
-						groups = "spi1_miso_a",
895
-							"spi1_mosi_a",
896
-							"spi1_clk_a";
897
-						function = "spi1";
898
-					};
899
-				};
900
-
901
-				spi1_ss0_a_pins: spi1_ss0_a {
902
-					mux {
903
-						groups = "spi1_ss0_a";
904
-						function = "spi1";
905
-					};
906
-				};
907
-
908
-				spi1_ss1_pins: spi1_ss1 {
909
-					mux {
910
-						groups = "spi1_ss1";
911
-						function = "spi1";
912
-					};
913
-				};
914
-
915
-				spi1_x_pins: spi1_x {
916
-					mux {
917
-						groups = "spi1_miso_x",
918
-							"spi1_mosi_x",
919
-							"spi1_clk_x";
920
-						function = "spi1";
921
-					};
922
-				};
923
-
924
-				spi1_ss0_x_pins: spi1_ss0_x {
925
-					mux {
926
-						groups = "spi1_ss0_x";
927
-						function = "spi1";
928
-					};
929
-				};
930
-
931
-				i2c0_pins: i2c0 {
932
-					mux {
933
-						groups = "i2c0_sck",
934
-							"i2c0_sda";
935
-						function = "i2c0";
936
-					};
937
-				};
938
-
939
-				i2c1_z_pins: i2c1_z {
940
-					mux {
941
-						groups = "i2c1_sck_z",
942
-							"i2c1_sda_z";
943
-						function = "i2c1";
944
-					};
945
-				};
946
-
947
-				i2c1_x_pins: i2c1_x {
948
-					mux {
949
-						groups = "i2c1_sck_x",
950
-							"i2c1_sda_x";
951
-						function = "i2c1";
952
-					};
953
-				};
954
-
955
-				i2c2_x_pins: i2c2_x {
956
-					mux {
957
-						groups = "i2c2_sck_x",
958
-							"i2c2_sda_x";
959
-						function = "i2c2";
960
-					};
961
-				};
962
-
963
-				i2c2_a_pins: i2c2_a {
964
-					mux {
965
-						groups = "i2c2_sck_a",
966
-							"i2c2_sda_a";
967
-						function = "i2c2";
968
-					};
969
-				};
970
-
971
-				i2c3_a6_pins: i2c3_a6 {
972
-					mux {
973
-						groups = "i2c3_sda_a6",
974
-							"i2c3_sck_a7";
975
-						function = "i2c3";
976
-					};
977
-				};
978
-
979
-				i2c3_a12_pins: i2c3_a12 {
980
-					mux {
981
-						groups = "i2c3_sda_a12",
982
-							"i2c3_sck_a13";
983
-						function = "i2c3";
984
-					};
985
-				};
986
-
987
-				i2c3_a19_pins: i2c3_a19 {
988
-					mux {
989
-						groups = "i2c3_sda_a19",
990
-							"i2c3_sck_a20";
991
-						function = "i2c3";
992
-					};
993
-				};
994
-
995
-				uart_a_pins: uart_a {
996
-					mux {
997
-						groups = "uart_tx_a",
998
-							"uart_rx_a";
999
-						function = "uart_a";
1000
-					};
1001
-				};
1002
-
1003
-				uart_a_cts_rts_pins: uart_a_cts_rts {
1004
-					mux {
1005
-						groups = "uart_cts_a",
1006
-							"uart_rts_a";
1007
-						function = "uart_a";
1008
-					};
1009
-				};
1010
-
1011
-				uart_b_x_pins: uart_b_x {
1012
-					mux {
1013
-						groups = "uart_tx_b_x",
1014
-							"uart_rx_b_x";
1015
-						function = "uart_b";
1016
-					};
1017
-				};
1018
-
1019
-				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1020
-					mux {
1021
-						groups = "uart_cts_b_x",
1022
-							"uart_rts_b_x";
1023
-						function = "uart_b";
1024
-					};
1025
-				};
1026
-
1027
-				uart_b_z_pins: uart_b_z {
1028
-					mux {
1029
-						groups = "uart_tx_b_z",
1030
-							"uart_rx_b_z";
1031
-						function = "uart_b";
1032
-					};
1033
-				};
1034
-
1035
-				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1036
-					mux {
1037
-						groups = "uart_cts_b_z",
1038
-							"uart_rts_b_z";
1039
-						function = "uart_b";
1040
-					};
1041
-				};
1042
-
1043
-				uart_ao_b_z_pins: uart_ao_b_z {
1044
-					mux {
1045
-						groups = "uart_ao_tx_b_z",
1046
-							"uart_ao_rx_b_z";
1047
-						function = "uart_ao_b_z";
1048
-					};
1049
-				};
1050
-
1051
-				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1052
-					mux {
1053
-						groups = "uart_ao_cts_b_z",
1054
-							"uart_ao_rts_b_z";
1055
-						function = "uart_ao_b_z";
1056
-					};
1057
-				};
1058
-
1059
-				mclk_b_pins: mclk_b {
1060
-					mux {
1061
-						groups = "mclk_b";
1062
-						function = "mclk_b";
1063
-					};
1064
-				};
1065
-
1066
-				mclk_c_pins: mclk_c {
1067
-					mux {
1068
-						groups = "mclk_c";
1069
-						function = "mclk_c";
1070
-					};
1071
-				};
1072
-
1073
-				tdma_sclk_pins: tdma_sclk {
1074
-					mux {
1075
-						groups = "tdma_sclk";
1076
-						function = "tdma";
1077
-					};
1078
-				};
1079
-
1080
-				tdma_sclk_slv_pins: tdma_sclk_slv {
1081
-					mux {
1082
-						groups = "tdma_sclk_slv";
1083
-						function = "tdma";
1084
-					};
1085
-				};
1086
-
1087
-				tdma_fs_pins: tdma_fs {
1088
-					mux {
1089
-						groups = "tdma_fs";
1090
-						function = "tdma";
1091
-					};
1092
-				};
1093
-
1094
-				tdma_fs_slv_pins: tdma_fs_slv {
1095
-					mux {
1096
-						groups = "tdma_fs_slv";
1097
-						function = "tdma";
1098
-					};
1099
-				};
1100
-
1101
-				tdma_din0_pins: tdma_din0 {
1102
-					mux {
1103
-						groups = "tdma_din0";
1104
-						function = "tdma";
1105
-					};
1106
-				};
1107
-
1108
-				tdma_dout0_x14_pins: tdma_dout0_x14 {
1109
-					mux {
1110
-						groups = "tdma_dout0_x14";
1111
-						function = "tdma";
1112
-					};
1113
-				};
1114
-
1115
-				tdma_dout0_x15_pins: tdma_dout0_x15 {
1116
-					mux {
1117
-						groups = "tdma_dout0_x15";
1118
-						function = "tdma";
1119
-					};
1120
-				};
1121
-
1122
-				tdma_dout1_pins: tdma_dout1 {
1123
-					mux {
1124
-						groups = "tdma_dout1";
1125
-						function = "tdma";
1126
-					};
1127
-				};
1128
-
1129
-				tdma_din1_pins: tdma_din1 {
1130
-					mux {
1131
-						groups = "tdma_din1";
1132
-						function = "tdma";
1133
-					};
1134
-				};
1135
-
1136
-				tdmb_sclk_pins: tdmb_sclk {
1137
-					mux {
1138
-						groups = "tdmb_sclk";
1139
-						function = "tdmb";
1140
-					};
1141
-				};
1142
-
1143
-				tdmb_sclk_slv_pins: tdmb_sclk_slv {
1144
-					mux {
1145
-						groups = "tdmb_sclk_slv";
1146
-						function = "tdmb";
1147
-					};
1148
-				};
1149
-
1150
-				tdmb_fs_pins: tdmb_fs {
1151
-					mux {
1152
-						groups = "tdmb_fs";
1153
-						function = "tdmb";
1154
-					};
1155
-				};
1156
-
1157
-				tdmb_fs_slv_pins: tdmb_fs_slv {
1158
-					mux {
1159
-						groups = "tdmb_fs_slv";
1160
-						function = "tdmb";
1161
-					};
1162
-				};
1163
-
1164
-				tdmb_din0_pins: tdmb_din0 {
1165
-					mux {
1166
-						groups = "tdmb_din0";
1167
-						function = "tdmb";
1168
-					};
1169
-				};
1170
-
1171
-				tdmb_dout0_pins: tdmb_dout0 {
1172
-					mux {
1173
-						groups = "tdmb_dout0";
1174
-						function = "tdmb";
1175
-					};
1176
-				};
1177
-
1178
-				tdmb_din1_pins: tdmb_din1 {
1179
-					mux {
1180
-						groups = "tdmb_din1";
1181
-						function = "tdmb";
1182
-					};
1183
-				};
1184
-
1185
-				tdmb_dout1_pins: tdmb_dout1 {
1186
-					mux {
1187
-						groups = "tdmb_dout1";
1188
-						function = "tdmb";
1189
-					};
1190
-				};
1191
-
1192
-				tdmb_din2_pins: tdmb_din2 {
1193
-					mux {
1194
-						groups = "tdmb_din2";
1195
-						function = "tdmb";
1196
-					};
1197
-				};
1198
-
1199
-				tdmb_dout2_pins: tdmb_dout2 {
1200
-					mux {
1201
-						groups = "tdmb_dout2";
1202
-						function = "tdmb";
1203
-					};
1204
-				};
1205
-
1206
-				tdmb_din3_pins: tdmb_din3 {
1207
-					mux {
1208
-						groups = "tdmb_din3";
1209
-						function = "tdmb";
1210
-					};
1211
-				};
1212
-
1213
-				tdmb_dout3_pins: tdmb_dout3 {
1214
-					mux {
1215
-						groups = "tdmb_dout3";
1216
-						function = "tdmb";
1217
-					};
1218
-				};
1219
-
1220
-				tdmc_sclk_pins: tdmc_sclk {
1221
-					mux {
1222
-						groups = "tdmc_sclk";
1223
-						function = "tdmc";
1224
-					};
1225
-				};
1226
-
1227
-				tdmc_sclk_slv_pins: tdmc_sclk_slv {
1228
-					mux {
1229
-						groups = "tdmc_sclk_slv";
1230
-						function = "tdmc";
1231
-					};
1232
-				};
1233
-
1234
-				tdmc_fs_pins: tdmc_fs {
1235
-					mux {
1236
-						groups = "tdmc_fs";
1237
-						function = "tdmc";
1238
-					};
1239
-				};
1240
-
1241
-				tdmc_fs_slv_pins: tdmc_fs_slv {
1242
-					mux {
1243
-						groups = "tdmc_fs_slv";
1244
-						function = "tdmc";
1245
-					};
1246
-				};
1247
-
1248
-				tdmc_din0_pins: tdmc_din0 {
1249
-					mux {
1250
-						groups = "tdmc_din0";
1251
-						function = "tdmc";
1252
-					};
1253
-				};
1254
-
1255
-				tdmc_dout0_pins: tdmc_dout0 {
1256
-					mux {
1257
-						groups = "tdmc_dout0";
1258
-						function = "tdmc";
1259
-					};
1260
-				};
1261
-
1262
-				tdmc_din1_pins: tdmc_din1 {
1263
-					mux {
1264
-						groups = "tdmc_din1";
1265
-						function = "tdmc";
1266
-					};
1267
-				};
1268
-
1269
-				tdmc_dout1_pins: tdmc_dout1 {
1270
-					mux {
1271
-						groups = "tdmc_dout1";
1272
-						function = "tdmc";
1273
-					};
1274
-				};
1275
-
1276
-				tdmc_din2_pins: tdmc_din2 {
1277
-					mux {
1278
-						groups = "tdmc_din2";
1279
-						function = "tdmc";
1280
-					};
1281
-				};
1282
-
1283
-				tdmc_dout2_pins: tdmc_dout2 {
1284
-					mux {
1285
-						groups = "tdmc_dout2";
1286
-						function = "tdmc";
1287
-					};
1288
-				};
1289
-
1290
-				tdmc_din3_pins: tdmc_din3 {
1291
-					mux {
1292
-						groups = "tdmc_din3";
1293
-						function = "tdmc";
1294
-					};
1295
-				};
1296
-
1297
-				tdmc_dout3_pins: tdmc_dout3 {
1298
-					mux {
1299
-						groups = "tdmc_dout3";
1300
-						function = "tdmc";
1301
-					};
1302
-				};
1778
+			usb2_phy1: phy@9020 {
1779
+				compatible = "amlogic,meson-gxl-usb2-phy";
1780
+				#phy-cells = <0>;
1781
+				reg = <0x0 0x9020 0x0 0x20>;
1782
+				clocks = <&clkc CLKID_USB>;
1783
+				clock-names = "phy";
1784
+				resets = <&reset RESET_USB_OTG>;
1785
+				reset-names = "phy";
13031786 			};
13041787 		};
13051788 
13061789 		sram: sram@fffc0000 {
1307
-			compatible = "amlogic,meson-axg-sram", "mmio-sram";
1790
+			compatible = "mmio-sram";
13081791 			reg = <0x0 0xfffc0000 0x0 0x20000>;
13091792 			#address-cells = <1>;
13101793 			#size-cells = <1>;
13111794 			ranges = <0 0x0 0xfffc0000 0x20000>;
13121795 
1313
-			cpu_scp_lpri: scp-shmem@0 {
1796
+			cpu_scp_lpri: scp-sram@13000 {
13141797 				compatible = "amlogic,meson-axg-scp-shmem";
13151798 				reg = <0x13000 0x400>;
13161799 			};
13171800 
1318
-			cpu_scp_hpri: scp-shmem@200 {
1801
+			cpu_scp_hpri: scp-sram@13400 {
13191802 				compatible = "amlogic,meson-axg-scp-shmem";
13201803 				reg = <0x13400 0x400>;
13211804 			};
13221805 		};
1806
+	};
13231807 
1324
-		aobus: bus@ff800000 {
1325
-			compatible = "simple-bus";
1326
-			reg = <0x0 0xff800000 0x0 0x100000>;
1327
-			#address-cells = <2>;
1328
-			#size-cells = <2>;
1329
-			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1808
+	timer {
1809
+		compatible = "arm,armv8-timer";
1810
+		interrupts = <GIC_PPI 13
1811
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1812
+			     <GIC_PPI 14
1813
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1814
+			     <GIC_PPI 11
1815
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1816
+			     <GIC_PPI 10
1817
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1818
+	};
13301819 
1331
-			sysctrl_AO: sys-ctrl@0 {
1332
-				compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
1333
-				reg =  <0x0 0x0 0x0 0x100>;
1334
-
1335
-				clkc_AO: clock-controller {
1336
-					compatible = "amlogic,meson-axg-aoclkc";
1337
-					#clock-cells = <1>;
1338
-					#reset-cells = <1>;
1339
-				};
1340
-			};
1341
-
1342
-			pinctrl_aobus: pinctrl@14 {
1343
-				compatible = "amlogic,meson-axg-aobus-pinctrl";
1344
-				#address-cells = <2>;
1345
-				#size-cells = <2>;
1346
-				ranges;
1347
-
1348
-				gpio_ao: bank@14 {
1349
-					reg = <0x0 0x00014 0x0 0x8>,
1350
-						<0x0 0x0002c 0x0 0x4>,
1351
-						<0x0 0x00024 0x0 0x8>;
1352
-					reg-names = "mux", "pull", "gpio";
1353
-					gpio-controller;
1354
-					#gpio-cells = <2>;
1355
-					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1356
-				};
1357
-
1358
-				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1359
-					mux {
1360
-						groups = "i2c_ao_sck_4";
1361
-						function = "i2c_ao";
1362
-					};
1363
-				};
1364
-
1365
-				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1366
-					mux {
1367
-						groups = "i2c_ao_sck_8";
1368
-						function = "i2c_ao";
1369
-					};
1370
-				};
1371
-
1372
-				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1373
-					mux {
1374
-						groups = "i2c_ao_sck_10";
1375
-						function = "i2c_ao";
1376
-					};
1377
-				};
1378
-
1379
-				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1380
-					mux {
1381
-						groups = "i2c_ao_sda_5";
1382
-						function = "i2c_ao";
1383
-					};
1384
-				};
1385
-
1386
-				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1387
-					mux {
1388
-						groups = "i2c_ao_sda_9";
1389
-						function = "i2c_ao";
1390
-					};
1391
-				};
1392
-
1393
-				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1394
-					mux {
1395
-						groups = "i2c_ao_sda_11";
1396
-						function = "i2c_ao";
1397
-					};
1398
-				};
1399
-
1400
-				remote_input_ao_pins: remote_input_ao {
1401
-					mux {
1402
-						groups = "remote_input_ao";
1403
-						function = "remote_input_ao";
1404
-					};
1405
-				};
1406
-
1407
-				uart_ao_a_pins: uart_ao_a {
1408
-					mux {
1409
-						groups = "uart_ao_tx_a",
1410
-							"uart_ao_rx_a";
1411
-						function = "uart_ao_a";
1412
-					};
1413
-				};
1414
-
1415
-				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1416
-					mux {
1417
-						groups = "uart_ao_cts_a",
1418
-							"uart_ao_rts_a";
1419
-						function = "uart_ao_a";
1420
-					};
1421
-				};
1422
-
1423
-				uart_ao_b_pins: uart_ao_b {
1424
-					mux {
1425
-						groups = "uart_ao_tx_b",
1426
-							"uart_ao_rx_b";
1427
-						function = "uart_ao_b";
1428
-					};
1429
-				};
1430
-
1431
-				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1432
-					mux {
1433
-						groups = "uart_ao_cts_b",
1434
-							"uart_ao_rts_b";
1435
-						function = "uart_ao_b";
1436
-					};
1437
-				};
1438
-			};
1439
-
1440
-			sec_AO: ao-secure@140 {
1441
-				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1442
-				reg = <0x0 0x140 0x0 0x140>;
1443
-				amlogic,has-chip-id;
1444
-			};
1445
-
1446
-			pwm_AO_ab: pwm@7000 {
1447
-				compatible = "amlogic,meson-axg-ao-pwm";
1448
-				reg = <0x0 0x07000 0x0 0x20>;
1449
-				#pwm-cells = <3>;
1450
-				status = "disabled";
1451
-			};
1452
-
1453
-			pwm_AO_cd: pwm@2000 {
1454
-				compatible = "amlogic,meson-axg-ao-pwm";
1455
-				reg = <0x0 0x02000  0x0 0x20>;
1456
-				#pwm-cells = <3>;
1457
-				status = "disabled";
1458
-			};
1459
-
1460
-			i2c_AO: i2c@5000 {
1461
-				compatible = "amlogic,meson-axg-i2c";
1462
-				reg = <0x0 0x05000 0x0 0x20>;
1463
-				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1464
-				clocks = <&clkc CLKID_AO_I2C>;
1465
-				#address-cells = <1>;
1466
-				#size-cells = <0>;
1467
-				status = "disabled";
1468
-			};
1469
-
1470
-			uart_AO: serial@3000 {
1471
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1472
-				reg = <0x0 0x3000 0x0 0x18>;
1473
-				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1474
-				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1475
-				clock-names = "xtal", "pclk", "baud";
1476
-				status = "disabled";
1477
-			};
1478
-
1479
-			uart_AO_B: serial@4000 {
1480
-				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1481
-				reg = <0x0 0x4000 0x0 0x18>;
1482
-				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1483
-				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1484
-				clock-names = "xtal", "pclk", "baud";
1485
-				status = "disabled";
1486
-			};
1487
-
1488
-			ir: ir@8000 {
1489
-				compatible = "amlogic,meson-gxbb-ir";
1490
-				reg = <0x0 0x8000 0x0 0x20>;
1491
-				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1492
-				status = "disabled";
1493
-			};
1494
-
1495
-			saradc: adc@9000 {
1496
-				compatible = "amlogic,meson-axg-saradc",
1497
-					"amlogic,meson-saradc";
1498
-				reg = <0x0 0x9000 0x0 0x38>;
1499
-				#io-channel-cells = <1>;
1500
-				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1501
-				clocks = <&xtal>,
1502
-					<&clkc_AO CLKID_AO_SAR_ADC>,
1503
-					<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1504
-					<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1505
-				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1506
-				status = "disabled";
1507
-			};
1508
-		};
1820
+	xtal: xtal-clk {
1821
+		compatible = "fixed-clock";
1822
+		clock-frequency = <24000000>;
1823
+		clock-output-names = "xtal";
1824
+		#clock-cells = <0>;
15091825 	};
15101826 };