.. | .. |
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1 | 1 | // SPDX-License-Identifier: GPL-2.0 |
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2 | 2 | /dts-v1/; |
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3 | 3 | |
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4 | | -/include/ "skeleton.dtsi" |
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5 | | - |
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6 | 4 | #include <dt-bindings/interrupt-controller/irq.h> |
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7 | 5 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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8 | 6 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> |
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9 | 7 | #include <dt-bindings/soc/qcom,gsbi.h> |
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10 | 8 | |
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11 | 9 | / { |
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| 10 | + #address-cells = <1>; |
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| 11 | + #size-cells = <1>; |
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12 | 12 | model = "Qualcomm MSM8660"; |
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13 | 13 | compatible = "qcom,msm8660"; |
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14 | 14 | interrupt-parent = <&intc>; |
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.. | .. |
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37 | 37 | compatible = "cache"; |
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38 | 38 | cache-level = <2>; |
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39 | 39 | }; |
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| 40 | + }; |
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| 41 | + |
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| 42 | + memory { |
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| 43 | + device_type = "memory"; |
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| 44 | + reg = <0x0 0x0>; |
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40 | 45 | }; |
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41 | 46 | |
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42 | 47 | cpu-pmu { |
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.. | .. |
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110 | 115 | reg = <0x800000 0x4000>; |
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111 | 116 | |
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112 | 117 | gpio-controller; |
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| 118 | + gpio-ranges = <&tlmm 0 0 173>; |
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113 | 119 | #gpio-cells = <2>; |
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114 | 120 | interrupts = <0 16 0x4>; |
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115 | 121 | interrupt-controller; |
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.. | .. |
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133 | 139 | #address-cells = <1>; |
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134 | 140 | #size-cells = <1>; |
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135 | 141 | ranges; |
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| 142 | + status = "disabled"; |
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136 | 143 | |
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137 | 144 | syscon-tcsr = <&tcsr>; |
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138 | 145 | |
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.. | .. |
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140 | 147 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
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141 | 148 | reg = <0x16540000 0x1000>, |
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142 | 149 | <0x16500000 0x1000>; |
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143 | | - interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>; |
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| 150 | + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
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144 | 151 | clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; |
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145 | 152 | clock-names = "core", "iface"; |
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146 | 153 | status = "disabled"; |
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.. | .. |
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149 | 156 | gsbi6_i2c: i2c@16580000 { |
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150 | 157 | compatible = "qcom,i2c-qup-v1.1.1"; |
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151 | 158 | reg = <0x16580000 0x1000>; |
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152 | | - interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; |
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| 159 | + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
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153 | 160 | clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; |
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154 | 161 | clock-names = "core", "iface"; |
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155 | 162 | #address-cells = <1>; |
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.. | .. |
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167 | 174 | #address-cells = <1>; |
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168 | 175 | #size-cells = <1>; |
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169 | 176 | ranges; |
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| 177 | + status = "disabled"; |
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170 | 178 | |
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171 | 179 | syscon-tcsr = <&tcsr>; |
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172 | 180 | |
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.. | .. |
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174 | 182 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
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175 | 183 | reg = <0x16640000 0x1000>, |
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176 | 184 | <0x16600000 0x1000>; |
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177 | | - interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>; |
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| 185 | + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
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178 | 186 | clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; |
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179 | 187 | clock-names = "core", "iface"; |
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180 | 188 | status = "disabled"; |
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.. | .. |
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183 | 191 | gsbi7_i2c: i2c@16680000 { |
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184 | 192 | compatible = "qcom,i2c-qup-v1.1.1"; |
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185 | 193 | reg = <0x16680000 0x1000>; |
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186 | | - interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; |
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| 194 | + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
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187 | 195 | clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; |
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188 | 196 | clock-names = "core", "iface"; |
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189 | 197 | #address-cells = <1>; |
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.. | .. |
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207 | 215 | gsbi8_i2c: i2c@19880000 { |
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208 | 216 | compatible = "qcom,i2c-qup-v1.1.1"; |
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209 | 217 | reg = <0x19880000 0x1000>; |
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210 | | - interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>; |
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| 218 | + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; |
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211 | 219 | clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; |
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212 | 220 | clock-names = "core", "iface"; |
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213 | 221 | #address-cells = <1>; |
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.. | .. |
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232 | 240 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
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233 | 241 | reg = <0x19c40000 0x1000>, |
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234 | 242 | <0x19c00000 0x1000>; |
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235 | | - interrupts = <0 195 IRQ_TYPE_NONE>; |
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| 243 | + interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; |
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236 | 244 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; |
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237 | 245 | clock-names = "core", "iface"; |
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238 | 246 | status = "disabled"; |
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.. | .. |
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241 | 249 | gsbi12_i2c: i2c@19c80000 { |
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242 | 250 | compatible = "qcom,i2c-qup-v1.1.1"; |
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243 | 251 | reg = <0x19c80000 0x1000>; |
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244 | | - interrupts = <0 196 IRQ_TYPE_NONE>; |
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| 252 | + interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; |
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245 | 253 | clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; |
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246 | 254 | clock-names = "core", "iface"; |
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247 | 255 | #address-cells = <1>; |
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.. | .. |
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285 | 293 | compatible = "qcom,pm8058-gpio", |
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286 | 294 | "qcom,ssbi-gpio"; |
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287 | 295 | reg = <0x150>; |
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288 | | - interrupt-parent = <&pm8058>; |
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289 | | - interrupts = <192 IRQ_TYPE_NONE>, |
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290 | | - <193 IRQ_TYPE_NONE>, |
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291 | | - <194 IRQ_TYPE_NONE>, |
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292 | | - <195 IRQ_TYPE_NONE>, |
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293 | | - <196 IRQ_TYPE_NONE>, |
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294 | | - <197 IRQ_TYPE_NONE>, |
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295 | | - <198 IRQ_TYPE_NONE>, |
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296 | | - <199 IRQ_TYPE_NONE>, |
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297 | | - <200 IRQ_TYPE_NONE>, |
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298 | | - <201 IRQ_TYPE_NONE>, |
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299 | | - <202 IRQ_TYPE_NONE>, |
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300 | | - <203 IRQ_TYPE_NONE>, |
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301 | | - <204 IRQ_TYPE_NONE>, |
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302 | | - <205 IRQ_TYPE_NONE>, |
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303 | | - <206 IRQ_TYPE_NONE>, |
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304 | | - <207 IRQ_TYPE_NONE>, |
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305 | | - <208 IRQ_TYPE_NONE>, |
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306 | | - <209 IRQ_TYPE_NONE>, |
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307 | | - <210 IRQ_TYPE_NONE>, |
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308 | | - <211 IRQ_TYPE_NONE>, |
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309 | | - <212 IRQ_TYPE_NONE>, |
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310 | | - <213 IRQ_TYPE_NONE>, |
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311 | | - <214 IRQ_TYPE_NONE>, |
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312 | | - <215 IRQ_TYPE_NONE>, |
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313 | | - <216 IRQ_TYPE_NONE>, |
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314 | | - <217 IRQ_TYPE_NONE>, |
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315 | | - <218 IRQ_TYPE_NONE>, |
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316 | | - <219 IRQ_TYPE_NONE>, |
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317 | | - <220 IRQ_TYPE_NONE>, |
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318 | | - <221 IRQ_TYPE_NONE>, |
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319 | | - <222 IRQ_TYPE_NONE>, |
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320 | | - <223 IRQ_TYPE_NONE>, |
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321 | | - <224 IRQ_TYPE_NONE>, |
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322 | | - <225 IRQ_TYPE_NONE>, |
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323 | | - <226 IRQ_TYPE_NONE>, |
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324 | | - <227 IRQ_TYPE_NONE>, |
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325 | | - <228 IRQ_TYPE_NONE>, |
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326 | | - <229 IRQ_TYPE_NONE>, |
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327 | | - <230 IRQ_TYPE_NONE>, |
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328 | | - <231 IRQ_TYPE_NONE>, |
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329 | | - <232 IRQ_TYPE_NONE>, |
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330 | | - <233 IRQ_TYPE_NONE>, |
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331 | | - <234 IRQ_TYPE_NONE>, |
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332 | | - <235 IRQ_TYPE_NONE>; |
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| 296 | + interrupt-controller; |
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| 297 | + #interrupt-cells = <2>; |
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333 | 298 | gpio-controller; |
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| 299 | + gpio-ranges = <&pm8058_gpio 0 0 44>; |
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334 | 300 | #gpio-cells = <2>; |
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335 | 301 | |
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336 | 302 | }; |
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