forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-02-18 a08c8b75ee83d7f62c9aefc23bfb42082aa4076c 
 kernel/arch/arm64/boot/dts/rockchip/NK-R36S0.dtsi
....@@ -8,6 +8,7 @@
88 
99 #include <dt-bindings/gpio/gpio.h>
1010 #include <dt-bindings/pinctrl/rockchip.h>
11
+#include <dt-bindings/display/media-bus-format.h>
1112 #include "rk3568.dtsi"
1213 #include "rk3568-evb.dtsi"
1314 
....@@ -58,7 +59,9 @@
5859 		regulator-name = "vcc3v3_pcie";
5960 		regulator-min-microvolt = <3300000>;
6061 		regulator-max-microvolt = <3300000>;
62
+		regulator-always-on;
6163 		enable-active-high;
64
+		regulator-boot-on;
6265 		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
6366 		startup-delay-us = <5000>;
6467 		vin-supply = <&dc_12v>;
....@@ -88,13 +91,9 @@
8891 
8992 	    nk_io_init {
9093                 compatible = "nk_io_control";
91
-//				usb_en_oc_gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;  //USB_EN_OC_GPIO0_A5
92
-				lcd_bk_en_gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
93
-				lcd_pwblk_gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;  //LCD0_BKLT_EN_3V3
9494 				vcc3_io_en_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; //VCC3_IO_EN_GPIO0_C4_3V3
9595                 hub_host2_5V_rest_gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //HUB_RST_GPIO4_D2_3V3
9696                 hub_host3_5v_gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; //HOST3_EN_GPIO4_B2_1V8
97
-//              hub_host3_5V_rest_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 
9897                 vcc_5v_io = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;   //VCC5_IO_EN_GPIO1_A4_3V3
9998                 vcc_12v_io = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; //VCC12_IO_EN_GPIO0_C7_3V3
10099                 en_4g_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; //4G_PWREN_H_GPIO0_C6
....@@ -102,23 +101,55 @@
102101                 air_mode_4g_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; //4G_AIR_MODE_GPIO01_B0_3V3
103102                 wake_4g_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; //4G_WAKEUP_GPIO01_B1_3V3
104103 				hp_en_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;//HP_EN_GPIO3_A6_3V3
105
-                spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3
106
-				
107
-				edp_enable_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
108
-                edp_gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; //7511_GPIO0-GPIO3_D2
109
-				edp_gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; //7511_GPIO1-GPIO3_D3
110
-				edp_gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; //7511_GPIO2-GPIO3_D4
111
-				edp_gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //7511_GPIO3-GPIO3_D5
112
-                edp_reset = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
113
-//              tp_reset = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
114
-//              vddio_mipi = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
115
-		
104
+                spk_out_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;//AMP_SD_GPIO4_C2_3V3			
116105 				wifi_power_en_gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; //WIFI_PWREN_GPIO3_C6_1V8
117
-
106
+//				pcie_power_en_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;//PCIE_PWREN_H_GPIO0_D4				
118107 				pinctrl-names = "default";
119
-				pinctrl-0 = <&nk_io_gpio>;
120
-				nodka_lvds = <9>;
108
+				pinctrl-0 = <&nk_io_gpio>;				
121109         };
110
+		
111
+		panel: panel {
112
+				compatible = "simple-panel";
113
+				backlight = <&backlight>;
114
+				power-supply = <&vcc3v3_lcd0_n>;
115
+				enable-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; //LCD0_VDD_H_GPIO2_D4
116
+				reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //7511_RST_GPIO3_D1
117
+				edp-bl-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;  //LCD0_BKLT_EN_3V3
118
+				edp-bl-en = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; //LCD0_BKLT_EN_3V3
119
+				bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
120
+				bpc = <8>;
121
+				prepare-delay-ms = <200>;
122
+				enable-delay-ms = <20>;
123
+				lvds-gpio0 = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; //7511_GPIO0-GPIO3_D2 
124
+				lvds-gpio1 = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; //7511_GPIO1-GPIO3_D3 
125
+				lvds-gpio2 = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; //7511_GPIO2-GPIO3_D4 
126
+				lvds-gpio3 = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; //7511_GPIO3-GPIO3_D5
127
+				nodka-lvds = <9>;
128
+
129
+				display-timings {
130
+                native-mode = <&timing0>;
131
+                timing0: timing0 {
132
+					clock-frequency = <142300000>;
133
+					hactive = <1920>;
134
+					vactive = <1080>;
135
+					hfront-porch = <48>;
136
+					hsync-len = <32>;
137
+					hback-porch = <100>;
138
+					vfront-porch = <7>;
139
+					vsync-len = <20>;
140
+					vback-porch = <23>;
141
+					hsync-active = <0>;
142
+					vsync-active = <0>;
143
+					de-active = <0>;
144
+					pixelclk-active = <0>;			
145
+					};
146
+				};
147
+				ports {
148
+					panel_in: endpoint {
149
+					remote-endpoint = <&edp_out>;
150
+						};
151
+					};   
152
+				};
122153 };
123154 
124155 &combphy0_us {
....@@ -134,11 +165,11 @@
134165 };
135166 
136167 &csi2_dphy_hw {
137
-	status = "okay";
168
+	status = "disabled";
138169 };
139170 
140171 &csi2_dphy0 {
141
-	status = "okay";
172
+	status = "disabled";
142173 
143174 	ports {
144175 		#address-cells = <1>;
....@@ -181,8 +212,12 @@
181212  * video_phy0 needs to be enabled
182213  * when dsi0 is enabled
183214  */
215
+&video_phy0 {
216
+	status = "disabled";
217
+};
218
+
184219 &dsi0 {
185
-	status = "okay";
220
+	status = "disabled";
186221 };
187222 
188223 &dsi0_in_vp0 {
....@@ -190,7 +225,7 @@
190225 };
191226 
192227 &dsi0_in_vp1 {
193
-	status = "okay";
228
+	status = "disabled";
194229 };
195230 
196231 &dsi0_panel {
....@@ -201,6 +236,10 @@
201236  * video_phy1 needs to be enabled
202237  * when dsi1 is enabled
203238  */
239
+ 
240
+&video_phy1 {
241
+	status = "disabled";
242
+}; 
204243 &dsi1 {
205244 	status = "disabled";
206245 };
....@@ -217,22 +256,82 @@
217256 	power-supply = <&vcc3v3_lcd1_n>;
218257 };
219258 
259
+/*
260
+*  edp_start
261
+*/
262
+
220263 &edp {
221
-	hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
222
-	status = "okay";
264
+    force-hpd;
265
+    status = "okay";
266
+    ports {
267
+        port@1 {
268
+            reg = <1>;
269
+            edp_out: endpoint {
270
+                remote-endpoint = <&panel_in>;
271
+            };
272
+        };
273
+    };
223274 };
224275 
225276 &edp_phy {
226
-	status = "okay";
277
+    status = "okay";
227278 };
228279 
229280 &edp_in_vp0 {
230
-	status = "okay";
281
+    status = "disabled";
231282 };
232283 
233284 &edp_in_vp1 {
285
+    status = "okay";
286
+};
287
+
288
+&route_edp {
289
+    status = "okay";
290
+    connect = <&vp1_out_edp>;
291
+};
292
+
293
+&route_edp {
294
+	status = "okay";
295
+};
296
+/*
297
+*  edp_end
298
+*/
299
+
300
+/*
301
+*  Hdmi_start
302
+*/
303
+
304
+&hdmi {
305
+	status = "okay";
306
+	rockchip,phy-table =
307
+		<92812500  0x8009 0x0000 0x0270>,
308
+		<165000000 0x800b 0x0000 0x026d>,
309
+		<185625000 0x800b 0x0000 0x01ed>,
310
+		<297000000 0x800b 0x0000 0x01ad>,
311
+		<594000000 0x8029 0x0000 0x0088>,
312
+		<000000000 0x0000 0x0000 0x0000>;
313
+};
314
+
315
+&route_hdmi {
316
+	status = "okay";
317
+	connect = <&vp0_out_hdmi>;
318
+};
319
+
320
+&hdmi_in_vp0 {
321
+	status = "okay";
322
+};
323
+
324
+&hdmi_in_vp1 {
234325 	status = "disabled";
235326 };
327
+
328
+&hdmi_sound {
329
+	status = "okay";
330
+};
331
+
332
+/*
333
+ *  Hdmi_END
334
+*/
236335 
237336 &gmac0 {
238337 	phy-mode = "rgmii";
....@@ -310,9 +409,6 @@
310409                 compatible = "nk_mcu";
311410                 reg = <0x15>;
312411         };
313
-
314
-
315
-
316412 };
317413 
318414 &i2c4 {
....@@ -385,6 +481,19 @@
385481 	};
386482 };
387483 
484
+&i2c5 {
485
+	status = "okay";
486
+
487
+	hym8563: hym8563@51 {
488
+		compatible = "haoyu,hym8563";
489
+		reg = <0x51>;
490
+		#clock-cells = <0>;
491
+		clock-frequency = <32768>;
492
+		clock-output-names = "xin32k";
493
+		/* rtc_int is not connected */
494
+	};
495
+};
496
+
388497 &mdio0 {
389498 	rgmii_phy0: phy@0 {
390499 		compatible = "ethernet-phy-ieee802.3-c22";
....@@ -399,20 +508,14 @@
399508 	};
400509 };
401510 
402
-&video_phy0 {
403
-	status = "okay";
404
-};
405511 
406
-&video_phy1 {
407
-	status = "disabled";
408
-};
409512 
410513 &pcie30phy {
411514 	status = "okay";
412515 };
413516 
414
-&pcie3x2 {
415
-	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
517
+&pcie2x1 {
518
+	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
416519 	vpcie3v3-supply = <&vcc3v3_pcie>;
417520 	status = "okay";
418521 };
....@@ -467,15 +570,15 @@
467570 };
468571 
469572 &rkisp {
470
-	status = "okay";
573
+	status = "disabled";
471574 };
472575 
473576 &rkisp_mmu {
474
-	status = "okay";
577
+	status = "disabled";
475578 };
476579 
477580 &rkisp_vir0 {
478
-	status = "okay";
581
+	status = "disabled";
479582 
480583 	port {
481584 		#address-cells = <1>;
....@@ -489,14 +592,11 @@
489592 };
490593 
491594 &route_dsi0 {
492
-	status = "okay";
595
+	status = "disabled";
493596 	connect = <&vp1_out_dsi0>;
494597 };
495598 
496
-&route_edp {
497
-	status = "okay";
498
-	connect = <&vp0_out_edp>;
499
-};
599
+
500600 
501601 &sata2 {
502602 	status = "okay";
....@@ -535,7 +635,7 @@
535635 };
536636 
537637 &vcc3v3_lcd0_n {
538
-	gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
638
+	gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; 
539639 	enable-active-high;
540640 };
541641