.. | .. |
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97 | 97 | return false; |
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98 | 98 | } |
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99 | 99 | |
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| 100 | +static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode) |
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| 101 | +{ |
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| 102 | + /* |
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| 103 | + * The default component order of serial rgb3x8 formats |
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| 104 | + * is BGR. So it is needed to enable RB swap. |
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| 105 | + */ |
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| 106 | + if (bus_format == MEDIA_BUS_FMT_SRGB888_3X8 || |
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| 107 | + bus_format == MEDIA_BUS_FMT_SRGB888_DUMMY_4X8) |
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| 108 | + return true; |
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| 109 | + else |
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| 110 | + return false; |
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| 111 | +} |
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| 112 | + |
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100 | 113 | static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) |
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101 | 114 | { |
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102 | 115 | struct crtc_state *crtc_state = &state->crtc_state; |
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.. | .. |
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298 | 311 | VOP_CTRL_SET(vop, win_channel[2], 0x56); |
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299 | 312 | VOP_CTRL_SET(vop, dsp_blank, 0); |
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300 | 313 | |
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301 | | - dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; |
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| 314 | + dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0; |
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302 | 315 | /* For improving signal quality, dclk need to be inverted by default on rv1106. */ |
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303 | 316 | if ((VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) == 12)) |
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304 | 317 | dclk_inv = !dclk_inv; |
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.. | .. |
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403 | 416 | VOP_CTRL_SET(vop, hdmi_dclk_out_en, |
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404 | 417 | conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); |
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405 | 418 | |
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406 | | - if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) |
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407 | | - VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); |
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| 419 | + if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) || |
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| 420 | + is_rb_swap(conn_state->bus_format, conn_state->output_mode)) |
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| 421 | + VOP_CTRL_SET(vop, dsp_rb_swap, 1); |
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408 | 422 | else |
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409 | 423 | VOP_CTRL_SET(vop, dsp_data_swap, 0); |
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410 | 424 | |
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.. | .. |
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888 | 902 | return 0; |
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889 | 903 | } |
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890 | 904 | |
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| 905 | +static int rockchip_vop_mode_fixup(struct display_state *state) |
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| 906 | +{ |
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| 907 | + struct connector_state *conn_state = &state->conn_state; |
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| 908 | + struct drm_display_mode *mode = &conn_state->mode; |
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| 909 | + |
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| 910 | + drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); |
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| 911 | + |
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| 912 | + return 0; |
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| 913 | +} |
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| 914 | + |
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891 | 915 | const struct rockchip_crtc_funcs rockchip_vop_funcs = { |
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892 | 916 | .preinit = rockchip_vop_preinit, |
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893 | 917 | .init = rockchip_vop_init, |
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.. | .. |
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899 | 923 | .send_mcu_cmd = rockchip_vop_send_mcu_cmd, |
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900 | 924 | .mode_valid = rockchip_vop_mode_valid, |
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901 | 925 | .plane_check = rockchip_vop_plane_check, |
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| 926 | + .mode_fixup = rockchip_vop_mode_fixup, |
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902 | 927 | }; |
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