rk3568 rt uboot init

hc

2023-11-06 9df731a176aab8e03b984b681b1bea01ccff6644

 u-boot/drivers/video/drm/rockchip_dw_hdmi.c
..
..
@@ -7,6 +7,7 @@
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7
 #include <common.h>
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8
 #include <boot_rkimg.h>
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 #include <asm/io.h>
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+#include <asm/gpio.h>
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 #include <dm/of_access.h>
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 #include <dm/device.h>
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 #include <linux/dw_hdmi.h>
..
..
@@ -35,6 +36,19 @@
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 #define RK3328_GRF_SOC_CON2              0x0408
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 #define RK3328_GRF_SOC_CON3              0x040c
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 #define RK3328_GRF_SOC_CON4              0x0410
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+
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+#define RK3528_GPIO0A_IOMUX_SEL_H	0x4
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+#define RK3528_GPIO0A_PULL 		0x200
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+#define RK3528_DDC_PULL			(0xf00 << 16)
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+#define RK3528_VO_GRF_HDMI_MASK		0x60014
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+#define RK3528_HDMI_SNKDET_SEL		((BIT(6) << 16) | BIT(6))
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+#define RK3528_HDMI_SNKDET		BIT(21)
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+#define RK3528_HDMI_CECIN_MSK		((BIT(2) << 16) | BIT(2))
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+#define RK3528_HDMI_SDAIN_MSK		((BIT(1) << 16) | BIT(1))
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+#define RK3528_HDMI_SCLIN_MSK		((BIT(0) << 16) | BIT(0))
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+
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+#define RK3528_GPIO_SWPORT_DR_L		0x0000
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+#define RK3528_GPIO0_A2_DR		((BIT(2) << 16) | BIT(2))
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52
 
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 #define RK3568_GRF_VO_CON1               0x0364
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 #define RK3568_HDMI_SDAIN_MSK            ((1 << 15) | (1 << (15 + 16)))
..
..
@@ -177,7 +191,7 @@
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 	}
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 };
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193
 
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-static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
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+static struct dw_hdmi_phy_config rockchip_phy_config[] = {
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 	/*pixelclk   symbol   term   vlev*/
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 	{ 74250000,  0x8009, 0x0004, 0x0272},
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 	{ 165000000, 0x802b, 0x0004, 0x0209},
..
..
@@ -334,19 +348,23 @@
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 			  enum dw_hdmi_devtype dev_type,
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349
 			  bool output_bus_format_rgb)
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 {
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-	int ret, i, screen_size;
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-	struct base_disp_info base_parameter;
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 	struct base2_disp_info *base2_parameter = conn_state->disp_info;
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 	const struct base_overscan *scan;
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 	struct base_screen_info *screen_info = NULL;
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 	struct base2_screen_info *screen_info2 = NULL;
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 	int max_scan = 100;
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 	int min_scan = 51;
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+#ifdef CONFIG_SPL_BUILD
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+	int i, screen_size;
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+#else
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+	int ret, i, screen_size;
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 	int offset = 0;
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 	bool found = false;
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 	struct blk_desc *dev_desc;
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 	disk_partition_t part_info;
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 	char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN);
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+	struct base_disp_info base_parameter;
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+#endif
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368
 
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 	overscan->left_margin = max_scan;
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 	overscan->right_margin = max_scan;
..
..
@@ -358,6 +376,27 @@
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 	else
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 		*bus_format = MEDIA_BUS_FMT_YUV8_1X24;
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378
 
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+#ifdef CONFIG_SPL_BUILD
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+	scan = &base2_parameter->overscan_info;
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+	screen_size = sizeof(base2_parameter->screen_info) /
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+		sizeof(base2_parameter->screen_info[0]);
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+
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+	for (i = 0; i < screen_size; i++) {
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+		if (base2_parameter->screen_info[i].type ==
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+		    DRM_MODE_CONNECTOR_HDMIA) {
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+			screen_info2 =
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+				&base2_parameter->screen_info[i];
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+			break;
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+		}
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+	}
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+	screen_info = malloc(sizeof(*screen_info));
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+
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+	screen_info->type = screen_info2->type;
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+	screen_info->mode = screen_info2->resolution;
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+	screen_info->format = screen_info2->format;
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+	screen_info->depth = screen_info2->depthc;
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+	screen_info->feature = screen_info2->feature;
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+#else
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 	if (!base2_parameter) {
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 		dev_desc = rockchip_get_bootdev();
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 		if (!dev_desc) {
..
..
@@ -422,6 +461,7 @@
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 		screen_info->depth = screen_info2->depthc;
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 		screen_info->feature = screen_info2->feature;
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 	}
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+#endif
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465
 
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 	if (scan->leftscale < min_scan && scan->leftscale > 0)
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467
 		overscan->left_margin = min_scan;
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..
@@ -443,7 +483,9 @@
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 	else if (scan->bottomscale < max_scan && scan->bottomscale > 0)
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 		overscan->bottom_margin = scan->bottomscale;
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485
 
486
+#ifndef CONFIG_SPL_BUILD
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 null_basep:
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+#endif
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489
 
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 	if (screen_info)
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491
 		printf("base_parameter.mode:%dx%d\n",
..
..
@@ -463,8 +505,15 @@
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 		writel(RK3328_IO_3V_DOMAIN, grf + RK3328_GRF_SOC_CON4);
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 }
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507
 
466
-void dw_hdmi_set_iomux(void *grf, int dev_type)
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+void dw_hdmi_set_iomux(void *grf, void *gpio_base, struct gpio_desc *hpd_gpiod,
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+		       int dev_type)
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 {
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+	u32 val = 0;
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+	int i = 400;
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+#ifdef CONFIG_SPL_BUILD
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+	void *gpio0_ioc = (void *)RK3528_GPIO0_IOC_BASE;
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+#endif
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+
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 	switch (dev_type) {
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 	case RK3328_HDMI:
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 		writel(RK3328_IO_DDC_IN_MSK, grf + RK3328_GRF_SOC_CON2);
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@@ -473,6 +522,49 @@
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 	case RK3228_HDMI:
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 		writel(RK3228_IO_3V_DOMAIN, grf + RK3228_GRF_SOC_CON6);
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 		writel(RK3228_IO_DDC_IN_MSK, grf + RK3228_GRF_SOC_CON2);
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+		break;
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+	case RK3528_HDMI:
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+		writel(RK3528_HDMI_SDAIN_MSK | RK3528_HDMI_SCLIN_MSK |
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+		       RK3528_HDMI_SNKDET_SEL,
529
+		       grf + RK3528_VO_GRF_HDMI_MASK);
530
+
531
+#ifdef CONFIG_SPL_BUILD
532
+		val = (0x11 << 16) | 0x11;
533
+		writel(val, gpio0_ioc + RK3528_GPIO0A_IOMUX_SEL_H);
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+
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+		writel(RK3528_DDC_PULL, gpio0_ioc + RK3528_GPIO0A_PULL);
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+
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+		/* gpio0_a2's input enable is controlled by gpio output data bit */
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+		writel(RK3528_GPIO0_A2_DR, gpio_base + RK3528_GPIO_SWPORT_DR_L);
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+
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+		while (i--) {
541
+			val = readl(gpio_base + 0x70) & BIT(2);
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+			if (val)
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+				break;
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+			mdelay(5);
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+		}
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+#else
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+		writel(val, grf + RK3528_VO_GRF_HDMI_MASK);
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+
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+		/* gpio0_a2's input enable is controlled by gpio output data bit */
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+		writel(RK3528_GPIO0_A2_DR, gpio_base + RK3528_GPIO_SWPORT_DR_L);
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+
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+		if (dm_gpio_is_valid(hpd_gpiod)) {
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+			while (i--) {
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+				val = dm_gpio_get_value(hpd_gpiod);
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+				if (val)
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+					break;
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+				mdelay(5);
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+			}
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+		}
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+#endif
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+
562
+		if (val)
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+			val = RK3528_HDMI_SNKDET | BIT(5);
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+		else
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+			val = RK3528_HDMI_SNKDET;
566
+		writel(val, grf + RK3528_VO_GRF_HDMI_MASK);
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+
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 		break;
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569
 	case RK3568_HDMI:
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 		writel(RK3568_HDMI_SDAIN_MSK | RK3568_HDMI_SCLIN_MSK,
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@@ -544,6 +636,14 @@
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 	.dev_type   = RK3399_HDMI,
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637
 };
546
638
 
639
+const struct dw_hdmi_plat_data rk3528_hdmi_drv_data = {
640
+	.vop_sel_bit = 0,
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+	.grf_vop_sel_reg = 0,
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+	.phy_ops    = &inno_dw_hdmi_phy_ops,
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+	.phy_name   = "inno_dw_hdmi_phy2",
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+	.dev_type   = RK3528_HDMI,
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+};
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+
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 const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
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 	.vop_sel_bit = 0,
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649
 	.grf_vop_sel_reg = 0,
..
..
@@ -554,6 +654,19 @@
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 	.dev_type   = RK3568_HDMI,
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 };
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656
 
657
+#ifdef CONFIG_SPL_BUILD
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+int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state)
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+{
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+	conn_state->connector = malloc(sizeof(struct rockchip_connector));
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+
662
+	memset(conn_state->connector, 0, sizeof(*conn_state->connector));
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+	rockchip_connector_bind(conn_state->connector, NULL, 0, &rockchip_dw_hdmi_funcs,
664
+				(void *)&rk3528_hdmi_drv_data,
665
+				DRM_MODE_CONNECTOR_HDMIA);
666
+
667
+	return 0;
668
+}
669
+#else
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 static int rockchip_dw_hdmi_probe(struct udevice *dev)
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671
 {
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672
 	int id;
..
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@@ -568,9 +681,13 @@
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681
 
569
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 	return 0;
570
683
 }
684
+#endif
571
685
 
572
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 static const struct udevice_id rockchip_dw_hdmi_ids[] = {
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 	{
688
+	 .compatible = "rockchip,rk3528-dw-hdmi",
689
+	 .data = (ulong)&rk3528_hdmi_drv_data,
690
+	}, {
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 	 .compatible = "rockchip,rk3568-dw-hdmi",
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 	 .data = (ulong)&rk3568_hdmi_drv_data,
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 	}, {
..
..
@@ -598,6 +715,8 @@
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 	.name = "rockchip_dw_hdmi",
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 	.id = UCLASS_DISPLAY,
600
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 	.of_match = rockchip_dw_hdmi_ids,
718
+#ifndef CONFIG_SPL_BUILD
601
719
 	.probe	= rockchip_dw_hdmi_probe,
720
+#endif
602
721
 	.priv_auto_alloc_size = sizeof(struct rockchip_connector),
603
722
 };