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2023-11-06 9df731a176aab8e03b984b681b1bea01ccff6644 
 u-boot/drivers/mtd/spi/spi-nor-ids.c
....@@ -85,6 +85,9 @@
8585 	{ INFO("en25qh64",  0x1c7017, 0, 64 * 1024,  128, SECT_4K) },
8686 	{ INFO("en25qh128",  0x1c7018, 0, 64 * 1024,  256, SECT_4K) },
8787 	{ INFO("en25s64",    0x1c3817, 0, 64 * 1024,  128, SECT_4K) },
88
+	{ INFO("en25qh256a", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
89
+	{ INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
90
+	{ INFO("en25qx128a", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
8891 #endif
8992 #ifdef CONFIG_SPI_FLASH_GIGADEVICE	/* GIGADEVICE */
9093 	/* GigaDevice */
....@@ -118,28 +121,18 @@
118121 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
119122 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
120123 	},
121
-	{
122
-		INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
123
-			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
124
-			SPI_NOR_HAS_TB)
125
-	},
126
-	{	INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
127
-			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
128
-			SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
129
-			SPI_NOR_HAS_TB)
130
-	},
131124 	{	INFO("gd25q512", 0xc84020, 0, 64 * 1024, 1024,
132125 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
133126 			SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
134127 			SPI_NOR_HAS_TB)
135128 	},
136129 	{
137
-		INFO("gd25lq255", 0xc86019, 0, 64 * 1024, 512,
130
+		INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024,
138131 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
139132 			SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
140133 	},
141134 	{
142
-		INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024,
135
+		INFO("gd55lb01ge", 0xc8671b, 0, 64 * 1024, 2048,
143136 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
144137 			SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
145138 	},
....@@ -148,17 +141,112 @@
148141 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
149142 			SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
150143 	},
144
+	{
145
+		INFO("gd55b01ge", 0xc8471b, 0, 64 * 1024, 2048,
146
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
147
+			SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
148
+	},
149
+	/* adding these 3V QSPI flash parts */
150
+	{INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512,	SECT_4K |
151
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)	},
152
+	{INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024,	SECT_4K |
153
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
154
+	{INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048,	SECT_4K |
155
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
156
+	{INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096,	SECT_4K |
157
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
158
+	{INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128,	SECT_4K |
159
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
160
+	{INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256,	SECT_4K	|
161
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
162
+	{INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512,	SECT_4K |
163
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
164
+	{INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024,	SECT_4K |
165
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
166
+	{INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024,	SECT_4K |
167
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
168
+	{INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048,	SECT_4K |
169
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
170
+	{INFO("gd55t02g",	0xc8461C, 0, 64 * 1024, 4096,	SECT_4K |
171
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
172
+	/* adding these 3V OSPI flash parts */
173
+	{INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024,	SECT_4K |
174
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
175
+	{INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048,	SECT_4K |
176
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
177
+	{INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096,	SECT_4K |
178
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
179
+	{
180
+		INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
181
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
182
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
183
+	},
184
+	{
185
+		INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512,
186
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
187
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
188
+	},
189
+	/* adding these 1.8V QSPI flash parts */
190
+	{INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512,	SECT_4K |
191
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
192
+	{INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024,	SECT_4K |
193
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
194
+	{INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048,	SECT_4K |
195
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
196
+	{INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096,	SECT_4K |
197
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
198
+	{INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16,	SECT_4K |
199
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
200
+	{INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32,	SECT_4K |
201
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
202
+	{INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64,	SECT_4K |
203
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)	},
204
+	{INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128,	SECT_4K |
205
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)	},
206
+	{INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256,	SECT_4K |
207
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)	},
208
+	{INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512,	SECT_4K |
209
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
210
+	{INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024,	SECT_4K |
211
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
212
+	{INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512,	SECT_4K |
213
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
214
+	{INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024,	SECT_4K |
215
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
216
+	{INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048,	SECT_4K |
217
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
218
+	{INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096,	SECT_4K |
219
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
220
+	{
221
+		INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
222
+		     SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
223
+	},
224
+	/* adding these 1.8V OSPI flash parts */
225
+	{INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024,	SECT_4K |
226
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
227
+	{INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048,	SECT_4K |
228
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
229
+	{INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096,	SECT_4K |
230
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
151231 #endif
152232 #ifdef CONFIG_SPI_FLASH_ISSI		/* ISSI */
153233 	/* ISSI */
154234 	{ INFO("is25lq040b", 0x9d4013, 0, 64 * 1024,   8,
155235 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
236
+	{ INFO("is25lp008", 0x9d6014, 0, 64 * 1024,  16, SPI_NOR_QUAD_READ) },
237
+	{ INFO("is25lp016", 0x9d6015, 0, 64 * 1024,  32, SPI_NOR_QUAD_READ) },
156238 	{ INFO("is25lp032",	0x9d6016, 0, 64 * 1024,  64, 0) },
157239 	{ INFO("is25lp064",	0x9d6017, 0, 64 * 1024, 128, 0) },
158240 	{ INFO("is25lp128",  0x9d6018, 0, 64 * 1024, 256,
159241 			SECT_4K | SPI_NOR_DUAL_READ) },
160242 	{ INFO("is25lp256",  0x9d6019, 0, 64 * 1024, 512,
161243 			SECT_4K | SPI_NOR_DUAL_READ) },
244
+	{ INFO("is25lp512",  0x9d601a, 0, 64 * 1024, 1024,
245
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
246
+	{ INFO("is25lp01g",  0x9d601b, 0, 64 * 1024, 2048,
247
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
248
+	{ INFO("is25wp008", 0x9d7014, 0, 64 * 1024,  16, SPI_NOR_QUAD_READ) },
249
+	{ INFO("is25wp016", 0x9d7015, 0, 64 * 1024,  32, SPI_NOR_QUAD_READ) },
162250 	{ INFO("is25wp032",  0x9d7016, 0, 64 * 1024,  64,
163251 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
164252 	{ INFO("is25wp064",  0x9d7017, 0, 64 * 1024, 128,
....@@ -168,6 +256,12 @@
168256 	{ INFO("is25wp256",  0x9d7019, 0, 64 * 1024, 512,
169257 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
170258 			SPI_NOR_4B_OPCODES) },
259
+	{ INFO("is25wp512",  0x9d701a, 0, 64 * 1024, 1024,
260
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
261
+	{ INFO("is25wp01g",  0x9d701b, 0, 64 * 1024, 2048,
262
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
263
+	{ INFO("is25wx256",  0x9d5b19, 0, 128 * 1024, 256,
264
+			SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
171265 #endif
172266 #ifdef CONFIG_SPI_FLASH_MACRONIX	/* MACRONIX */
173267 	/* Macronix */
....@@ -183,17 +277,41 @@
183277 	{ INFO("mx25u6435f",  0xc22537, 0, 64 * 1024, 128, SECT_4K) },
184278 	{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
185279 	{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
280
+	{ INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
281
+	       SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
186282 	{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
187283 	{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
188284 	{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
285
+	{ INFO("mx25v8035f",  0xc22314, 0, 64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
286
+	{ INFO("mx25r1635f",  0xc22815, 0, 64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
189287 	{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
190288 	{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
191289 	{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
290
+	{ INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
291
+	{ INFO("mx66u1g45g",  0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
192292 	{ INFO("mx66u2g45g",  0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
193293 	{ INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
294
+	{ INFO("mx66l2g45g",  0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
194295 	{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
195296 	{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
196
-	{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
297
+	{ INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
298
+	{ INFO("mx66lm1g45g",    0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
299
+	{ INFO("mx25lm51245g",   0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
300
+	{ INFO("mx25lw51245g",   0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
301
+	{ INFO("mx25lm25645g",   0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
302
+	{ INFO("mx66uw2g345g",   0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
303
+	{ INFO("mx66um1g45g",    0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
304
+	{ INFO("mx66uw1g45g",    0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
305
+	{ INFO("mx25uw51245g",   0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
306
+	{ INFO("mx25uw51345g",   0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
307
+	{ INFO("mx25um25645g",   0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
308
+	{ INFO("mx25uw25645g",   0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
309
+	{ INFO("mx25um25345g",   0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
310
+	{ INFO("mx25uw25345g",   0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
311
+	{ INFO("mx25uw12845g",   0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
312
+	{ INFO("mx25uw12345g",   0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
313
+	{ INFO("mx25uw6445g",    0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
314
+	{ INFO("mx25uw6345g",    0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
197315 #endif
198316 
199317 #ifdef CONFIG_SPI_FLASH_STMICRO		/* STMICRO */
....@@ -210,7 +328,7 @@
210328 	{ INFO6("mt25qu256a",  0x20bb19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
211329 	{ INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
212330 	{ INFO6("mt25qu512a",  0x20bb20, 0x104400, 64 * 1024, 1024,
213
-		 SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
331
+		 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
214332 		 USE_FSR) },
215333 	{ INFO("n25q512a",    0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
216334 	{ INFO6("mt25ql512a",  0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
....@@ -219,7 +337,12 @@
219337 	{ INFO("n25q00a",     0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
220338 	{ INFO("mt25ql01g",   0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
221339 	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
222
-	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
340
+	{ INFO("mt25ql02g",   0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
341
+#ifdef CONFIG_SPI_FLASH_MT35XU
342
+	{ INFO("mt35xl512aba", 0x2c5a1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
343
+	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
344
+#endif /* CONFIG_SPI_FLASH_MT35XU */
345
+	{ INFO6("mt35xu01g",  0x2c5b1b, 0x104100, 128 * 1024,  1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
223346 	{ INFO("mt35xu02g",  0x2c5b1c, 0, 128 * 1024,  2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
224347 #endif
225348 #ifdef CONFIG_SPI_FLASH_SPANSION	/* SPANSION */
....@@ -235,6 +358,7 @@
235358 	{ INFO("s25fl512s_256k",  0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
236359 	{ INFO("s25fl512s_64k",  0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
237360 	{ INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
361
+	{ INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
238362 	{ INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024,  64, 0) },
239363 	{ INFO("s25sl12801", 0x012018, 0x0301,  64 * 1024, 256, 0) },
240364 	{ INFO6("s25fl128s",  0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
....@@ -347,6 +471,31 @@
347471 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
348472 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
349473 	},
474
+	{
475
+		INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512,
476
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
477
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
478
+	},
479
+	{
480
+		INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024,
481
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
482
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
483
+	},
484
+	{
485
+		INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024,
486
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
487
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
488
+	},
489
+	{
490
+		INFO("w25q512jvq", 0xef4020, 0, 64 * 1024, 1024,
491
+		     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
492
+		     SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
493
+	},
494
+	{
495
+		INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
496
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
497
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
498
+	},
350499 	{ INFO("w25q80", 0xef5014, 0, 64 * 1024,  16, SECT_4K) },
351500 	{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
352501 	{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
....@@ -358,6 +507,7 @@
358507 	{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
359508 	{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
360509 	{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
510
+	{ INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
361511 #endif
362512 #ifdef CONFIG_SPI_FLASH_XMC
363513 	/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
....@@ -376,17 +526,23 @@
376526 	/* XTX Technology (Shenzhen) Limited */
377527 	{ INFO("xt25f64f", 0x0b4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
378528 	{ INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
529
+	{ INFO("xt25f256b", 0x0b4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
530
+	{ INFO("xt25q64d", 0x0b6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
531
+	{ INFO("xt25q128d", 0x0b6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
379532 #endif
380533 #ifdef CONFIG_SPI_FLASH_PUYA
381534 	/* PUYA Semiconductor (Shanghai) Co., Ltd. */
382535 	{ INFO("P25Q64H", 0x856017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
383536 	{ INFO("P25Q128H", 0x856018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
537
+	{ INFO("PY25Q64HA", 0x852017, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
384538 	{ INFO("PY25Q128HA", 0x852018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
539
+	{ INFO("PY25Q256HB", 0x852019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
385540 #endif
386541 #ifdef CONFIG_SPI_FLASH_FMSH
387542 	/* FUDAN MICRO (Shanghai) Co., Ltd. */
388543 	{ INFO("FM25Q128A", 0xA14018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
389544 	{ INFO("FM25Q64", 0xA14017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
545
+	{ INFO("FM25Q256I3", 0xA14019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
390546 #endif
391547 #ifdef CONFIG_SPI_FLASH_DOSILICON
392548 	/* Dosilicon Co., Ltd. */