rk3568 rt uboot init

hc

2023-11-06 9df731a176aab8e03b984b681b1bea01ccff6644

 u-boot/drivers/clk/rockchip/clk_rk3588.c
..
..
@@ -332,12 +332,18 @@
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 	switch (clk_id) {
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 	case ACLK_TOP_ROOT:
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-		src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
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+		if (!(priv->cpll_hz % rate)) {
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+			src_clk = ACLK_TOP_ROOT_SRC_SEL_CPLL;
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+			src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
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+		} else {
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+			src_clk = ACLK_TOP_ROOT_SRC_SEL_GPLL;
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+			src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
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+		}
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 		assert(src_clk_div - 1 <= 31);
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 		rk_clrsetreg(&cru->clksel_con[8],
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 			     ACLK_TOP_ROOT_DIV_MASK |
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 			     ACLK_TOP_ROOT_SRC_SEL_MASK,
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-			     (ACLK_TOP_ROOT_SRC_SEL_GPLL <<
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+			     (src_clk <<
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 			      ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
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 			     (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
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 		break;
..
..
@@ -1148,13 +1154,23 @@
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 	}
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 	if (sel == DCLK_VOP_SRC_SEL_V0PLL) {
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-		div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
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-		rk_clrsetreg(&cru->clksel_con[conid],
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-			     mask,
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-			     DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
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-			     ((div - 1) << div_shift));
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-		rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
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-				      priv->cru, V0PLL, div * rate);
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+		pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
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+						 priv->cru, V0PLL);
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+		if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
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+			div = DIV_ROUND_UP(pll_rate, rate);
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+			rk_clrsetreg(&cru->clksel_con[conid],
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+				     mask,
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+				     DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
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+				     ((div - 1) << div_shift));
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+		} else {
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+			div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
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+			rk_clrsetreg(&cru->clksel_con[conid],
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+				     mask,
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+				     DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
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+				     ((div - 1) << div_shift));
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+			rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
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+					      priv->cru, V0PLL, div * rate);
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+		}
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 	} else {
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 		for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) {
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 			switch (i) {