u-boot/drivers/clk/rockchip/clk_rk3399.c
.. .. @@ -773,6 +773,10 @@ 773 773 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 774 774 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | 775 775 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 776 + rk_clrsetreg(&cru->clksel_con[42],777 + ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,778 + ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT |779 + (div - 1) << ACLK_VOP_DIV_CON_SHIFT);776 780 777 781 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) { 778 782 if (pll_para_config(hz, &cpll_config))