forked from ~ljy/RK356X_SDK_RELEASE

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hc
2023-11-06 9df731a176aab8e03b984b681b1bea01ccff6644 
 u-boot/drivers/clk/rockchip/clk_pll.c
....@@ -267,9 +267,11 @@
267267 	 * When power on or changing PLL setting,
268268 	 * we must force PLL into slow mode to ensure output stable clock.
269269 	 */
270
-	rk_clrsetreg(base + pll->mode_offset,
271
-		     pll->mode_mask << pll->mode_shift,
272
-		     RKCLK_PLL_MODE_SLOW << pll->mode_shift);
270
+	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
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+		rk_clrsetreg(base + pll->mode_offset,
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+			     pll->mode_mask << pll->mode_shift,
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+			     RKCLK_PLL_MODE_SLOW << pll->mode_shift);
274
+	}
273275 
274276 	/* Power down */
275277 	rk_setreg(base + pll->con_offset + 0x4,
....@@ -308,8 +310,11 @@
308310 	if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
309311 		printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id);
310312 
311
-	rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
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-		     RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
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+	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
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+		rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
315
+			     RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
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+	}
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+
313318 	debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
314319 	      pll, readl(base + pll->con_offset),
315320 	      readl(base + pll->con_offset + 0x4),
....@@ -325,12 +330,18 @@
325330 	u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
326331 	u32 con = 0, shift, mask;
327332 	ulong rate;
333
+	int mode;
328334 
329335 	con = readl(base + pll->mode_offset);
330336 	shift = pll->mode_shift;
331337 	mask = pll->mode_mask << shift;
332338 
333
-	switch ((con & mask) >> shift) {
339
+	if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
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+		mode = (con & mask) >> shift;
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+	else
342
+		mode = RKCLK_PLL_MODE_NORMAL;
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+
344
+	switch (mode) {
334345 	case RKCLK_PLL_MODE_SLOW:
335346 		return OSC_HZ;
336347 	case RKCLK_PLL_MODE_NORMAL: