rk3568 rt uboot init

hc

2023-11-06 9df731a176aab8e03b984b681b1bea01ccff6644

 u-boot/arch/arm/mach-rockchip/rv1126/rv1126.c
..
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@@ -63,6 +63,9 @@
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 #define PMU_PWR_DWN_ST		(0x108)
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 #define PMU_PWR_GATE_SFTCON	(0x110)
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+#define PMU_BUS_IDLE_NPU	BIT(18)
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+#define PMU_BUS_IDLE_VEPU	BIT(9)
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+
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 #define CRU_BASE		0xFF490000
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 #define CRU_CLKSEL_CON02	0x108
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 #define CRU_CLKSEL_CON03	0x10c
..
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@@ -548,6 +551,7 @@
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 	 * CONFIG_DM_RAMDISK: for ramboot that without SPL.
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 	 */
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 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DM_RAMDISK)
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+	u32 pd_st, idle_st;
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 	int delay;
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 	/*
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@@ -624,11 +628,7 @@
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 	do {
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 		udelay(1);
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 		delay--;
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-		if (delay == 0) {
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-			printf("Fail to set domain.");
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-			hang();
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-		}
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-	} while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST));
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+	} while (delay && readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST));
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 	/* release all idle request */
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 	writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(0));
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@@ -639,22 +639,30 @@
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 	do {
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 		udelay(1);
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 		delay--;
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-		if (delay == 0) {
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-			printf("Fail to get ack on domain.\n");
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-			hang();
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-		}
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-	} while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK));
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+	} while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK));
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643
 
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 	delay = 1000;
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 	/* wait idle status */
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 	do {
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 		udelay(1);
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 		delay--;
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-		if (delay == 0) {
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-			printf("Fail to set idle on domain.\n");
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-			hang();
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-		}
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-	} while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST));
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+	} while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST));
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+
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+	pd_st = readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST);
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+	idle_st = readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST);
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+
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+	if (pd_st || idle_st) {
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+		printf("PMU_PWR_DOWN_ST: 0x%08x\n", pd_st);
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+		printf("PMU_BUS_IDLE_ST: 0x%08x\n", idle_st);
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+
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+		if (idle_st & PMU_BUS_IDLE_NPU)
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+			printf("Failed to enable PD_NPU, please check VDD_NPU is supplied\n");
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+
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+		if (idle_st & PMU_BUS_IDLE_VEPU)
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+			printf("Failed to enable PD_VEPU, please check VDD_VEPU is supplied\n");
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+
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+		hang();
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+	}
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 	writel(0x303, USB_HOST_PRIORITY_REG);
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 	writel(0x303, USB_OTG_PRIORITY_REG);