rk3568 rt uboot init

hc

2023-11-06 9df731a176aab8e03b984b681b1bea01ccff6644

 u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
..
..
@@ -19,20 +19,31 @@
19
19
 #define FIREWALL_DDR_BASE		0xfe030000
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 #define FW_DDR_MST5_REG			0x54
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 #define FW_DDR_MST13_REG		0x74
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+#define FW_DDR_MST19_REG		0x8c
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 #define FW_DDR_MST21_REG		0x94
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 #define FW_DDR_MST26_REG		0xa8
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 #define FW_DDR_MST27_REG		0xac
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 #define FIREWALL_SYSMEM_BASE		0xfe038000
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 #define FW_SYSM_MST5_REG		0x54
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 #define FW_SYSM_MST13_REG		0x74
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+#define FW_SYSM_MST19_REG		0x8c
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 #define FW_SYSM_MST21_REG		0x94
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 #define FW_SYSM_MST26_REG		0xa8
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 #define FW_SYSM_MST27_REG		0xac
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+#define PMU1_SGRF_BASE			0xfd582000
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+#define PMU1_SGRF_SOC_CON0		0x0
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+#define PMU1_SGRF_SOC_CON6		0x18
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+#define PMU1_SGRF_SOC_CON7		0x1c
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+#define PMU1_SGRF_SOC_CON8		0x20
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+#define PMU1_SGRF_SOC_CON9		0x24
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+#define PMU1_SGRF_SOC_CON10		0x28
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+#define PMU1_SGRF_SOC_CON13		0x34
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 #define SYS_GRF_BASE			0xfd58c000
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 #define SYS_GRF_SOC_CON6		0x0318
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 #define USBGRF_BASE			0xfd5ac000
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 #define USB_GRF_USB3OTG0_CON1		0x001c
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 #define BUS_SGRF_BASE			0xfd586000
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+#define BUS_SGRF_SOC_CON2		0x08
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 #define BUS_SGRF_FIREWALL_CON18		0x288
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 #define PMU_BASE			0xfd8d0000
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 #define PMU_PWR_GATE_SFTCON1		0x8150
..
..
@@ -66,14 +77,21 @@
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 #define EMMC_IOC_GPIO2D_DS_H		0x5c
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 #define CRU_BASE			0xfd7c0000
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+#define CRU_GPLL_CON1			0x01c4
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 #define CRU_SOFTRST_CON77		0x0b34
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+#define CRU_GLB_RST_CON			0x0c10
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83
 
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 #define PMU1CRU_BASE			0xfd7f0000
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+#define PMU1CRU_SOFTRST_CON00		0x0a00
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 #define PMU1CRU_SOFTRST_CON03		0x0a0c
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 #define PMU1CRU_SOFTRST_CON04		0x0a10
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88
 
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 #define HDMIRX_NODE_FDT_PATH		"/hdmirx-controller@fdee0000"
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 #define RK3588_PHY_CONFIG		0xfdee00c0
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+
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+#define VOP_M0_PRIORITY_REG		0xfdf82008
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+#define VOP_M1_PRIORITY_REG		0xfdf82208
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+#define QOS_PRIORITY_LEVEL(h, l)	((((h) & 7) << 8) | ((l) & 7))
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95
 
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 #ifdef CONFIG_ARM64
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 #include <asm/armv8/mmu.h>
..
..
@@ -865,8 +883,15 @@
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 	secure_reg &= 0xffff0000;
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 	writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
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885
 
868
-	/* Select clk_tx source as default for i2s2/i2s3 */
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-	writel(0x03400340, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
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+	/*
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+	 * Select clk_tx source as default for i2s2/i2s3
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+	 * Set I2Sx_MCLK as input default
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+	 *
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+	 * It's safe to set mclk as input default to avoid high freq glitch
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+	 * which may make devices work unexpected. And then enabled by
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+	 * kernel stage or any state where user use it.
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+	 */
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+	writel(0x03c703c7, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
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895
 
871
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 	if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x2222) {
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 		/* Set the fspi m0 io ds level to 55ohm */
..
..
@@ -922,7 +947,14 @@
922
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 	writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
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 	writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
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 #endif
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-
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+	/*
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+	 * set VOP M0 and VOP M1 to priority 0x303,then
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+	 * Peri > VOP/MCU > ISP/VICAP > other
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+	 * Note: VOP priority can only be modified during the u-boot stage,
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+	 * 	 as VOP default power down, and power up after trust.
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+	 */
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+	writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M0_PRIORITY_REG);
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+	writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M1_PRIORITY_REG);
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 #endif
927
959
 
928
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 	/* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */
..
..
@@ -1245,31 +1277,36 @@
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 #ifdef CONFIG_SPL_BUILD
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 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
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 {
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-	/* gpll enable */
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-	writel(0x00f00042, 0xfd7c01c4);
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+	u32 val;
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+
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+	/* pmu m0 configuration: */
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+	/* set gpll */
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+	writel(0x00f00042, CRU_BASE + CRU_GPLL_CON1);
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+	/* set pmu mcu to access ddr memory */
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+	val = readl(FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
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+	writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
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+	/* set pmu mcu to access system memory */
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+	val = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
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+	writel(val & 0x000000ff, FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
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+	/* set pmu mcu to secure */
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+	writel(0x00080000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON0);
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 	/* set start addr, pmu_mcu_code_addr_start */
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-	writel(0xFFFF0000 | (entry_point >> 16), 0xFD582024);
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-	/* pmu_mcu_sram_addr_start */
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-	writel(0xFFFF2000, 0xFD582028);
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-	/* pmu_mcu_tcm_addr_start */
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-	writel(0xFFFF2000, 0xFD582034);
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-	/* set mcu secure */
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-	writel(0x00080000, 0xFD582000);
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+	writel(0xFFFF0000 | (entry_point >> 16), PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON9);
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+	/* set pmu_mcu_sram_addr_start */
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+	writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10);
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+	/* set pmu_mcu_tcm_addr_start */
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+	writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON13);
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 	/* set cache cache_peripheral_addr */
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-	writel(0xffff0000, 0xFD582018);
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-	writel(0xffffee00, 0xFD58201c);
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-	writel(0x00ff00ff, 0xFD582020);  /* 0xf0000000 ~ 0xfee00000 */
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-	/* mcupmu access DDR secure control, each bit for a region. */
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-	writel(0x0000ffff, 0xFE03008C);
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-	/* mcupmu access DDR secure control, each bit for a region. */
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-	writel(0x000000ff, 0xFE03808C);
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-	/* PMU WDT reset system enable */
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-	writel(0x02000200, 0xFD586008);
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-	/* WDT trigger global reset. */
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-	writel(0x08400840, 0xFD7C0C10);
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-	/* Spl helps to load the mcu image, but not need to release
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-	 * mcu for rk3588.
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-	 */
1300
+	/* 0xf0000000 ~ 0xfee00000 */
1301
+	writel(0xffff0000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON6);
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+	writel(0xffffee00, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON7);
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+	writel(0x00ff00ff, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON8);
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+	/* enable PMU WDT reset system */
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+	writel(0x02000200, BUS_SGRF_BASE + BUS_SGRF_SOC_CON2);
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+	/* select WDT trigger global reset. */
1307
+	writel(0x08400840, CRU_BASE + CRU_GLB_RST_CON);
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+	/* release pmu mcu */
1309
+	/* writel(0x20000000, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON00); */
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1310
 
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 	return 0;
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 }