modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/tools/objtool/arch/x86/decode.c
..
..
@@ -1,18 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
1
2
 /*
2
3
  * Copyright (C) 2015 Josh Poimboeuf <jpoimboe@redhat.com>
3
- *
4
- * This program is free software; you can redistribute it and/or
5
- * modify it under the terms of the GNU General Public License
6
- * as published by the Free Software Foundation; either version 2
7
- * of the License, or (at your option) any later version.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
13
- *
14
- * You should have received a copy of the GNU General Public License
15
- * along with this program; if not, see <http://www.gnu.org/licenses/>.
16
4
  */
17
5
 
18
6
 #include <stdio.h>
..
..
@@ -20,12 +8,15 @@
20
8
 
21
9
 #define unlikely(cond) (cond)
22
10
 #include <asm/insn.h>
23
-#include "lib/inat.c"
24
-#include "lib/insn.c"
11
+#include "../../../arch/x86/lib/inat.c"
12
+#include "../../../arch/x86/lib/insn.c"
25
13
 
14
+#include "../../check.h"
26
15
 #include "../../elf.h"
27
16
 #include "../../arch.h"
28
17
 #include "../../warn.h"
18
+#include <asm/orc_types.h>
19
+#include "arch_elf.h"
29
20
 
30
21
 static unsigned char op_to_cfi_reg[][2] = {
31
22
 	{CFI_AX, CFI_R8},
..
..
@@ -38,7 +29,7 @@
38
29
 	{CFI_DI, CFI_R15},
39
30
 };
40
31
 
41
-static int is_x86_64(struct elf *elf)
32
+static int is_x86_64(const struct elf *elf)
42
33
 {
43
34
 	switch (elf->ehdr.e_machine) {
44
35
 	case EM_X86_64:
..
..
@@ -78,16 +69,34 @@
78
69
 	}
79
70
 }
80
71
 
81
-int arch_decode_instruction(struct elf *elf, struct section *sec,
72
+unsigned long arch_dest_reloc_offset(int addend)
73
+{
74
+	return addend + 4;
75
+}
76
+
77
+unsigned long arch_jump_destination(struct instruction *insn)
78
+{
79
+	return insn->offset + insn->len + insn->immediate;
80
+}
81
+
82
+#define ADD_OP(op) \
83
+	if (!(op = calloc(1, sizeof(*op)))) \
84
+		return -1; \
85
+	else for (list_add_tail(&op->list, ops_list); op; op = NULL)
86
+
87
+int arch_decode_instruction(const struct elf *elf, const struct section *sec,
82
88
 			    unsigned long offset, unsigned int maxlen,
83
-			    unsigned int *len, unsigned char *type,
84
-			    unsigned long *immediate, struct stack_op *op)
89
+			    unsigned int *len, enum insn_type *type,
90
+			    unsigned long *immediate,
91
+			    struct list_head *ops_list)
85
92
 {
86
93
 	struct insn insn;
87
94
 	int x86_64, sign;
88
95
 	unsigned char op1, op2, rex = 0, rex_b = 0, rex_r = 0, rex_w = 0,
89
96
 		      rex_x = 0, modrm = 0, modrm_mod = 0, modrm_rm = 0,
90
97
 		      modrm_reg = 0, sib = 0;
98
+	struct stack_op *op = NULL;
99
+	struct symbol *sym;
91
100
 
92
101
 	x86_64 = is_x86_64(elf);
93
102
 	if (x86_64 == -1)
..
..
@@ -97,7 +106,7 @@
97
106
 	insn_get_length(&insn);
98
107
 
99
108
 	if (!insn_complete(&insn)) {
100
-		WARN_FUNC("can't decode instruction", sec, offset);
109
+		WARN("can't decode instruction at %s:0x%lx", sec->name, offset);
101
110
 		return -1;
102
111
 	}
103
112
 
..
..
@@ -135,40 +144,44 @@
135
144
 		if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
136
145
 
137
146
 			/* add/sub reg, %rsp */
138
-			*type = INSN_STACK;
139
-			op->src.type = OP_SRC_ADD;
140
-			op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
141
-			op->dest.type = OP_DEST_REG;
142
-			op->dest.reg = CFI_SP;
147
+			ADD_OP(op) {
148
+				op->src.type = OP_SRC_ADD;
149
+				op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
150
+				op->dest.type = OP_DEST_REG;
151
+				op->dest.reg = CFI_SP;
152
+			}
143
153
 		}
144
154
 		break;
145
155
 
146
156
 	case 0x50 ... 0x57:
147
157
 
148
158
 		/* push reg */
149
-		*type = INSN_STACK;
150
-		op->src.type = OP_SRC_REG;
151
-		op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
152
-		op->dest.type = OP_DEST_PUSH;
159
+		ADD_OP(op) {
160
+			op->src.type = OP_SRC_REG;
161
+			op->src.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
162
+			op->dest.type = OP_DEST_PUSH;
163
+		}
153
164
 
154
165
 		break;
155
166
 
156
167
 	case 0x58 ... 0x5f:
157
168
 
158
169
 		/* pop reg */
159
-		*type = INSN_STACK;
160
-		op->src.type = OP_SRC_POP;
161
-		op->dest.type = OP_DEST_REG;
162
-		op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
170
+		ADD_OP(op) {
171
+			op->src.type = OP_SRC_POP;
172
+			op->dest.type = OP_DEST_REG;
173
+			op->dest.reg = op_to_cfi_reg[op1 & 0x7][rex_b];
174
+		}
163
175
 
164
176
 		break;
165
177
 
166
178
 	case 0x68:
167
179
 	case 0x6a:
168
180
 		/* push immediate */
169
-		*type = INSN_STACK;
170
-		op->src.type = OP_SRC_CONST;
171
-		op->dest.type = OP_DEST_PUSH;
181
+		ADD_OP(op) {
182
+			op->src.type = OP_SRC_CONST;
183
+			op->dest.type = OP_DEST_PUSH;
184
+		}
172
185
 		break;
173
186
 
174
187
 	case 0x70 ... 0x7f:
..
..
@@ -182,12 +195,13 @@
182
195
 
183
196
 		if (modrm == 0xe4) {
184
197
 			/* and imm, %rsp */
185
-			*type = INSN_STACK;
186
-			op->src.type = OP_SRC_AND;
187
-			op->src.reg = CFI_SP;
188
-			op->src.offset = insn.immediate.value;
189
-			op->dest.type = OP_DEST_REG;
190
-			op->dest.reg = CFI_SP;
198
+			ADD_OP(op) {
199
+				op->src.type = OP_SRC_AND;
200
+				op->src.reg = CFI_SP;
201
+				op->src.offset = insn.immediate.value;
202
+				op->dest.type = OP_DEST_REG;
203
+				op->dest.reg = CFI_SP;
204
+			}
191
205
 			break;
192
206
 		}
193
207
 
..
..
@@ -199,34 +213,37 @@
199
213
 			break;
200
214
 
201
215
 		/* add/sub imm, %rsp */
202
-		*type = INSN_STACK;
203
-		op->src.type = OP_SRC_ADD;
204
-		op->src.reg = CFI_SP;
205
-		op->src.offset = insn.immediate.value * sign;
206
-		op->dest.type = OP_DEST_REG;
207
-		op->dest.reg = CFI_SP;
216
+		ADD_OP(op) {
217
+			op->src.type = OP_SRC_ADD;
218
+			op->src.reg = CFI_SP;
219
+			op->src.offset = insn.immediate.value * sign;
220
+			op->dest.type = OP_DEST_REG;
221
+			op->dest.reg = CFI_SP;
222
+		}
208
223
 		break;
209
224
 
210
225
 	case 0x89:
211
226
 		if (rex_w && !rex_r && modrm_mod == 3 && modrm_reg == 4) {
212
227
 
213
228
 			/* mov %rsp, reg */
214
-			*type = INSN_STACK;
215
-			op->src.type = OP_SRC_REG;
216
-			op->src.reg = CFI_SP;
217
-			op->dest.type = OP_DEST_REG;
218
-			op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
229
+			ADD_OP(op) {
230
+				op->src.type = OP_SRC_REG;
231
+				op->src.reg = CFI_SP;
232
+				op->dest.type = OP_DEST_REG;
233
+				op->dest.reg = op_to_cfi_reg[modrm_rm][rex_b];
234
+			}
219
235
 			break;
220
236
 		}
221
237
 
222
238
 		if (rex_w && !rex_b && modrm_mod == 3 && modrm_rm == 4) {
223
239
 
224
240
 			/* mov reg, %rsp */
225
-			*type = INSN_STACK;
226
-			op->src.type = OP_SRC_REG;
227
-			op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
228
-			op->dest.type = OP_DEST_REG;
229
-			op->dest.reg = CFI_SP;
241
+			ADD_OP(op) {
242
+				op->src.type = OP_SRC_REG;
243
+				op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
244
+				op->dest.type = OP_DEST_REG;
245
+				op->dest.reg = CFI_SP;
246
+			}
230
247
 			break;
231
248
 		}
232
249
 
..
..
@@ -236,22 +253,24 @@
236
253
 		    (modrm_mod == 1 || modrm_mod == 2) && modrm_rm == 5) {
237
254
 
238
255
 			/* mov reg, disp(%rbp) */
239
-			*type = INSN_STACK;
240
-			op->src.type = OP_SRC_REG;
241
-			op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
242
-			op->dest.type = OP_DEST_REG_INDIRECT;
243
-			op->dest.reg = CFI_BP;
244
-			op->dest.offset = insn.displacement.value;
256
+			ADD_OP(op) {
257
+				op->src.type = OP_SRC_REG;
258
+				op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
259
+				op->dest.type = OP_DEST_REG_INDIRECT;
260
+				op->dest.reg = CFI_BP;
261
+				op->dest.offset = insn.displacement.value;
262
+			}
245
263
 
246
264
 		} else if (rex_w && !rex_b && modrm_rm == 4 && sib == 0x24) {
247
265
 
248
266
 			/* mov reg, disp(%rsp) */
249
-			*type = INSN_STACK;
250
-			op->src.type = OP_SRC_REG;
251
-			op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
252
-			op->dest.type = OP_DEST_REG_INDIRECT;
253
-			op->dest.reg = CFI_SP;
254
-			op->dest.offset = insn.displacement.value;
267
+			ADD_OP(op) {
268
+				op->src.type = OP_SRC_REG;
269
+				op->src.reg = op_to_cfi_reg[modrm_reg][rex_r];
270
+				op->dest.type = OP_DEST_REG_INDIRECT;
271
+				op->dest.reg = CFI_SP;
272
+				op->dest.offset = insn.displacement.value;
273
+			}
255
274
 		}
256
275
 
257
276
 		break;
..
..
@@ -260,23 +279,25 @@
260
279
 		if (rex_w && !rex_b && modrm_mod == 1 && modrm_rm == 5) {
261
280
 
262
281
 			/* mov disp(%rbp), reg */
263
-			*type = INSN_STACK;
264
-			op->src.type = OP_SRC_REG_INDIRECT;
265
-			op->src.reg = CFI_BP;
266
-			op->src.offset = insn.displacement.value;
267
-			op->dest.type = OP_DEST_REG;
268
-			op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
282
+			ADD_OP(op) {
283
+				op->src.type = OP_SRC_REG_INDIRECT;
284
+				op->src.reg = CFI_BP;
285
+				op->src.offset = insn.displacement.value;
286
+				op->dest.type = OP_DEST_REG;
287
+				op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
288
+			}
269
289
 
270
290
 		} else if (rex_w && !rex_b && sib == 0x24 &&
271
291
 			   modrm_mod != 3 && modrm_rm == 4) {
272
292
 
273
293
 			/* mov disp(%rsp), reg */
274
-			*type = INSN_STACK;
275
-			op->src.type = OP_SRC_REG_INDIRECT;
276
-			op->src.reg = CFI_SP;
277
-			op->src.offset = insn.displacement.value;
278
-			op->dest.type = OP_DEST_REG;
279
-			op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
294
+			ADD_OP(op) {
295
+				op->src.type = OP_SRC_REG_INDIRECT;
296
+				op->src.reg = CFI_SP;
297
+				op->src.offset = insn.displacement.value;
298
+				op->dest.type = OP_DEST_REG;
299
+				op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
300
+			}
280
301
 		}
281
302
 
282
303
 		break;
..
..
@@ -284,28 +305,30 @@
284
305
 	case 0x8d:
285
306
 		if (sib == 0x24 && rex_w && !rex_b && !rex_x) {
286
307
 
287
-			*type = INSN_STACK;
288
-			if (!insn.displacement.value) {
289
-				/* lea (%rsp), reg */
290
-				op->src.type = OP_SRC_REG;
291
-			} else {
292
-				/* lea disp(%rsp), reg */
293
-				op->src.type = OP_SRC_ADD;
294
-				op->src.offset = insn.displacement.value;
308
+			ADD_OP(op) {
309
+				if (!insn.displacement.value) {
310
+					/* lea (%rsp), reg */
311
+					op->src.type = OP_SRC_REG;
312
+				} else {
313
+					/* lea disp(%rsp), reg */
314
+					op->src.type = OP_SRC_ADD;
315
+					op->src.offset = insn.displacement.value;
316
+				}
317
+				op->src.reg = CFI_SP;
318
+				op->dest.type = OP_DEST_REG;
319
+				op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
295
320
 			}
296
-			op->src.reg = CFI_SP;
297
-			op->dest.type = OP_DEST_REG;
298
-			op->dest.reg = op_to_cfi_reg[modrm_reg][rex_r];
299
321
 
300
322
 		} else if (rex == 0x48 && modrm == 0x65) {
301
323
 
302
324
 			/* lea disp(%rbp), %rsp */
303
-			*type = INSN_STACK;
304
-			op->src.type = OP_SRC_ADD;
305
-			op->src.reg = CFI_BP;
306
-			op->src.offset = insn.displacement.value;
307
-			op->dest.type = OP_DEST_REG;
308
-			op->dest.reg = CFI_SP;
325
+			ADD_OP(op) {
326
+				op->src.type = OP_SRC_ADD;
327
+				op->src.reg = CFI_BP;
328
+				op->src.offset = insn.displacement.value;
329
+				op->dest.type = OP_DEST_REG;
330
+				op->dest.reg = CFI_SP;
331
+			}
309
332
 
310
333
 		} else if (rex == 0x49 && modrm == 0x62 &&
311
334
 			   insn.displacement.value == -8) {
..
..
@@ -316,12 +339,13 @@
316
339
 			 * Restoring rsp back to its original value after a
317
340
 			 * stack realignment.
318
341
 			 */
319
-			*type = INSN_STACK;
320
-			op->src.type = OP_SRC_ADD;
321
-			op->src.reg = CFI_R10;
322
-			op->src.offset = -8;
323
-			op->dest.type = OP_DEST_REG;
324
-			op->dest.reg = CFI_SP;
342
+			ADD_OP(op) {
343
+				op->src.type = OP_SRC_ADD;
344
+				op->src.reg = CFI_R10;
345
+				op->src.offset = -8;
346
+				op->dest.type = OP_DEST_REG;
347
+				op->dest.reg = CFI_SP;
348
+			}
325
349
 
326
350
 		} else if (rex == 0x49 && modrm == 0x65 &&
327
351
 			   insn.displacement.value == -16) {
..
..
@@ -332,21 +356,23 @@
332
356
 			 * Restoring rsp back to its original value after a
333
357
 			 * stack realignment.
334
358
 			 */
335
-			*type = INSN_STACK;
336
-			op->src.type = OP_SRC_ADD;
337
-			op->src.reg = CFI_R13;
338
-			op->src.offset = -16;
339
-			op->dest.type = OP_DEST_REG;
340
-			op->dest.reg = CFI_SP;
359
+			ADD_OP(op) {
360
+				op->src.type = OP_SRC_ADD;
361
+				op->src.reg = CFI_R13;
362
+				op->src.offset = -16;
363
+				op->dest.type = OP_DEST_REG;
364
+				op->dest.reg = CFI_SP;
365
+			}
341
366
 		}
342
367
 
343
368
 		break;
344
369
 
345
370
 	case 0x8f:
346
371
 		/* pop to mem */
347
-		*type = INSN_STACK;
348
-		op->src.type = OP_SRC_POP;
349
-		op->dest.type = OP_DEST_MEM;
372
+		ADD_OP(op) {
373
+			op->src.type = OP_SRC_POP;
374
+			op->dest.type = OP_DEST_MEM;
375
+		}
350
376
 		break;
351
377
 
352
378
 	case 0x90:
..
..
@@ -355,21 +381,30 @@
355
381
 
356
382
 	case 0x9c:
357
383
 		/* pushf */
358
-		*type = INSN_STACK;
359
-		op->src.type = OP_SRC_CONST;
360
-		op->dest.type = OP_DEST_PUSH;
384
+		ADD_OP(op) {
385
+			op->src.type = OP_SRC_CONST;
386
+			op->dest.type = OP_DEST_PUSHF;
387
+		}
361
388
 		break;
362
389
 
363
390
 	case 0x9d:
364
391
 		/* popf */
365
-		*type = INSN_STACK;
366
-		op->src.type = OP_SRC_POP;
367
-		op->dest.type = OP_DEST_MEM;
392
+		ADD_OP(op) {
393
+			op->src.type = OP_SRC_POPF;
394
+			op->dest.type = OP_DEST_MEM;
395
+		}
368
396
 		break;
369
397
 
370
398
 	case 0x0f:
371
399
 
372
-		if (op2 >= 0x80 && op2 <= 0x8f) {
400
+		if (op2 == 0x01) {
401
+
402
+			if (modrm == 0xca)
403
+				*type = INSN_CLAC;
404
+			else if (modrm == 0xcb)
405
+				*type = INSN_STAC;
406
+
407
+		} else if (op2 >= 0x80 && op2 <= 0x8f) {
373
408
 
374
409
 			*type = INSN_JUMP_CONDITIONAL;
375
410
 
..
..
@@ -392,16 +427,18 @@
392
427
 		} else if (op2 == 0xa0 || op2 == 0xa8) {
393
428
 
394
429
 			/* push fs/gs */
395
-			*type = INSN_STACK;
396
-			op->src.type = OP_SRC_CONST;
397
-			op->dest.type = OP_DEST_PUSH;
430
+			ADD_OP(op) {
431
+				op->src.type = OP_SRC_CONST;
432
+				op->dest.type = OP_DEST_PUSH;
433
+			}
398
434
 
399
435
 		} else if (op2 == 0xa1 || op2 == 0xa9) {
400
436
 
401
437
 			/* pop fs/gs */
402
-			*type = INSN_STACK;
403
-			op->src.type = OP_SRC_POP;
404
-			op->dest.type = OP_DEST_MEM;
438
+			ADD_OP(op) {
439
+				op->src.type = OP_SRC_POP;
440
+				op->dest.type = OP_DEST_MEM;
441
+			}
405
442
 		}
406
443
 
407
444
 		break;
..
..
@@ -414,9 +451,14 @@
414
451
 		 * mov bp, sp
415
452
 		 * pop bp
416
453
 		 */
417
-		*type = INSN_STACK;
418
-		op->dest.type = OP_DEST_LEAVE;
454
+		ADD_OP(op)
455
+			op->dest.type = OP_DEST_LEAVE;
419
456
 
457
+		break;
458
+
459
+	case 0xcc:
460
+		/* int3 */
461
+		*type = INSN_TRAP;
420
462
 		break;
421
463
 
422
464
 	case 0xe3:
..
..
@@ -434,14 +476,49 @@
434
476
 		*type = INSN_RETURN;
435
477
 		break;
436
478
 
479
+	case 0xcf: /* iret */
480
+		/*
481
+		 * Handle sync_core(), which has an IRET to self.
482
+		 * All other IRET are in STT_NONE entry code.
483
+		 */
484
+		sym = find_symbol_containing(sec, offset);
485
+		if (sym && sym->type == STT_FUNC) {
486
+			ADD_OP(op) {
487
+				/* add $40, %rsp */
488
+				op->src.type = OP_SRC_ADD;
489
+				op->src.reg = CFI_SP;
490
+				op->src.offset = 5*8;
491
+				op->dest.type = OP_DEST_REG;
492
+				op->dest.reg = CFI_SP;
493
+			}
494
+			break;
495
+		}
496
+
497
+		/* fallthrough */
498
+
437
499
 	case 0xca: /* retf */
438
500
 	case 0xcb: /* retf */
439
-	case 0xcf: /* iret */
440
501
 		*type = INSN_CONTEXT_SWITCH;
441
502
 		break;
442
503
 
443
504
 	case 0xe8:
444
505
 		*type = INSN_CALL;
506
+		/*
507
+		 * For the impact on the stack, a CALL behaves like
508
+		 * a PUSH of an immediate value (the return address).
509
+		 */
510
+		ADD_OP(op) {
511
+			op->src.type = OP_SRC_CONST;
512
+			op->dest.type = OP_DEST_PUSH;
513
+		}
514
+		break;
515
+
516
+	case 0xfc:
517
+		*type = INSN_CLD;
518
+		break;
519
+
520
+	case 0xfd:
521
+		*type = INSN_STD;
445
522
 		break;
446
523
 
447
524
 	case 0xff:
..
..
@@ -461,9 +538,10 @@
461
538
 		else if (modrm_reg == 6) {
462
539
 
463
540
 			/* push from mem */
464
-			*type = INSN_STACK;
465
-			op->src.type = OP_SRC_CONST;
466
-			op->dest.type = OP_DEST_PUSH;
541
+			ADD_OP(op) {
542
+				op->src.type = OP_SRC_CONST;
543
+				op->dest.type = OP_DEST_PUSH;
544
+			}
467
545
 		}
468
546
 
469
547
 		break;
..
..
@@ -477,7 +555,7 @@
477
555
 	return 0;
478
556
 }
479
557
 
480
-void arch_initial_func_cfi_state(struct cfi_state *state)
558
+void arch_initial_func_cfi_state(struct cfi_init_state *state)
481
559
 {
482
560
 	int i;
483
561
 
..
..
@@ -491,6 +569,94 @@
491
569
 	state->cfa.offset = 8;
492
570
 
493
571
 	/* initial RA (return address) */
494
-	state->regs[16].base = CFI_CFA;
495
-	state->regs[16].offset = -8;
572
+	state->regs[CFI_RA].base = CFI_CFA;
573
+	state->regs[CFI_RA].offset = -8;
574
+}
575
+
576
+const char *arch_nop_insn(int len)
577
+{
578
+	static const char nops[5][5] = {
579
+		/* 1 */ { 0x90 },
580
+		/* 2 */ { 0x66, 0x90 },
581
+		/* 3 */ { 0x0f, 0x1f, 0x00 },
582
+		/* 4 */ { 0x0f, 0x1f, 0x40, 0x00 },
583
+		/* 5 */ { 0x0f, 0x1f, 0x44, 0x00, 0x00 },
584
+	};
585
+
586
+	if (len < 1 || len > 5) {
587
+		WARN("invalid NOP size: %d\n", len);
588
+		return NULL;
589
+	}
590
+
591
+	return nops[len-1];
592
+}
593
+
594
+#define BYTE_RET	0xC3
595
+
596
+const char *arch_ret_insn(int len)
597
+{
598
+	static const char ret[5][5] = {
599
+		{ BYTE_RET },
600
+		{ BYTE_RET, 0xcc },
601
+		{ BYTE_RET, 0xcc, 0x90 },
602
+		{ BYTE_RET, 0xcc, 0x66, 0x90 },
603
+		{ BYTE_RET, 0xcc, 0x0f, 0x1f, 0x00 },
604
+	};
605
+
606
+	if (len < 1 || len > 5) {
607
+		WARN("invalid RET size: %d\n", len);
608
+		return NULL;
609
+	}
610
+
611
+	return ret[len-1];
612
+}
613
+
614
+int arch_decode_hint_reg(u8 sp_reg, int *base)
615
+{
616
+	switch (sp_reg) {
617
+	case ORC_REG_UNDEFINED:
618
+		*base = CFI_UNDEFINED;
619
+		break;
620
+	case ORC_REG_SP:
621
+		*base = CFI_SP;
622
+		break;
623
+	case ORC_REG_BP:
624
+		*base = CFI_BP;
625
+		break;
626
+	case ORC_REG_SP_INDIRECT:
627
+		*base = CFI_SP_INDIRECT;
628
+		break;
629
+	case ORC_REG_R10:
630
+		*base = CFI_R10;
631
+		break;
632
+	case ORC_REG_R13:
633
+		*base = CFI_R13;
634
+		break;
635
+	case ORC_REG_DI:
636
+		*base = CFI_DI;
637
+		break;
638
+	case ORC_REG_DX:
639
+		*base = CFI_DX;
640
+		break;
641
+	default:
642
+		return -1;
643
+	}
644
+
645
+	return 0;
646
+}
647
+
648
+bool arch_is_retpoline(struct symbol *sym)
649
+{
650
+	return !strncmp(sym->name, "__x86_indirect_", 15);
651
+}
652
+
653
+bool arch_is_rethunk(struct symbol *sym)
654
+{
655
+	return !strcmp(sym->name, "__x86_return_thunk");
656
+}
657
+
658
+bool arch_is_embedded_insn(struct symbol *sym)
659
+{
660
+	return !strcmp(sym->name, "retbleed_return_thunk") ||
661
+	       !strcmp(sym->name, "srso_safe_ret");
496
662
 }