~hc/RK356X_SDK_RELEASE.git

..	..	@@ -8,6 +8,8 @@
8	8	#define pr_fmt(fmt) "rga3_reg: " fmt
9	9
10	10	#include "rga3_reg_info.h"
	11	+#include "rga_dma_buf.h"
	12	+#include "rga_iommu.h"
11	13	#include "rga_common.h"
12	14	#include "rga_debugger.h"
13	15	#include "rga_hw_config.h"
..	..	@@ -91,14 +93,12 @@
91	93	dw = msg->win0.dst_act_w;
92	94	dh = msg->win0.dst_act_h;
93	95
94		- if (msg->win0.rotate_mode != 0) {
95		- if (rotate_mode) {
96		- sh = msg->win0.src_act_w;
97		- sw = msg->win0.src_act_h;
98		- } else {
99		- sw = msg->win0.src_act_w;
100		- sh = msg->win0.src_act_h;
101		- }
	96	+ if (rotate_mode) {
	97	+ sh = msg->win0.src_act_w;
	98	+ sw = msg->win0.src_act_h;
	99	+ } else {
	100	+ sw = msg->win0.src_act_w;
	101	+ sh = msg->win0.src_act_h;
102	102	}
103	103
104	104	if (sw > dw) {
..	..	@@ -289,7 +289,7 @@
289	289	}
290	290
291	291	/* rotate & mirror */
292		- if (msg->win1.yrgb_addr == 0) {
	292	+ if (msg->win0.rotate_mode == 1) {
293	293	reg =
294	294	((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT)) \|
295	295	(s_RGA3_WIN0_RD_CTRL_SW_WIN0_ROT(rotate_mode)));
..	..	@@ -299,36 +299,23 @@
299	299	reg =
300	300	((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR)) \|
301	301	(s_RGA3_WIN0_RD_CTRL_SW_WIN0_YMIRROR(ymirror)));
302		-
303		- /* scale */
304		- *bRGA3_WIN0_SCL_FAC = param_x \| param_y << 16;
305		-
306		- reg =
307		- ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY)) \|
308		- (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x_by)));
309		- reg =
310		- ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP)) \|
311		- (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x_up)));
312		- reg =
313		- ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY)) \|
314		- (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(y_by)));
315		- reg =
316		- ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP)) \|
317		- (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(y_up)));
318		- } else {
319		- reg =
320		- ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY)) \|
321		- (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(1)));
322		- reg =
323		- ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP)) \|
324		- (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(0)));
325		- reg =
326		- ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY)) \|
327		- (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(1)));
328		- reg =
329		- ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP)) \|
330		- (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(0)));
331	302	}
	303	+
	304	+ /* scale */
	305	+ *bRGA3_WIN0_SCL_FAC = param_x \| param_y << 16;
	306	+
	307	+ reg =
	308	+ ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY)) \|
	309	+ (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_BY(x_by)));
	310	+ reg =
	311	+ ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP)) \|
	312	+ (s_RGA3_WIN0_RD_CTRL_SW_WIN0_HOR_UP(x_up)));
	313	+ reg =
	314	+ ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY)) \|
	315	+ (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_BY(y_by)));
	316	+ reg =
	317	+ ((reg & (~m_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP)) \|
	318	+ (s_RGA3_WIN0_RD_CTRL_SW_WIN0_VER_UP(y_up)));
332	319
333	320	/* rd_mode */
334	321	reg =
..	..	@@ -357,19 +344,36 @@
357	344
358	345	*bRGA3_WIN0_RD_CTRL = reg;
359	346
360		- /* stride need align to 16 */
361		- if (msg->win0.rd_mode != 1)
	347	+ switch (msg->win0.rd_mode) {
	348	+ case 0: /* raster */
362	349	stride = (((msg->win0.vir_w * pixel_width) + 15) & ~15) >> 2;
363		- else
364		- stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
	350	+ if (rga_is_yuv420_semi_planar_format(msg->win0.format))
	351	+ uv_stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
	352	+ else
	353	+ uv_stride = stride;
	354	+ break;
365	355
366		- if (msg->win0.format == RGA_FORMAT_YCbCr_420_SP
367		- \|\| msg->win0.format == RGA_FORMAT_YCrCb_420_SP
368		- \|\| msg->win0.format == RGA_FORMAT_YCbCr_420_SP_10B
369		- \|\| msg->win0.format == RGA_FORMAT_YCrCb_420_SP_10B)
370		- uv_stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
371		- else
372		- uv_stride = stride;
	356	+ case 1: /* fbc */
	357	+ stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
	358	+ if (rga_is_yuv420_semi_planar_format(msg->win0.format))
	359	+ uv_stride = ((msg->win0.vir_w + 15) & ~15) >> 2;
	360	+ else
	361	+ uv_stride = stride;
	362	+ break;
	363	+
	364	+ case 2: /* tile 88 /
	365	+ /*
	366	+ * tile 8*8 mode 8 lines of data are read/written at one time,
	367	+ * so stride needs * 8. YUV420 only has 4 lines of UV data, so
	368	+ * it needs to >>1.
	369	+ */
	370	+ stride = (((msg->win0.vir_w * pixel_width * 8) + 15) & ~15) >> 2;
	371	+ if (rga_is_yuv420_semi_planar_format(msg->win0.format))
	372	+ uv_stride = ((((msg->win0.vir_w * 8) + 15) & ~15) >> 1) >> 2;
	373	+ else
	374	+ uv_stride = stride;
	375	+ break;
	376	+ }
373	377
374	378	*bRGA3_WIN0_Y_BASE = (u32) msg->win0.yrgb_addr;
375	379	*bRGA3_WIN0_U_BASE = (u32) msg->win0.uv_addr;
..	..	@@ -386,9 +390,9 @@
386	390	*/
387	391
388	392	/* do not use win0 src size except fbcd */
389		- *bRGA3_WIN0_SRC_SIZE = (msg->win0.src_act_w +
390		- msg->win0.x_offset) \| ((msg->win0.y_offset +
391		- msg->win0.src_act_h) << 16);
	393	+ /* in FBCD, src_width needs to be aligned at 16 */
	394	+ *bRGA3_WIN0_SRC_SIZE = ALIGN(msg->win0.src_act_w + msg->win0.x_offset, 16) \|
	395	+ (ALIGN(msg->win0.y_offset + msg->win0.src_act_h, 16) << 16);
392	396	*bRGA3_WIN0_ACT_SIZE =
393	397	msg->win0.src_act_w \| (msg->win0.src_act_h << 16);
394	398	*bRGA3_WIN0_DST_SIZE =
..	..	@@ -721,19 +725,31 @@
721	725
722	726	*bRGA3_WIN1_RD_CTRL = reg;
723	727
724		- /* stride need align to 16 */
725		- if (msg->win1.rd_mode != 1)
	728	+ switch (msg->win1.rd_mode) {
	729	+ case 0: /* raster */
726	730	stride = (((msg->win1.vir_w * pixel_width) + 15) & ~15) >> 2;
727		- else
728		- stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
	731	+ if (rga_is_yuv420_semi_planar_format(msg->win1.format))
	732	+ uv_stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
	733	+ else
	734	+ uv_stride = stride;
	735	+ break;
729	736
730		- if (msg->win1.format == RGA_FORMAT_YCbCr_420_SP
731		- \|\| msg->win1.format == RGA_FORMAT_YCrCb_420_SP
732		- \|\| msg->win1.format == RGA_FORMAT_YCbCr_420_SP_10B
733		- \|\| msg->win1.format == RGA_FORMAT_YCrCb_420_SP_10B)
734		- uv_stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
735		- else
736		- uv_stride = stride;
	737	+ case 1: /* fbc */
	738	+ stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
	739	+ if (rga_is_yuv420_semi_planar_format(msg->win1.format))
	740	+ uv_stride = ((msg->win1.vir_w + 15) & ~15) >> 2;
	741	+ else
	742	+ uv_stride = stride;
	743	+ break;
	744	+
	745	+ case 2: /* tile 88 /
	746	+ stride = (((msg->win1.vir_w * pixel_width * 8) + 15) & ~15) >> 2;
	747	+ if (rga_is_yuv420_semi_planar_format(msg->win1.format))
	748	+ uv_stride = ((((msg->win1.vir_w * 8) + 15) & ~15) >> 1) >> 2;
	749	+ else
	750	+ uv_stride = stride;
	751	+ break;
	752	+ }
737	753
738	754	*bRGA3_WIN1_Y_BASE = (u32) msg->win1.yrgb_addr;
739	755	*bRGA3_WIN1_U_BASE = (u32) msg->win1.uv_addr;
..	..	@@ -947,16 +963,20 @@
947	963	*bRGA3_WR_RD_CTRL = reg;
948	964	*bRGA3_WR_FBCD_CTRL = fbcd_reg;
949	965
950		- /* stride need align to 16 */
951		- if (msg->wr.rd_mode != 1) {
	966	+ switch (msg->wr.rd_mode) {
	967	+ case 0: /* raster */
952	968	stride = (((msg->wr.vir_w * pixel_width) + 15) & ~15) >> 2;
953		- *bRGA3_WR_U_BASE = (u32) msg->wr.uv_addr;
954	969	uv_stride = ((msg->wr.vir_w + 15) & ~15) >> 2;
955		- } else {
	970	+
	971	+ *bRGA3_WR_U_BASE = (u32) msg->wr.uv_addr;
	972	+
	973	+ break;
	974	+
	975	+ case 1: /* fbc */
956	976	stride = ((msg->wr.vir_w + 15) & ~15) >> 2;
957	977	/* need to calculate fbcd header size */
958	978	vir_h = ((msg->wr.vir_h + 15) & ~15);
959		- bRGA3_WR_U_BASE = (u32) (msg->wr.uv_addr + ((stride vir_h)>>2));
	979	+
960	980	/* RGBA8888 */
961	981	if (wr_format == 0x6)
962	982	uv_stride = ((msg->wr.vir_w + 15) & ~15);
..	..	@@ -972,6 +992,20 @@
972	992	/* yuv422 10bit */
973	993	else if (wr_format == 0x3)
974	994	uv_stride = (((msg->wr.vir_w + 15) & ~15) >> 3) * 5;
	995	+
	996	+ bRGA3_WR_U_BASE = (u32) (msg->wr.uv_addr + ((stride vir_h)>>2));
	997	+
	998	+ break;
	999	+
	1000	+ case 2: /* tile 88 /
	1001	+ stride = (((msg->wr.vir_w * pixel_width * 8) + 15) & ~15) >> 2;
	1002	+ if (rga_is_yuv420_semi_planar_format(msg->win0.format))
	1003	+ uv_stride = ((((msg->wr.vir_w * 8) + 15) & ~15) >> 1) >> 2;
	1004	+ else
	1005	+ uv_stride = stride;
	1006	+
	1007	+ *bRGA3_WR_U_BASE = (u32) msg->wr.uv_addr;
	1008	+ break;
975	1009	}
976	1010
977	1011	*bRGA3_WR_Y_BASE = (u32) msg->wr.yrgb_addr;
..	..	@@ -994,6 +1028,9 @@
994	1028	u32 *bRGA3_OVLP_OFF;
995	1029
996	1030	u32 reg;
	1031	+ union rga3_color_ctrl top_color_ctrl, bottom_color_ctrl;
	1032	+ union rga3_alpha_ctrl top_alpha_ctrl, bottom_alpha_ctrl;
	1033	+ struct rga_alpha_config *config;
997	1034
998	1035	bRGA_OVERLAP_TOP_CTRL = (u32 *) (base + RGA3_OVLP_TOP_CTRL_OFFSET);
999	1036	bRGA_OVERLAP_BOT_CTRL = (u32 *) (base + RGA3_OVLP_BOT_CTRL_OFFSET);
..	..	@@ -1005,98 +1042,249 @@
1005	1042
1006	1043	/* Alpha blend */
1007	1044	/bot -> win0(dst), top -> win1(src). /
1008		- reg = 0;
1009		- reg =
1010		- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0)) \|
1011		- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_COLOR_M0
1012		- (msg->alpha_mode_0 >> 7)));
1013		- reg =
1014		- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0)) \|
1015		- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_M0
1016		- (msg->alpha_mode_0 >> 0)));
1017		- reg =
1018		- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0)) \|
1019		- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_BLEND_M0
1020		- (msg->alpha_mode_0 >> 1)));
1021		- reg =
1022		- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0)) \|
1023		- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_ALPHA_CAL_M0
1024		- (msg->alpha_mode_0 >> 3)));
1025		- reg =
1026		- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0)) \|
1027		- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_FACTOR_M0
1028		- (msg->alpha_mode_0 >> 4)));
1029		- reg =
1030		- ((reg & (~m_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA)) \|
1031		- (s_RGA3_OVLP_TOP_CTRL_SW_TOP_GLOBAL_ALPHA
1032		- (msg->win1_a_global_val)));
1033		- *bRGA_OVERLAP_TOP_CTRL = reg;
	1045	+ top_color_ctrl.value = 0;
	1046	+ bottom_color_ctrl.value = 0;
	1047	+ top_alpha_ctrl.value = 0;
	1048	+ bottom_alpha_ctrl.value = 0;
	1049	+ config = &msg->alpha_config;
1034	1050
1035		- reg = 0;
1036		- reg =
1037		- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0)) \|
1038		- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_COLOR_M0
1039		- (msg->alpha_mode_0 >> 15)));
1040		- reg =
1041		- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0)) \|
1042		- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_M0
1043		- (msg->alpha_mode_0 >> 8)));
1044		- reg =
1045		- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0)) \|
1046		- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_BLEND_M0
1047		- (msg->alpha_mode_0 >> 9)));
1048		- reg =
1049		- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0)) \|
1050		- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_ALPHA_CAL_M0
1051		- (msg->alpha_mode_0 >> 11)));
1052		- reg =
1053		- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0)) \|
1054		- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_FACTOR_M0
1055		- (msg->alpha_mode_0 >> 12)));
1056		- reg =
1057		- ((reg & (~m_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA)) \|
1058		- (s_RGA3_OVLP_BOT_CTRL_SW_BOT_GLOBAL_ALPHA
1059		- (msg->win0_a_global_val)));
1060		- *bRGA_OVERLAP_BOT_CTRL = reg;
	1051	+ if (config->fg_pixel_alpha_en)
	1052	+ top_color_ctrl.bits.blend_mode =
	1053	+ config->fg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
	1054	+ RGA_ALPHA_PER_PIXEL;
	1055	+ else
	1056	+ top_color_ctrl.bits.blend_mode = RGA_ALPHA_GLOBAL;
1061	1057
1062		- reg = 0;
1063		- reg =
1064		- ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1)) \|
1065		- (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_M1
1066		- (msg->alpha_mode_1 >> 0)));
1067		- reg =
1068		- ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1)) \|
1069		- (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_BLEND_M1
1070		- (msg->alpha_mode_1 >> 1)));
1071		- reg =
1072		- ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1)) \|
1073		- (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_ALPHA_CAL_M1
1074		- (msg->alpha_mode_1 >> 3)));
1075		- reg =
1076		- ((reg & (~m_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1)) \|
1077		- (s_RGA3_OVLP_TOP_ALPHA_SW_TOP_FACTOR_M1
1078		- (msg->alpha_mode_1 >> 4)));
1079		- *bRGA_OVERLAP_TOP_ALPHA = reg;
	1058	+ if (config->bg_pixel_alpha_en)
	1059	+ bottom_color_ctrl.bits.blend_mode =
	1060	+ config->bg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
	1061	+ RGA_ALPHA_PER_PIXEL;
	1062	+ else
	1063	+ bottom_color_ctrl.bits.blend_mode = RGA_ALPHA_GLOBAL;
1080	1064
1081		- reg = 0;
1082		- reg =
1083		- ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1)) \|
1084		- (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_M1
1085		- (msg->alpha_mode_1 >> 8)));
1086		- reg =
1087		- ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1)) \|
1088		- (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_BLEND_M1
1089		- (msg->alpha_mode_1 >> 9)));
1090		- reg =
1091		- ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1)) \|
1092		- (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_ALPHA_CAL_M1
1093		- (msg->alpha_mode_1 >> 11)));
1094		- reg =
1095		- ((reg & (~m_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1)) \|
1096		- (s_RGA3_OVLP_BOT_ALPHA_SW_BOT_FACTOR_M1
1097		- (msg->alpha_mode_1 >> 12)));
	1065	+ /*
	1066	+ * Since the hardware uses 256 as 1, the original alpha value needs to
	1067	+ * be + (alpha >> 7).
	1068	+ */
	1069	+ top_color_ctrl.bits.alpha_cal_mode = RGA_ALPHA_SATURATION;
	1070	+ bottom_color_ctrl.bits.alpha_cal_mode = RGA_ALPHA_SATURATION;
1098	1071
1099		- *bRGA_OVERLAP_BOT_ALPHA = reg;
	1072	+ top_color_ctrl.bits.global_alpha = config->fg_global_alpha_value;
	1073	+ bottom_color_ctrl.bits.global_alpha = config->bg_global_alpha_value;
	1074	+
	1075	+ /* porter duff alpha enable */
	1076	+ switch (config->mode) {
	1077	+ case RGA_ALPHA_BLEND_SRC:
	1078	+ /*
	1079	+ * SRC mode:
	1080	+ * Sf = 1, Df = 0；
	1081	+ * [Rc,Ra] = [Sc,Sa]；
	1082	+ */
	1083	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1084	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
	1085	+
	1086	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1087	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
	1088	+
	1089	+ break;
	1090	+
	1091	+ case RGA_ALPHA_BLEND_DST:
	1092	+ /*
	1093	+ * SRC mode:
	1094	+ * Sf = 0, Df = 1；
	1095	+ * [Rc,Ra] = [Dc,Da]；
	1096	+ */
	1097	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1098	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
	1099	+
	1100	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1101	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
	1102	+
	1103	+ break;
	1104	+
	1105	+ case RGA_ALPHA_BLEND_SRC_OVER:
	1106	+ /*
	1107	+ * SRC-OVER mode:
	1108	+ * Sf = 1, Df = (1 - Sa)
	1109	+ * [Rc,Ra] = [ Sc + (1 - Sa) * Dc, Sa + (1 - Sa) * Da ]
	1110	+ */
	1111	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1112	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
	1113	+
	1114	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1115	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
	1116	+
	1117	+ break;
	1118	+
	1119	+ case RGA_ALPHA_BLEND_DST_OVER:
	1120	+ /*
	1121	+ * DST-OVER mode:
	1122	+ * Sf = (1 - Da) , Df = 1
	1123	+ * [Rc,Ra] = [ Sc * (1 - Da) + Dc, Sa * (1 - Da) + Da ]
	1124	+ */
	1125	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1126	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
	1127	+
	1128	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1129	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ONE;
	1130	+
	1131	+ break;
	1132	+
	1133	+ case RGA_ALPHA_BLEND_SRC_IN:
	1134	+ /*
	1135	+ * SRC-IN mode:
	1136	+ * Sf = Da , Df = 0
	1137	+ * [Rc,Ra] = [ Sc * Da, Sa * Da ]
	1138	+ */
	1139	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1140	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
	1141	+
	1142	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1143	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
	1144	+
	1145	+ break;
	1146	+
	1147	+ case RGA_ALPHA_BLEND_DST_IN:
	1148	+ /*
	1149	+ * DST-IN mode:
	1150	+ * Sf = 0 , Df = Sa
	1151	+ * [Rc,Ra] = [ Dc * Sa, Da * Sa ]
	1152	+ */
	1153	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1154	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
	1155	+
	1156	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1157	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
	1158	+
	1159	+ break;
	1160	+
	1161	+ case RGA_ALPHA_BLEND_SRC_OUT:
	1162	+ /*
	1163	+ * SRC-OUT mode:
	1164	+ * Sf = (1 - Da) , Df = 0
	1165	+ * [Rc,Ra] = [ Sc * (1 - Da), Sa * (1 - Da) ]
	1166	+ */
	1167	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1168	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
	1169	+
	1170	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1171	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
	1172	+
	1173	+ break;
	1174	+
	1175	+ case RGA_ALPHA_BLEND_DST_OUT:
	1176	+ /*
	1177	+ * DST-OUT mode:
	1178	+ * Sf = 0 , Df = (1 - Sa)
	1179	+ * [Rc,Ra] = [ Dc * (1 - Sa), Da * (1 - Sa) ]
	1180	+ */
	1181	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1182	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
	1183	+
	1184	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1185	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
	1186	+
	1187	+ break;
	1188	+
	1189	+ case RGA_ALPHA_BLEND_SRC_ATOP:
	1190	+ /*
	1191	+ * SRC-ATOP mode:
	1192	+ * Sf = Da , Df = (1 - Sa)
	1193	+ * [Rc,Ra] = [ Sc * Da + Dc * (1 - Sa), Sa * Da + Da * (1 - Sa) ]
	1194	+ */
	1195	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1196	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
	1197	+
	1198	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1199	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
	1200	+
	1201	+ break;
	1202	+
	1203	+ case RGA_ALPHA_BLEND_DST_ATOP:
	1204	+ /*
	1205	+ * DST-ATOP mode:
	1206	+ * Sf = (1 - Da) , Df = Sa
	1207	+ * [Rc,Ra] = [ Sc * (1 - Da) + Dc * Sa, Sa * (1 - Da) + Da * Sa ]
	1208	+ */
	1209	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1210	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
	1211	+
	1212	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1213	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE;
	1214	+
	1215	+ break;
	1216	+
	1217	+ case RGA_ALPHA_BLEND_XOR:
	1218	+ /*
	1219	+ * DST-XOR mode:
	1220	+ * Sf = (1 - Da) , Df = (1 - Sa)
	1221	+ * [Rc,Ra] = [ Sc * (1 - Da) + Dc * (1 - Sa), Sa * (1 - Da) + Da * (1 - Sa) ]
	1222	+ */
	1223	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1224	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
	1225	+
	1226	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1227	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
	1228	+
	1229	+ break;
	1230	+
	1231	+ case RGA_ALPHA_BLEND_CLEAR:
	1232	+ /*
	1233	+ * DST-CLEAR mode:
	1234	+ * Sf = 0 , Df = 0
	1235	+ * [Rc,Ra] = [ 0, 0 ]
	1236	+ */
	1237	+ top_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1238	+ top_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
	1239	+
	1240	+ bottom_color_ctrl.bits.alpha_mode = RGA_ALPHA_STRAIGHT;
	1241	+ bottom_color_ctrl.bits.factor_mode = RGA_ALPHA_ZERO;
	1242	+
	1243	+ break;
	1244	+
	1245	+ default:
	1246	+ break;
	1247	+ }
	1248	+
	1249	+ if (!config->enable && msg->abb_alpha_pass) {
	1250	+ /*
	1251	+ * enabled by default bot_blend_m1 && bot_alpha_cal_m1 for src channel(win0)
	1252	+ * In ABB mode, the number will be fetched according to 16*16, so it needs to
	1253	+ * be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr).
	1254	+ */
	1255	+ top_color_ctrl.bits.color_mode = RGA_ALPHA_PRE_MULTIPLIED;
	1256	+
	1257	+ top_alpha_ctrl.bits.blend_mode = RGA_ALPHA_PER_PIXEL;
	1258	+ top_alpha_ctrl.bits.alpha_cal_mode = RGA_ALPHA_NO_SATURATION;
	1259	+
	1260	+ bottom_color_ctrl.bits.color_mode = RGA_ALPHA_PRE_MULTIPLIED;
	1261	+
	1262	+ bottom_alpha_ctrl.bits.blend_mode = RGA_ALPHA_PER_PIXEL;
	1263	+ bottom_alpha_ctrl.bits.alpha_cal_mode = RGA_ALPHA_NO_SATURATION;
	1264	+ } else {
	1265	+ top_color_ctrl.bits.color_mode =
	1266	+ config->fg_pre_multiplied ?
	1267	+ RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
	1268	+
	1269	+ top_alpha_ctrl.bits.blend_mode = top_color_ctrl.bits.blend_mode;
	1270	+ top_alpha_ctrl.bits.alpha_cal_mode = top_color_ctrl.bits.alpha_cal_mode;
	1271	+ top_alpha_ctrl.bits.alpha_mode = top_color_ctrl.bits.alpha_mode;
	1272	+ top_alpha_ctrl.bits.factor_mode = top_color_ctrl.bits.factor_mode;
	1273	+
	1274	+ bottom_color_ctrl.bits.color_mode =
	1275	+ config->bg_pre_multiplied ?
	1276	+ RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
	1277	+
	1278	+ bottom_alpha_ctrl.bits.blend_mode = bottom_color_ctrl.bits.blend_mode;
	1279	+ bottom_alpha_ctrl.bits.alpha_cal_mode = bottom_color_ctrl.bits.alpha_cal_mode;
	1280	+ bottom_alpha_ctrl.bits.alpha_mode = bottom_color_ctrl.bits.alpha_mode;
	1281	+ bottom_alpha_ctrl.bits.factor_mode = bottom_color_ctrl.bits.factor_mode;
	1282	+ }
	1283	+
	1284	+ *bRGA_OVERLAP_TOP_CTRL = top_color_ctrl.value;
	1285	+ *bRGA_OVERLAP_BOT_CTRL = bottom_color_ctrl.value;
	1286	+ *bRGA_OVERLAP_TOP_ALPHA = top_alpha_ctrl.value;
	1287	+ *bRGA_OVERLAP_BOT_ALPHA = bottom_alpha_ctrl.value;
1100	1288
1101	1289	/* set RGA_OVERLAP_CTRL */
1102	1290	reg = 0;
..	..	@@ -1132,16 +1320,15 @@
1132	1320	* warning: if m1 & m0 need config split，need to redesign
1133	1321	* this judge, which consider RGBA8888 format
1134	1322	*/
1135		- if (msg->alpha_mode_1 > 0 && msg->alpha_mode_0 > 0)
1136		- reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN)) \|
1137		- (s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(1)));
	1323	+ reg = ((reg & (~m_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN)) \|
	1324	+ (s_RGA3_OVLP_CTRL_SW_TOP_ALPHA_EN(config->enable)));
1138	1325
1139	1326	*bRGA_OVERLAP_CTRL = reg;
1140	1327
1141	1328	*bRGA3_OVLP_OFF = msg->wr.x_offset \| (msg->wr.y_offset << 16);
1142	1329	}
1143	1330
1144		-int rga3_gen_reg_info(u8 base, struct rga3_req msg)
	1331	+static int rga3_gen_reg_info(u8 base, struct rga3_req msg)
1145	1332	{
1146	1333	switch (msg->render_mode) {
1147	1334	case BITBLT_MODE:
..	..	@@ -1225,9 +1412,8 @@
1225	1412	}
1226	1413
1227	1414	/* TODO: common part */
1228		-void rga_cmd_to_rga3_cmd(struct rga_req req_rga, struct rga3_req req)
	1415	+static void rga_cmd_to_rga3_cmd(struct rga_req req_rga, struct rga3_req req)
1229	1416	{
1230		- u16 alpha_mode_0, alpha_mode_1;
1231	1417	struct rga_img_info_t tmp;
1232	1418
1233	1419	req->render_mode = BITBLT_MODE;
..	..	@@ -1290,8 +1476,8 @@
1290	1476	if (!(req_rga->alpha_rop_flag & 1)) {
1291	1477	if (!rga_is_alpha_format(req_rga->src.format) &&
1292	1478	rga_is_alpha_format(req_rga->dst.format)) {
1293		- req->win0_a_global_val = 0xff;
1294		- req->win1_a_global_val = 0xff;
	1479	+ req->alpha_config.fg_global_alpha_value = 0xff;
	1480	+ req->alpha_config.bg_global_alpha_value = 0xff;
1295	1481	}
1296	1482	}
1297	1483
..	..	@@ -1311,7 +1497,7 @@
1311	1497	* be enabled top_blend_m1 && top_alpha_cal_m1 for dst channel(wr).
1312	1498	*/
1313	1499	if (rga_is_alpha_format(req_rga->src.format))
1314		- req->alpha_mode_1 = 0x0a0a;
	1500	+ req->abb_alpha_pass = true;
1315	1501
1316	1502	set_win_info(&req->win0, &req_rga->src);
1317	1503
..	..	@@ -1341,7 +1527,7 @@
1341	1527	* be enabled bot_blend_m1 && bot_alpha_cal_m1 for src1/dst channel(win0).
1342	1528	*/
1343	1529	if (rga_is_alpha_format(req_rga->src.format))
1344		- req->alpha_mode_1 = 0x0a0a;
	1530	+ req->abb_alpha_pass = true;
1345	1531
1346	1532	if (req_rga->pat.yrgb_addr != 0) {
1347	1533	if (req_rga->src.yrgb_addr == req_rga->dst.yrgb_addr) {
..	..	@@ -1385,18 +1571,18 @@
1385	1571	if (req->win0.x_offset \|\| req->win0.y_offset) {
1386	1572	req->win0.src_act_w = req->win0.src_act_w + req->win0.x_offset;
1387	1573	req->win0.src_act_h = req->win0.src_act_h + req->win0.y_offset;
1388		- req->win0.dst_act_w = req_rga->pat.act_w + req->win0.x_offset;
1389		- req->win0.dst_act_h = req_rga->pat.act_h + req->win0.y_offset;
	1574	+ req->win0.dst_act_w = req_rga->dst.act_w + req->win0.x_offset;
	1575	+ req->win0.dst_act_h = req_rga->dst.act_h + req->win0.y_offset;
1390	1576
1391	1577	req->win0.x_offset = 0;
1392	1578	req->win0.y_offset = 0;
1393	1579	} else {
1394		- req->win0.dst_act_w = req_rga->pat.act_w;
1395		- req->win0.dst_act_h = req_rga->pat.act_h;
	1580	+ req->win0.dst_act_w = req_rga->dst.act_w;
	1581	+ req->win0.dst_act_h = req_rga->dst.act_h;
1396	1582	}
1397	1583	/* set win1 dst size */
1398		- req->win1.dst_act_w = req_rga->pat.act_w;
1399		- req->win1.dst_act_h = req_rga->pat.act_h;
	1584	+ req->win1.dst_act_w = req_rga->dst.act_w;
	1585	+ req->win1.dst_act_h = req_rga->dst.act_h;
1400	1586	} else {
1401	1587	/* A+B->B mode */
1402	1588	set_win_info(&req->win0, &req_rga->dst);
..	..	@@ -1444,103 +1630,43 @@
1444	1630	/* Alpha blend mode */
1445	1631	if (((req_rga->alpha_rop_flag) & 1)) {
1446	1632	if ((req_rga->alpha_rop_flag >> 3) & 1) {
1447		- /* porter duff alpha enable */
1448		- switch (req_rga->PD_mode) {
1449		- /* dst = 0 */
1450		- case 0:
1451		- break;
1452		- /* dst = src */
1453		- case 1:
1454		- req->alpha_mode_0 = 0x0212;
1455		- req->alpha_mode_1 = 0x0212;
1456		- break;
1457		- /* dst = dst */
1458		- case 2:
1459		- req->alpha_mode_0 = 0x1202;
1460		- req->alpha_mode_1 = 0x1202;
1461		- break;
1462		- /* dst = (256sc + (256 - sa)dc) >> 8 */
1463		- case 3:
1464		- if ((req_rga->alpha_rop_mode & 3) == 0) {
1465		- /* both use globalAlpha. */
1466		- alpha_mode_0 = 0x3010;
1467		- alpha_mode_1 = 0x3010;
1468		- } else if ((req_rga->alpha_rop_mode & 3) == 1) {
1469		- /* Do not use globalAlpha. */
1470		- alpha_mode_0 = 0x3212;
1471		- alpha_mode_1 = 0x3212;
1472		- } else if ((req_rga->alpha_rop_mode & 3) == 2) {
1473		- /*
1474		- * dst use globalAlpha,
1475		- * and dst has pixelAlpha.
1476		- */
1477		- alpha_mode_0 = 0x3014;
1478		- alpha_mode_1 = 0x3014;
1479		- } else {
1480		- /*
1481		- * dst use globalAlpha,
1482		- * and dst does not have pixelAlpha.
1483		- */
1484		- alpha_mode_0 = 0x3012;
1485		- alpha_mode_1 = 0x3012;
1486		- }
1487		- req->alpha_mode_0 = alpha_mode_0;
1488		- req->alpha_mode_1 = alpha_mode_1;
1489		- break;
1490		- /* dst = (sc(256-da) + 256dc) >> 8 */
1491		- case 4:
1492		- /* Do not use globalAlpha. */
1493		- req->alpha_mode_0 = 0x1232;
1494		- req->alpha_mode_1 = 0x1232;
1495		- break;
1496		- /* dst = (dasc) >> 8 /
1497		- case 5:
1498		- break;
1499		- /* dst = (sadc) >> 8 /
1500		- case 6:
1501		- break;
1502		- /* dst = ((256-da)sc) >> 8 /
1503		- case 7:
1504		- break;
1505		- /* dst = ((256-sa)dc) >> 8 /
1506		- case 8:
1507		- break;
1508		- /* dst = (dasc + (256-sa)dc) >> 8 */
1509		- case 9:
1510		- req->alpha_mode_0 = 0x3040;
1511		- req->alpha_mode_1 = 0x3040;
1512		- break;
1513		- /* dst = ((256-da)sc + (sadc)) >> 8 */
1514		- case 10:
1515		- break;
1516		- /* dst = ((256-da)sc + (256-sa)dc) >> 8 */
1517		- case 11:
1518		- break;
1519		- case 12:
1520		- req->alpha_mode_0 = 0x0010;
1521		- req->alpha_mode_1 = 0x0820;
1522		- break;
1523		- default:
1524		- break;
1525		- }
1526		- /* Real color mode */
	1633	+ req->alpha_config.enable = true;
	1634	+
1527	1635	if ((req_rga->alpha_rop_flag >> 9) & 1) {
1528		- if (req->alpha_mode_0 & (0x01 << 1))
1529		- req->alpha_mode_0 \|= (1 << 7);
1530		- if (req->alpha_mode_0 & (0x01 << 9))
1531		- req->alpha_mode_0 \|= (1 << 15);
	1636	+ req->alpha_config.fg_pre_multiplied = false;
	1637	+ req->alpha_config.bg_pre_multiplied = false;
	1638	+ } else {
	1639	+ req->alpha_config.fg_pre_multiplied = true;
	1640	+ req->alpha_config.bg_pre_multiplied = true;
1532	1641	}
1533		- } else {
1534		- if ((req_rga->alpha_rop_mode & 3) == 0) {
1535		- req->alpha_mode_0 = 0x3040;
1536		- req->alpha_mode_1 = 0x3040;
1537		- } else if ((req_rga->alpha_rop_mode & 3) == 1) {
1538		- req->alpha_mode_0 = 0x3042;
1539		- req->alpha_mode_1 = 0x3242;
1540		- } else if ((req_rga->alpha_rop_mode & 3) == 2) {
1541		- req->alpha_mode_0 = 0x3044;
1542		- req->alpha_mode_1 = 0x3044;
	1642	+
	1643	+ req->alpha_config.fg_pixel_alpha_en = rga_is_alpha_format(req->win1.format);
	1644	+ req->alpha_config.bg_pixel_alpha_en = rga_is_alpha_format(req->win0.format);
	1645	+
	1646	+ if (req_rga->feature.global_alpha_en) {
	1647	+ if (req_rga->fg_global_alpha < 0xff) {
	1648	+ req->alpha_config.fg_global_alpha_en = true;
	1649	+ req->alpha_config.fg_global_alpha_value =
	1650	+ req_rga->fg_global_alpha;
	1651	+ } else if (!req->alpha_config.fg_pixel_alpha_en) {
	1652	+ req->alpha_config.fg_global_alpha_en = true;
	1653	+ req->alpha_config.fg_global_alpha_value = 0xff;
	1654	+ }
	1655	+
	1656	+ if (req_rga->bg_global_alpha < 0xff) {
	1657	+ req->alpha_config.bg_global_alpha_en = true;
	1658	+ req->alpha_config.bg_global_alpha_value =
	1659	+ req_rga->bg_global_alpha;
	1660	+ } else if (!req->alpha_config.bg_pixel_alpha_en) {
	1661	+ req->alpha_config.bg_global_alpha_en = true;
	1662	+ req->alpha_config.bg_global_alpha_value = 0xff;
	1663	+ }
	1664	+ } else {
	1665	+ req->alpha_config.bg_global_alpha_value = 0xff;
	1666	+ req->alpha_config.bg_global_alpha_value = 0xff;
1543	1667	}
	1668	+
	1669	+ req->alpha_config.mode = req_rga->PD_mode;
1544	1670	}
1545	1671	}
1546	1672
..	..	@@ -1589,54 +1715,39 @@
1589	1715	}
1590	1716	}
1591	1717
1592		-void rga3_soft_reset(struct rga_scheduler_t *scheduler)
	1718	+static void rga3_soft_reset(struct rga_scheduler_t *scheduler)
1593	1719	{
1594	1720	u32 i;
1595		- u32 reg;
1596		- u32 mmu_addr;
	1721	+ u32 iommu_dte_addr = 0;
1597	1722
1598		- mmu_addr = rga_read(0xf00, scheduler);
	1723	+ if (scheduler->data->mmu == RGA_IOMMU)
	1724	+ iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
1599	1725
1600		- rga_write((1 << 3) \| (1 << 4), RGA3_SYS_CTRL, scheduler);
1601		-
1602		- pr_err("soft reset sys_ctrl = %x, ro_rest = %x",
1603		- rga_read(RGA3_SYS_CTRL, scheduler),
1604		- rga_read(RGA3_RO_SRST, scheduler));
1605		-
1606		- mdelay(20);
1607		-
1608		- pr_err("soft reset sys_ctrl = %x, ro_rest = %x",
1609		- rga_read(RGA3_SYS_CTRL, scheduler),
1610		- rga_read(RGA3_RO_SRST, scheduler));
1611		-
1612		- rga_write((0 << 3) \| (0 << 4), RGA3_SYS_CTRL, scheduler);
1613		-
1614		- pr_err("soft after reset sys_ctrl = %x, ro_rest = %x",
1615		- rga_read(RGA3_SYS_CTRL, scheduler),
1616		- rga_read(RGA3_RO_SRST, scheduler));
1617		-
1618		- rga_write(1, RGA3_INT_CLR, scheduler);
1619		-
1620		- rga_write(mmu_addr, 0xf00, scheduler);
1621		- rga_write(0, 0xf08, scheduler);
1622		-
1623		- if (DEBUGGER_EN(INT_FLAG))
1624		- pr_info("irq INT[%x], STATS0[%x], STATS1[%x]\n",
1625		- rga_read(RGA3_INT_RAW, scheduler),
1626		- rga_read(RGA3_STATUS0, scheduler),
1627		- rga_read(RGA3_STATUS1, scheduler));
	1726	+ rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(1) \| s_RGA3_SYS_CTRL_ACLK_SRESET(1),
	1727	+ RGA3_SYS_CTRL, scheduler);
1628	1728
1629	1729	for (i = 0; i < RGA_RESET_TIMEOUT; i++) {
1630		- reg = rga_read(RGA3_SYS_CTRL, scheduler) & 1;
1631		-
1632		- if (reg == 0)
	1730	+ if (rga_read(RGA3_RO_SRST, scheduler) & m_RGA3_RO_SRST_RO_RST_DONE)
1633	1731	break;
1634	1732
1635	1733	udelay(1);
1636	1734	}
1637	1735
	1736	+ rga_write(s_RGA3_SYS_CTRL_CCLK_SRESET(0) \| s_RGA3_SYS_CTRL_ACLK_SRESET(0),
	1737	+ RGA3_SYS_CTRL, scheduler);
	1738	+
	1739	+ if (scheduler->data->mmu == RGA_IOMMU) {
	1740	+ rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
	1741	+ /* enable iommu */
	1742	+ rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
	1743	+ }
	1744	+
1638	1745	if (i == RGA_RESET_TIMEOUT)
1639		- pr_err("soft reset timeout.\n");
	1746	+ pr_err("RGA3 core[%d] soft reset timeout. SYS_CTRL[0x%x], RO_SRST[0x%x]\n",
	1747	+ scheduler->core, rga_read(RGA3_SYS_CTRL, scheduler),
	1748	+ rga_read(RGA3_RO_SRST, scheduler));
	1749	+ else
	1750	+ pr_info("RGA3 core[%d] soft reset complete.\n", scheduler->core);
1640	1751	}
1641	1752
1642	1753	static int rga3_scale_check(const struct rga3_req *req)
..	..	@@ -1803,11 +1914,14 @@
1803	1914	pr_info("mmu: win0 = %.2x win1 = %.2x wr = %.2x\n",
1804	1915	req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,
1805	1916	req->mmu_info.dst_mmu_flag);
1806		- pr_info("alpha: flag %x mode0=%x mode1=%x\n", req->alpha_rop_flag,
1807		- req->alpha_mode_0, req->alpha_mode_1);
1808		- pr_info("blend mode is %s\n",
1809		- rga_get_blend_mode_str(req->alpha_rop_flag, req->alpha_mode_0,
1810		- req->alpha_mode_1));
	1917	+ pr_info("alpha: flag %x mode=%s\n",
	1918	+ req->alpha_rop_flag, rga_get_blend_mode_str(req->alpha_config.mode));
	1919	+ pr_info("alpha: pre_multi=[%d,%d] pixl=[%d,%d] glb=[%d,%d]\n",
	1920	+ req->alpha_config.fg_pre_multiplied, req->alpha_config.bg_pre_multiplied,
	1921	+ req->alpha_config.fg_pixel_alpha_en, req->alpha_config.bg_pixel_alpha_en,
	1922	+ req->alpha_config.fg_global_alpha_en, req->alpha_config.bg_global_alpha_en);
	1923	+ pr_info("alpha: fg_global_alpha=%x bg_global_alpha=%x\n",
	1924	+ req->alpha_config.fg_global_alpha_value, req->alpha_config.bg_global_alpha_value);
1811	1925	pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
1812	1926	}
1813	1927
..	..	@@ -1836,11 +1950,12 @@
1836	1950	return 0;
1837	1951	}
1838	1952
1839		-int rga3_init_reg(struct rga_job *job)
	1953	+static int rga3_init_reg(struct rga_job *job)
1840	1954	{
1841	1955	struct rga3_req req;
1842	1956	int ret = 0;
1843	1957	struct rga_scheduler_t *scheduler = NULL;
	1958	+ ktime_t timestamp = ktime_get();
1844	1959
1845	1960	scheduler = job->scheduler;
1846	1961	if (unlikely(scheduler == NULL)) {
..	..	@@ -1870,6 +1985,10 @@
1870	1985	return -EINVAL;
1871	1986	}
1872	1987
	1988	+ if (DEBUGGER_EN(TIME))
	1989	+ pr_info("request[%d], generate register cost time %lld us\n",
	1990	+ job->request_id, ktime_us_delta(ktime_get(), timestamp));
	1991	+
1873	1992	return ret;
1874	1993	}
1875	1994
..	..	@@ -1893,29 +2012,24 @@
1893	2012	cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
1894	2013	}
1895	2014
1896		-int rga3_set_reg(struct rga_job job, struct rga_scheduler_t scheduler)
	2015	+static int rga3_set_reg(struct rga_job job, struct rga_scheduler_t scheduler)
1897	2016	{
	2017	+ int i;
	2018	+ bool master_mode_en;
	2019	+ uint32_t sys_ctrl;
1898	2020	ktime_t now = ktime_get();
1899	2021
1900		- //rga_dma_flush_range(&job->cmd_reg[0], &job->cmd_reg[50], scheduler);
1901		-
1902		- rga_write(0x0, RGA3_SYS_CTRL, scheduler);
1903		-
1904		-#if 0
1905		- /* CMD buff */
1906		- rga_write(virt_to_phys(job->cmd_reg), RGA3_CMD_ADDR, scheduler);
1907		-#else
1908		- {
1909		- int32_t m, *cmd;
1910		-
1911		- cmd = job->cmd_reg;
1912		- for (m = 0; m <= 50; m++)
1913		- rga_write(cmd[m], 0x100 + m * 4, scheduler);
1914		- }
1915		-#endif
	2022	+ /*
	2023	+ * Currently there is no iova allocated for storing cmd for the IOMMU device,
	2024	+ * so the iommu device needs to use the slave mode.
	2025	+ */
	2026	+ if (scheduler->data->mmu != RGA_IOMMU)
	2027	+ master_mode_en = true;
	2028	+ else
	2029	+ master_mode_en = false;
1916	2030
1917	2031	if (DEBUGGER_EN(REG)) {
1918		- int32_t i, *p;
	2032	+ uint32_t *p;
1919	2033
1920	2034	p = job->cmd_reg;
1921	2035	pr_info("CMD_REG\n");
..	..	@@ -1925,36 +2039,47 @@
1925	2039	p[2 + i * 4], p[3 + i * 4]);
1926	2040	}
1927	2041
1928		-#if 0
1929		- /* master mode */
1930		- rga_write((0x1 << 1) \| (0x1 << 2) \| (0x1 << 5) \| (0x1 << 6),
1931		- RGA3_SYS_CTRL, scheduler);
1932		-#else
1933		- /* slave mode */
1934		- //rga_write(1, 0xf08, scheduler);
1935		-#endif
1936		-
1937	2042	/* All CMD finish int */
1938		- rga_write(1, RGA3_INT_EN, scheduler);
	2043	+ rga_write(m_RGA3_INT_FRM_DONE \| m_RGA3_INT_CMD_LINE_FINISH \| m_RGA3_INT_ERROR_MASK,
	2044	+ RGA3_INT_EN, scheduler);
1939	2045
1940		- if (DEBUGGER_EN(MSG)) {
1941		- pr_info("sys_ctrl = %x, int_en = %x, int_raw = %x\n",
	2046	+ if (master_mode_en) {
	2047	+ /* master mode */
	2048	+ sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(1);
	2049	+
	2050	+ /* cmd buffer flush cache to ddr */
	2051	+ rga_dma_sync_flush_range(&job->cmd_reg[0], &job->cmd_reg[50], scheduler);
	2052	+
	2053	+ rga_write(virt_to_phys(job->cmd_reg), RGA3_CMD_ADDR, scheduler);
	2054	+ rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
	2055	+ rga_write(m_RGA3_CMD_CTRL_CMD_LINE_ST_P, RGA3_CMD_CTRL, scheduler);
	2056	+ } else {
	2057	+ /* slave mode */
	2058	+ sys_ctrl = s_RGA3_SYS_CTRL_CMD_MODE(0) \| m_RGA3_SYS_CTRL_RGA_SART;
	2059	+
	2060	+ for (i = 0; i <= 50; i++)
	2061	+ rga_write(job->cmd_reg[i], 0x100 + i * 4, scheduler);
	2062	+
	2063	+ rga_write(sys_ctrl, RGA3_SYS_CTRL, scheduler);
	2064	+ }
	2065	+
	2066	+ if (DEBUGGER_EN(REG)) {
	2067	+ pr_info("sys_ctrl = 0x%x, int_en = 0x%x, int_raw = 0x%x\n",
1942	2068	rga_read(RGA3_SYS_CTRL, scheduler),
1943	2069	rga_read(RGA3_INT_EN, scheduler),
1944	2070	rga_read(RGA3_INT_RAW, scheduler));
1945	2071
1946		- pr_info("status0 = %x, status1 = %x\n",
	2072	+ pr_info("hw_status = 0x%x, cmd_status = 0x%x\n",
1947	2073	rga_read(RGA3_STATUS0, scheduler),
1948		- rga_read(RGA3_STATUS1, scheduler));
	2074	+ rga_read(RGA3_CMD_STATE, scheduler));
1949	2075	}
1950	2076
1951	2077	if (DEBUGGER_EN(TIME))
1952		- pr_info("set cmd use time = %lld\n", ktime_us_delta(now, job->timestamp));
	2078	+ pr_info("request[%d], set register cost time %lld us\n",
	2079	+ job->request_id, ktime_us_delta(now, job->timestamp));
1953	2080
1954	2081	job->hw_running_time = now;
1955	2082	job->hw_recoder_time = now;
1956		-
1957		- rga_write(1, RGA3_SYS_CTRL, scheduler);
1958	2083
1959	2084	if (DEBUGGER_EN(REG))
1960	2085	rga3_dump_read_back_reg(scheduler);
..	..	@@ -1962,7 +2087,7 @@
1962	2087	return 0;
1963	2088	}
1964	2089
1965		-int rga3_get_version(struct rga_scheduler_t *scheduler)
	2090	+static int rga3_get_version(struct rga_scheduler_t *scheduler)
1966	2091	{
1967	2092	u32 major_version, minor_version, svn_version;
1968	2093	u32 reg_version;
..	..	@@ -1987,3 +2112,80 @@
1987	2112
1988	2113	return 0;
1989	2114	}
	2115	+
	2116	+static int rga3_irq(struct rga_scheduler_t *scheduler)
	2117	+{
	2118	+ struct rga_job *job = scheduler->running_job;
	2119	+
	2120	+ if (job == NULL)
	2121	+ return IRQ_HANDLED;
	2122	+
	2123	+ if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state))
	2124	+ return IRQ_WAKE_THREAD;
	2125	+
	2126	+ job->intr_status = rga_read(RGA3_INT_RAW, scheduler);
	2127	+ job->hw_status = rga_read(RGA3_STATUS0, scheduler);
	2128	+ job->cmd_status = rga_read(RGA3_CMD_STATE, scheduler);
	2129	+
	2130	+ if (DEBUGGER_EN(INT_FLAG))
	2131	+ pr_info("irq handler, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
	2132	+ job->intr_status, job->hw_status, job->cmd_status);
	2133	+
	2134	+ if (job->intr_status & (m_RGA3_INT_FRM_DONE \| m_RGA3_INT_CMD_LINE_FINISH)) {
	2135	+ set_bit(RGA_JOB_STATE_FINISH, &job->state);
	2136	+ } else if (job->intr_status & m_RGA3_INT_ERROR_MASK) {
	2137	+ set_bit(RGA_JOB_STATE_INTR_ERR, &job->state);
	2138	+
	2139	+ pr_err("irq handler err! INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
	2140	+ job->intr_status, job->hw_status, job->cmd_status);
	2141	+ scheduler->ops->soft_reset(scheduler);
	2142	+ }
	2143	+
	2144	+ /clear INTR /
	2145	+ rga_write(m_RGA3_INT_FRM_DONE \| m_RGA3_INT_CMD_LINE_FINISH \| m_RGA3_INT_ERROR_MASK,
	2146	+ RGA3_INT_CLR, scheduler);
	2147	+
	2148	+ return IRQ_WAKE_THREAD;
	2149	+}
	2150	+
	2151	+static int rga3_isr_thread(struct rga_job job, struct rga_scheduler_t scheduler)
	2152	+{
	2153	+ if (DEBUGGER_EN(INT_FLAG))
	2154	+ pr_info("isr thread, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
	2155	+ rga_read(RGA3_INT_RAW, scheduler),
	2156	+ rga_read(RGA3_STATUS0, scheduler),
	2157	+ rga_read(RGA3_CMD_STATE, scheduler));
	2158	+
	2159	+ if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state)) {
	2160	+ if (job->intr_status & m_RGA3_INT_RAG_MI_RD_BUS_ERR) {
	2161	+ pr_err("DMA read bus error, please check size of the input_buffer or whether the buffer has been freed.\n");
	2162	+ job->ret = -EFAULT;
	2163	+ } else if (job->intr_status & m_RGA3_INT_WIN0_FBCD_DEC_ERR) {
	2164	+ pr_err("win0 FBC decoder error, please check the fbc image of the source.\n");
	2165	+ job->ret = -EFAULT;
	2166	+ } else if (job->intr_status & m_RGA3_INT_WIN1_FBCD_DEC_ERR) {
	2167	+ pr_err("win1 FBC decoder error, please check the fbc image of the source.\n");
	2168	+ job->ret = -EFAULT;
	2169	+ } else if (job->intr_status & m_RGA3_INT_RGA_MI_WR_BUS_ERR) {
	2170	+ pr_err("wr buss error, please check size of the output_buffer or whether the buffer has been freed.\n");
	2171	+ job->ret = -EFAULT;
	2172	+ }
	2173	+
	2174	+ if (job->ret == 0) {
	2175	+ pr_err("rga intr error[0x%x]!\n", job->intr_status);
	2176	+ job->ret = -EFAULT;
	2177	+ }
	2178	+ }
	2179	+
	2180	+ return IRQ_HANDLED;
	2181	+}
	2182	+
	2183	+const struct rga_backend_ops rga3_ops = {
	2184	+ .get_version = rga3_get_version,
	2185	+ .set_reg = rga3_set_reg,
	2186	+ .init_reg = rga3_init_reg,
	2187	+ .soft_reset = rga3_soft_reset,
	2188	+ .read_back_reg = NULL,
	2189	+ .irq = rga3_irq,
	2190	+ .isr_thread = rga3_isr_thread,
	2191	+};