forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/video/rockchip/rga3/rga2_reg_info.c
....@@ -7,7 +7,6 @@
77 
88 #define pr_fmt(fmt) "rga2_reg: " fmt
99 
10
-#include "rga_job.h"
1110 #include "rga2_reg_info.h"
1211 #include "rga_dma_buf.h"
1312 #include "rga_iommu.h"
....@@ -165,12 +164,8 @@
165164 
166165 	bRGA_MODE_CTL = (u32 *) (base + RGA2_MODE_CTRL_OFFSET);
167166 
168
-	if (msg->render_mode == 4)
169
-		render_mode = 3;
170
-
171
-	/* In slave mode, the current frame completion interrupt must be enabled. */
172
-	if (!RGA2_USE_MASTER_MODE)
173
-		msg->CMD_fin_int_enable = 1;
167
+	if (msg->render_mode == UPDATE_PALETTE_TABLE_MODE)
168
+		render_mode = 0x3;
174169 
175170 	reg =
176171 		((reg & (~m_RGA2_MODE_CTRL_SW_RENDER_MODE)) |
....@@ -231,6 +226,7 @@
231226 	u32 sw, sh;
232227 	u32 dw, dh;
233228 	u8 rotate_mode;
229
+	u8 vsp_scale_mode = 0;
234230 	u8 scale_w_flag, scale_h_flag;
235231 
236232 	bRGA_SRC_INFO = (u32 *) (base + RGA2_SRC_INFO_OFFSET);
....@@ -292,6 +288,18 @@
292288 		/* uvvds need to force tile mode. */
293289 		if (msg->uvvds_mode && scale_w_flag == 0)
294290 			scale_w_flag = 3;
291
+	}
292
+
293
+	/* VSP scale mode select, HSD > VSD > VSP > HSP */
294
+	if (scale_h_flag == 0x2) {
295
+		/* After HSD, VSP needs to check dst_width */
296
+		if ((scale_w_flag == 0x1) && (dw < RGA2_VSP_BICUBIC_LIMIT))
297
+			vsp_scale_mode = 0x0;
298
+		else if (sw < RGA2_VSP_BICUBIC_LIMIT)
299
+			vsp_scale_mode = 0x0;
300
+		else
301
+			/* default select bilinear */
302
+			vsp_scale_mode = 0x1;
295303 	}
296304 
297305 	switch (msg->src.format) {
....@@ -564,8 +572,7 @@
564572 		 ((msg->alpha_rop_flag >> 4) & 0x1)));
565573 	reg =
566574 		((reg & (~m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL)) |
567
-		 (s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL((
568
-			 msg->scale_bicu_mode >> 4))));
575
+		 (s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL((vsp_scale_mode))));
569576 	reg =
570577 		((reg & (~m_RGA2_SRC_INFO_SW_SW_YUV10_E)) |
571578 		 (s_RGA2_SRC_INFO_SW_SW_YUV10_E((yuv10))));
....@@ -1270,104 +1277,253 @@
12701277 	u32 *bRGA_ALPHA_CTRL0;
12711278 	u32 *bRGA_ALPHA_CTRL1;
12721279 	u32 *bRGA_FADING_CTRL;
1273
-	u32 reg0 = 0;
1274
-	u32 reg1 = 0;
1280
+	u32 reg = 0;
1281
+	union rga2_color_ctrl color_ctrl;
1282
+	union rga2_alpha_ctrl alpha_ctrl;
1283
+	struct rga_alpha_config *config;
12751284 
12761285 	bRGA_ALPHA_CTRL0 = (u32 *) (base + RGA2_ALPHA_CTRL0_OFFSET);
12771286 	bRGA_ALPHA_CTRL1 = (u32 *) (base + RGA2_ALPHA_CTRL1_OFFSET);
12781287 	bRGA_FADING_CTRL = (u32 *) (base + RGA2_FADING_CTRL_OFFSET);
12791288 
1280
-	reg0 =
1281
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) |
1289
+	color_ctrl.value = 0;
1290
+	alpha_ctrl.value = 0;
1291
+	config = &msg->alpha_config;
1292
+
1293
+	color_ctrl.bits.src_color_mode =
1294
+		config->fg_pre_multiplied ? RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
1295
+	color_ctrl.bits.dst_color_mode =
1296
+		config->bg_pre_multiplied ? RGA_ALPHA_PRE_MULTIPLIED : RGA_ALPHA_NO_PRE_MULTIPLIED;
1297
+
1298
+	if (config->fg_pixel_alpha_en)
1299
+		color_ctrl.bits.src_blend_mode =
1300
+			config->fg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
1301
+			RGA_ALPHA_PER_PIXEL;
1302
+	else
1303
+		color_ctrl.bits.src_blend_mode = RGA_ALPHA_GLOBAL;
1304
+
1305
+	if (config->bg_pixel_alpha_en)
1306
+		color_ctrl.bits.dst_blend_mode =
1307
+			config->bg_global_alpha_en ? RGA_ALPHA_PER_PIXEL_GLOBAL :
1308
+			RGA_ALPHA_PER_PIXEL;
1309
+	else
1310
+		color_ctrl.bits.dst_blend_mode = RGA_ALPHA_GLOBAL;
1311
+
1312
+	/*
1313
+	 * Since the hardware uses 256 as 1, the original alpha value needs to
1314
+	 * be + (alpha >> 7).
1315
+	 */
1316
+	color_ctrl.bits.src_alpha_cal_mode = RGA_ALPHA_SATURATION;
1317
+	color_ctrl.bits.dst_alpha_cal_mode = RGA_ALPHA_SATURATION;
1318
+
1319
+	/* porter duff alpha enable */
1320
+	switch (config->mode) {
1321
+	case RGA_ALPHA_BLEND_SRC:
1322
+		/*
1323
+		 * SRC mode:
1324
+		 *	Sf = 1, Df = 0；
1325
+		 *	[Rc,Ra] = [Sc,Sa]；
1326
+		 */
1327
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1328
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ONE;
1329
+
1330
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1331
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1332
+
1333
+		break;
1334
+
1335
+	case RGA_ALPHA_BLEND_DST:
1336
+		/*
1337
+		 * SRC mode:
1338
+		 *	Sf = 0, Df = 1；
1339
+		 *	[Rc,Ra] = [Dc,Da]；
1340
+		 */
1341
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1342
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1343
+
1344
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1345
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ONE;
1346
+
1347
+		break;
1348
+
1349
+	case RGA_ALPHA_BLEND_SRC_OVER:
1350
+		/*
1351
+		 * SRC-OVER mode:
1352
+		 *	Sf = 1, Df = (1 - Sa)
1353
+		 *	[Rc,Ra] = [ Sc + (1 - Sa) * Dc, Sa + (1 - Sa) * Da ]
1354
+		 */
1355
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1356
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ONE;
1357
+
1358
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1359
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1360
+
1361
+		break;
1362
+
1363
+	case RGA_ALPHA_BLEND_DST_OVER:
1364
+		/*
1365
+		 * DST-OVER mode:
1366
+		 *	Sf = (1 - Da) , Df = 1
1367
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc, Sa * (1 - Da) + Da ]
1368
+		 */
1369
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1370
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1371
+
1372
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1373
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ONE;
1374
+
1375
+		break;
1376
+
1377
+	case RGA_ALPHA_BLEND_SRC_IN:
1378
+		/*
1379
+		 * SRC-IN mode:
1380
+		 *	Sf = Da , Df = 0
1381
+		 *	[Rc,Ra] = [ Sc * Da, Sa * Da ]
1382
+		 */
1383
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1384
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE;
1385
+
1386
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1387
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1388
+
1389
+		break;
1390
+
1391
+	case RGA_ALPHA_BLEND_DST_IN:
1392
+		/*
1393
+		 * DST-IN mode:
1394
+		 *	Sf = 0 , Df = Sa
1395
+		 *	[Rc,Ra] = [ Dc * Sa, Da * Sa ]
1396
+		 */
1397
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1398
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1399
+
1400
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1401
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE;
1402
+
1403
+		break;
1404
+
1405
+	case RGA_ALPHA_BLEND_SRC_OUT:
1406
+		/*
1407
+		 * SRC-OUT mode:
1408
+		 *	Sf = (1 - Da) , Df = 0
1409
+		 *	[Rc,Ra] = [ Sc * (1 - Da), Sa * (1 - Da) ]
1410
+		 */
1411
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1412
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1413
+
1414
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1415
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1416
+
1417
+		break;
1418
+
1419
+	case RGA_ALPHA_BLEND_DST_OUT:
1420
+		/*
1421
+		 * DST-OUT mode:
1422
+		 *	Sf = 0 , Df = (1 - Sa)
1423
+		 *	[Rc,Ra] = [ Dc * (1 - Sa), Da * (1 - Sa) ]
1424
+		 */
1425
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1426
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1427
+
1428
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1429
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1430
+
1431
+		break;
1432
+
1433
+	case RGA_ALPHA_BLEND_SRC_ATOP:
1434
+		/*
1435
+		 * SRC-ATOP mode:
1436
+		 *	Sf = Da , Df = (1 - Sa)
1437
+		 *	[Rc,Ra] = [ Sc * Da + Dc * (1 - Sa), Sa * Da + Da * (1 - Sa) ]
1438
+		 */
1439
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1440
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE;
1441
+
1442
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1443
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1444
+
1445
+		break;
1446
+
1447
+	case RGA_ALPHA_BLEND_DST_ATOP:
1448
+		/*
1449
+		 * DST-ATOP mode:
1450
+		 *	Sf = (1 - Da) , Df = Sa
1451
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc * Sa, Sa * (1 - Da) + Da * Sa ]
1452
+		 */
1453
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1454
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1455
+
1456
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1457
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE;
1458
+
1459
+		break;
1460
+
1461
+	case RGA_ALPHA_BLEND_XOR:
1462
+		/*
1463
+		 * DST-XOR mode:
1464
+		 *	Sf = (1 - Da) , Df = (1 - Sa)
1465
+		 *	[Rc,Ra] = [ Sc * (1 - Da) + Dc * (1 - Sa), Sa * (1 - Da) + Da * (1 - Sa) ]
1466
+		 */
1467
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1468
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1469
+
1470
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1471
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_OPPOSITE_INVERSE;
1472
+
1473
+		break;
1474
+
1475
+	case RGA_ALPHA_BLEND_CLEAR:
1476
+		/*
1477
+		 * DST-CLEAR mode:
1478
+		 *	Sf = 0 , Df = 0
1479
+		 *	[Rc,Ra] = [ 0, 0 ]
1480
+		 */
1481
+		color_ctrl.bits.src_alpha_mode = RGA_ALPHA_STRAIGHT;
1482
+		color_ctrl.bits.src_factor_mode = RGA_ALPHA_ZERO;
1483
+
1484
+		color_ctrl.bits.dst_alpha_mode = RGA_ALPHA_STRAIGHT;
1485
+		color_ctrl.bits.dst_factor_mode = RGA_ALPHA_ZERO;
1486
+
1487
+		break;
1488
+
1489
+	default:
1490
+		break;
1491
+	}
1492
+
1493
+	alpha_ctrl.bits.src_blend_mode = color_ctrl.bits.src_blend_mode;
1494
+	alpha_ctrl.bits.dst_blend_mode = color_ctrl.bits.dst_blend_mode;
1495
+
1496
+	alpha_ctrl.bits.src_alpha_cal_mode = color_ctrl.bits.src_alpha_cal_mode;
1497
+	alpha_ctrl.bits.dst_alpha_cal_mode = color_ctrl.bits.dst_alpha_cal_mode;
1498
+
1499
+	alpha_ctrl.bits.src_alpha_mode = color_ctrl.bits.src_alpha_mode;
1500
+	alpha_ctrl.bits.src_factor_mode = color_ctrl.bits.src_factor_mode;
1501
+
1502
+	alpha_ctrl.bits.dst_alpha_mode = color_ctrl.bits.dst_alpha_mode;
1503
+	alpha_ctrl.bits.dst_factor_mode = color_ctrl.bits.dst_factor_mode;
1504
+
1505
+	reg =
1506
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0)) |
12821507 		 (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(msg->alpha_rop_flag)));
1283
-	reg0 =
1284
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) |
1508
+	reg =
1509
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL)) |
12851510 		 (s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL
12861511 		 (msg->alpha_rop_flag >> 1)));
1287
-	reg0 =
1288
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) |
1512
+	reg =
1513
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_ROP_MODE)) |
12891514 		 (s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(msg->rop_mode)));
1290
-	reg0 =
1291
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) |
1515
+	reg =
1516
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA)) |
12921517 		 (s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA
1293
-		 (msg->src_a_global_val)));
1294
-	reg0 =
1295
-		((reg0 & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) |
1518
+		 ((uint8_t)config->fg_global_alpha_value)));
1519
+	reg =
1520
+		((reg & (~m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA)) |
12961521 		 (s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA
1297
-		 (msg->dst_a_global_val)));
1522
+		 ((uint8_t)config->bg_global_alpha_value)));
12981523 
1299
-	reg1 =
1300
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0)) |
1301
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0
1302
-		 (msg->alpha_mode_0 >> 15)));
1303
-	reg1 =
1304
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0)) |
1305
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0
1306
-		 (msg->alpha_mode_0 >> 7)));
1307
-	reg1 =
1308
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0)) |
1309
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0
1310
-		 (msg->alpha_mode_0 >> 12)));
1311
-	reg1 =
1312
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0)) |
1313
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0
1314
-		 (msg->alpha_mode_0 >> 4)));
1315
-	reg1 =
1316
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0)) |
1317
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0
1318
-		 (msg->alpha_mode_0 >> 11)));
1319
-	reg1 =
1320
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0)) |
1321
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0
1322
-		 (msg->alpha_mode_0 >> 3)));
1323
-	reg1 =
1324
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0)) |
1325
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0
1326
-		 (msg->alpha_mode_0 >> 9)));
1327
-	reg1 =
1328
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0)) |
1329
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0
1330
-		 (msg->alpha_mode_0 >> 1)));
1331
-	reg1 =
1332
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0)) |
1333
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0
1334
-		 (msg->alpha_mode_0 >> 8)));
1335
-	reg1 =
1336
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0)) |
1337
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0
1338
-		 (msg->alpha_mode_0 >> 0)));
1524
+	*bRGA_ALPHA_CTRL0 = reg;
1525
+	*bRGA_ALPHA_CTRL1 = color_ctrl.value | (alpha_ctrl.value << 16);
13391526 
1340
-	reg1 =
1341
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1)) |
1342
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1
1343
-		 (msg->alpha_mode_1 >> 12)));
1344
-	reg1 =
1345
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1)) |
1346
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1
1347
-		 (msg->alpha_mode_1 >> 4)));
1348
-	reg1 =
1349
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1)) |
1350
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1
1351
-		 (msg->alpha_mode_1 >> 11)));
1352
-	reg1 =
1353
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1)) |
1354
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1
1355
-		 (msg->alpha_mode_1 >> 3)));
1356
-	reg1 =
1357
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1)) |
1358
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(msg->alpha_mode_1 >> 9)));
1359
-	reg1 =
1360
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1)) |
1361
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(msg->alpha_mode_1 >> 1)));
1362
-	reg1 =
1363
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1)) |
1364
-		 (s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(msg->alpha_mode_1 >> 8)));
1365
-	reg1 =
1366
-		((reg1 & (~m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1)) |
1367
-		 (s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(msg->alpha_mode_1 >> 0)));
1368
-
1369
-	*bRGA_ALPHA_CTRL0 = reg0;
1370
-	*bRGA_ALPHA_CTRL1 = reg1;
13711527 
13721528 	if ((msg->alpha_rop_flag >> 2) & 1) {
13731529 		*bRGA_FADING_CTRL = (1 << 24) | (msg->fading_b_value << 16) |
....@@ -1715,7 +1871,7 @@
17151871 	*bRGA_MMU_ELS_BASE = (u32) (msg->mmu_info.els_base_addr) >> 4;
17161872 }
17171873 
1718
-int rga2_gen_reg_info(u8 *base, struct rga2_req *msg)
1874
+static int rga2_gen_reg_info(u8 *base, struct rga2_req *msg)
17191875 {
17201876 	u8 dst_nn_quantize_en = 0;
17211877 
....@@ -1769,8 +1925,6 @@
17691925 static void rga_cmd_to_rga2_cmd(struct rga_scheduler_t *scheduler,
17701926 				struct rga_req *req_rga, struct rga2_req *req)
17711927 {
1772
-	u16 alpha_mode_0, alpha_mode_1;
1773
-
17741928 	if (req_rga->render_mode == 6)
17751929 		req->render_mode = UPDATE_PALETTE_TABLE_MODE;
17761930 	else if (req_rga->render_mode == 7)
....@@ -1848,9 +2002,6 @@
18482002 		break;
18492003 	}
18502004 
1851
-	if ((req->dst.act_w > 2048) && (req->src.act_h < req->dst.act_h))
1852
-		req->scale_bicu_mode |= (1 << 4);
1853
-
18542005 	req->LUT_addr = req_rga->LUT_addr;
18552006 	req->rop_mask_addr = req_rga->rop_mask_addr;
18562007 
....@@ -1873,6 +2024,8 @@
18732024 
18742025 	req->palette_mode = req_rga->palette_mode;
18752026 	req->yuv2rgb_mode = req_rga->yuv2rgb_mode;
2027
+	if (req_rga->full_csc.flag & 0x1)
2028
+		req->full_csc_en = 1;
18762029 	req->endian_mode = req_rga->endian_mode;
18772030 	req->rgb2yuv_mode = 0;
18782031 
....@@ -1914,110 +2067,52 @@
19142067 
19152068 	if (((req_rga->alpha_rop_flag) & 1)) {
19162069 		if ((req_rga->alpha_rop_flag >> 3) & 1) {
1917
-			/* porter duff alpha enable */
1918
-			switch (req_rga->PD_mode) {
1919
-			/* dst = 0 */
1920
-			case 0:
1921
-				break;
1922
-			/* dst = src */
1923
-			case 1:
1924
-				req->alpha_mode_0 = 0x0212;
1925
-				req->alpha_mode_1 = 0x0212;
1926
-				break;
1927
-			/* dst = dst */
1928
-			case 2:
1929
-				req->alpha_mode_0 = 0x1202;
1930
-				req->alpha_mode_1 = 0x1202;
1931
-				break;
1932
-			/* dst = (256*sc + (256 - sa)*dc) >> 8 */
1933
-			case 3:
1934
-				if ((req_rga->alpha_rop_mode & 3) == 0) {
1935
-					/* both use globalAlpha. */
1936
-					alpha_mode_0 = 0x3010;
1937
-					alpha_mode_1 = 0x3010;
1938
-				} else if ((req_rga->alpha_rop_mode & 3) == 1) {
1939
-					/* Do not use globalAlpha. */
1940
-					alpha_mode_0 = 0x3212;
1941
-					alpha_mode_1 = 0x3212;
1942
-				} else if ((req_rga->alpha_rop_mode & 3) == 2) {
1943
-					/*
1944
-					 * dst use globalAlpha,
1945
-					 * and dst has pixelAlpha.
1946
-					 */
1947
-					alpha_mode_0 = 0x3014;
1948
-					alpha_mode_1 = 0x3014;
1949
-				} else {
1950
-					/*
1951
-					 * dst use globalAlpha, and
1952
-					 * dst does not have pixelAlpha.
1953
-					 */
1954
-					alpha_mode_0 = 0x3012;
1955
-					alpha_mode_1 = 0x3012;
1956
-				}
1957
-				req->alpha_mode_0 = alpha_mode_0;
1958
-				req->alpha_mode_1 = alpha_mode_1;
1959
-				break;
1960
-			/* dst = (sc*(256-da) + 256*dc) >> 8 */
1961
-			case 4:
1962
-				/* Do not use globalAlpha. */
1963
-				req->alpha_mode_0 = 0x1232;
1964
-				req->alpha_mode_1 = 0x1232;
1965
-				break;
1966
-			/* dst = (da*sc) >> 8 */
1967
-			case 5:
1968
-				break;
1969
-			/* dst = (sa*dc) >> 8 */
1970
-			case 6:
1971
-				break;
1972
-			/* dst = ((256-da)*sc) >> 8 */
1973
-			case 7:
1974
-				break;
1975
-			/* dst = ((256-sa)*dc) >> 8 */
1976
-			case 8:
1977
-				break;
1978
-			/* dst = (da*sc + (256-sa)*dc) >> 8 */
1979
-			case 9:
1980
-				req->alpha_mode_0 = 0x3040;
1981
-				req->alpha_mode_1 = 0x3040;
1982
-				break;
1983
-			/* dst = ((256-da)*sc + (sa*dc)) >> 8 */
1984
-			case 10:
1985
-				break;
1986
-			/* dst = ((256-da)*sc + (256-sa)*dc) >> 8 */
1987
-			case 11:
1988
-				break;
1989
-			case 12:
1990
-				req->alpha_mode_0 = 0x0010;
1991
-				req->alpha_mode_1 = 0x0820;
1992
-				break;
1993
-			default:
1994
-				break;
1995
-			}
2070
+			req->alpha_config.enable = true;
19962071 
1997
-			if (req->osd_info.enable) {
1998
-				/* set dst(osd_block) real color mode */
1999
-				if (req->alpha_mode_0 & (0x01 << 9))
2000
-					req->alpha_mode_0 |= (1 << 15);
2001
-			}
2002
-
2003
-			/* Real color mode */
20042072 			if ((req_rga->alpha_rop_flag >> 9) & 1) {
2005
-				if (req->alpha_mode_0 & (0x01 << 1))
2006
-					req->alpha_mode_0 |= (1 << 7);
2007
-				if (req->alpha_mode_0 & (0x01 << 9))
2008
-					req->alpha_mode_0 |= (1 << 15);
2073
+				req->alpha_config.fg_pre_multiplied = false;
2074
+				req->alpha_config.bg_pre_multiplied = false;
2075
+			} else if (req->osd_info.enable) {
2076
+				req->alpha_config.fg_pre_multiplied = true;
2077
+				/* set dst(osd_block) real color mode */
2078
+				req->alpha_config.bg_pre_multiplied = false;
2079
+			} else {
2080
+				req->alpha_config.fg_pre_multiplied = true;
2081
+				req->alpha_config.bg_pre_multiplied = true;
20092082 			}
2010
-		} else {
2011
-			if ((req_rga->alpha_rop_mode & 3) == 0) {
2012
-				req->alpha_mode_0 = 0x3040;
2013
-				req->alpha_mode_1 = 0x3040;
2014
-			} else if ((req_rga->alpha_rop_mode & 3) == 1) {
2015
-				req->alpha_mode_0 = 0x3042;
2016
-				req->alpha_mode_1 = 0x3242;
2017
-			} else if ((req_rga->alpha_rop_mode & 3) == 2) {
2018
-				req->alpha_mode_0 = 0x3044;
2019
-				req->alpha_mode_1 = 0x3044;
2083
+
2084
+			req->alpha_config.fg_pixel_alpha_en = rga_is_alpha_format(req->src.format);
2085
+			if (req->bitblt_mode)
2086
+				req->alpha_config.bg_pixel_alpha_en =
2087
+					rga_is_alpha_format(req->src1.format);
2088
+			else
2089
+				req->alpha_config.bg_pixel_alpha_en =
2090
+					rga_is_alpha_format(req->dst.format);
2091
+
2092
+			if (req_rga->feature.global_alpha_en) {
2093
+				if (req_rga->fg_global_alpha < 0xff) {
2094
+					req->alpha_config.fg_global_alpha_en = true;
2095
+					req->alpha_config.fg_global_alpha_value =
2096
+						req_rga->fg_global_alpha;
2097
+				} else if (!req->alpha_config.fg_pixel_alpha_en) {
2098
+					req->alpha_config.fg_global_alpha_en = true;
2099
+					req->alpha_config.fg_global_alpha_value = 0xff;
2100
+				}
2101
+
2102
+				if (req_rga->bg_global_alpha < 0xff) {
2103
+					req->alpha_config.bg_global_alpha_en = true;
2104
+					req->alpha_config.bg_global_alpha_value =
2105
+						req_rga->bg_global_alpha;
2106
+				} else if (!req->alpha_config.bg_pixel_alpha_en) {
2107
+					req->alpha_config.bg_global_alpha_en = true;
2108
+					req->alpha_config.bg_global_alpha_value = 0xff;
2109
+				}
2110
+			} else {
2111
+				req->alpha_config.bg_global_alpha_value = 0xff;
2112
+				req->alpha_config.bg_global_alpha_value = 0xff;
20202113 			}
2114
+
2115
+			req->alpha_config.mode = req_rga->PD_mode;
20212116 		}
20222117 	}
20232118 
....@@ -2060,16 +2155,18 @@
20602155 	}
20612156 }
20622157 
2063
-void rga2_soft_reset(struct rga_scheduler_t *scheduler)
2158
+static void rga2_soft_reset(struct rga_scheduler_t *scheduler)
20642159 {
20652160 	u32 i;
20662161 	u32 reg;
2067
-	u32 iommu_dte_addr;
2162
+	u32 iommu_dte_addr = 0;
20682163 
20692164 	if (scheduler->data->mmu == RGA_IOMMU)
2070
-		iommu_dte_addr = rga_read(0xf00, scheduler);
2165
+		iommu_dte_addr = rga_read(RGA_IOMMU_DTE_ADDR, scheduler);
20712166 
2072
-	rga_write((1 << 3) | (1 << 4) | (1 << 6), RGA2_SYS_CTRL, scheduler);
2167
+	rga_write(m_RGA2_SYS_CTRL_ACLK_SRESET_P | m_RGA2_SYS_CTRL_CCLK_SRESET_P |
2168
+		  m_RGA2_SYS_CTRL_RST_PROTECT_P,
2169
+		  RGA2_SYS_CTRL, scheduler);
20732170 
20742171 	for (i = 0; i < RGA_RESET_TIMEOUT; i++) {
20752172 		/* RGA_SYS_CTRL */
....@@ -2082,13 +2179,16 @@
20822179 	}
20832180 
20842181 	if (scheduler->data->mmu == RGA_IOMMU) {
2085
-		rga_write(iommu_dte_addr, 0xf00, scheduler);
2182
+		rga_write(iommu_dte_addr, RGA_IOMMU_DTE_ADDR, scheduler);
20862183 		/* enable iommu */
2087
-		rga_write(0, 0xf08, scheduler);
2184
+		rga_write(RGA_IOMMU_CMD_ENABLE_PAGING, RGA_IOMMU_COMMAND, scheduler);
20882185 	}
20892186 
20902187 	if (i == RGA_RESET_TIMEOUT)
2091
-		pr_err("soft reset timeout.\n");
2188
+		pr_err("RAG2 core[%d] soft reset timeout.\n", scheduler->core);
2189
+	else
2190
+		pr_info("RGA2 core[%d] soft reset complete.\n", scheduler->core);
2191
+
20922192 }
20932193 
20942194 static int rga2_check_param(const struct rga_hw_data *data, const struct rga2_req *req)
....@@ -2207,19 +2307,23 @@
22072307 	pr_info("mmu: src=%.2x src1=%.2x dst=%.2x els=%.2x\n",
22082308 		req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,
22092309 		req->mmu_info.dst_mmu_flag, req->mmu_info.els_mmu_flag);
2210
-	pr_info("alpha: flag %x mode0=%x mode1=%x\n", req->alpha_rop_flag,
2211
-		req->alpha_mode_0, req->alpha_mode_1);
2212
-	pr_info("blend mode is %s\n",
2213
-		rga_get_blend_mode_str(req->alpha_rop_flag, req->alpha_mode_0,
2214
-					req->alpha_mode_1));
2310
+	pr_info("alpha: flag %x mode=%s\n",
2311
+		req->alpha_rop_flag, rga_get_blend_mode_str(req->alpha_config.mode));
2312
+	pr_info("alpha: pre_multi=[%d,%d] pixl=[%d,%d] glb=[%d,%d]\n",
2313
+		req->alpha_config.fg_pre_multiplied, req->alpha_config.bg_pre_multiplied,
2314
+		req->alpha_config.fg_pixel_alpha_en, req->alpha_config.bg_pixel_alpha_en,
2315
+		req->alpha_config.fg_global_alpha_en, req->alpha_config.bg_global_alpha_en);
2316
+	pr_info("alpha: fg_global_alpha=%x bg_global_alpha=%x\n",
2317
+		req->alpha_config.fg_global_alpha_value, req->alpha_config.bg_global_alpha_value);
22152318 	pr_info("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
22162319 }
22172320 
2218
-int rga2_init_reg(struct rga_job *job)
2321
+static int rga2_init_reg(struct rga_job *job)
22192322 {
22202323 	struct rga2_req req;
22212324 	int ret = 0;
22222325 	struct rga_scheduler_t *scheduler = NULL;
2326
+	ktime_t timestamp = ktime_get();
22232327 
22242328 	scheduler = job->scheduler;
22252329 	if (unlikely(scheduler == NULL)) {
....@@ -2230,7 +2334,24 @@
22302334 	memset(&req, 0x0, sizeof(req));
22312335 
22322336 	rga_cmd_to_rga2_cmd(scheduler, &job->rga_command_base, &req);
2233
-	memcpy(&job->full_csc, &job->rga_command_base.full_csc, sizeof(job->full_csc));
2337
+	if (req.full_csc_en) {
2338
+		memcpy(&job->full_csc, &job->rga_command_base.full_csc, sizeof(job->full_csc));
2339
+		if (job->rga_command_base.feature.full_csc_clip_en) {
2340
+			memcpy(&job->full_csc_clip, &job->rga_command_base.full_csc_clip,
2341
+			       sizeof(job->full_csc_clip));
2342
+		} else {
2343
+			job->full_csc_clip.y.max = 0xff;
2344
+			job->full_csc_clip.y.min = 0x0;
2345
+			job->full_csc_clip.uv.max = 0xff;
2346
+			job->full_csc_clip.uv.min = 0x0;
2347
+		}
2348
+
2349
+	} else {
2350
+		job->full_csc_clip.y.max = 0xff;
2351
+		job->full_csc_clip.y.min = 0x0;
2352
+		job->full_csc_clip.uv.max = 0xff;
2353
+		job->full_csc_clip.uv.min = 0x0;
2354
+	}
22342355 	memcpy(&job->pre_intr_info, &job->rga_command_base.pre_intr_info,
22352356 	       sizeof(job->pre_intr_info));
22362357 
....@@ -2267,10 +2388,18 @@
22672388 		}
22682389 	}
22692390 
2391
+	/* In slave mode, the current frame completion interrupt must be enabled. */
2392
+	if (scheduler->data->mmu == RGA_IOMMU)
2393
+		req.CMD_fin_int_enable = 1;
2394
+
22702395 	if (rga2_gen_reg_info((uint8_t *)job->cmd_reg, &req) == -1) {
22712396 		pr_err("gen reg info error\n");
22722397 		return -EINVAL;
22732398 	}
2399
+
2400
+	if (DEBUGGER_EN(TIME))
2401
+		pr_info("request[%d], generate register cost time %lld us\n",
2402
+			job->request_id, ktime_us_delta(ktime_get(), timestamp));
22742403 
22752404 	return ret;
22762405 }
....@@ -2338,7 +2467,7 @@
23382467 			cmd_reg[2 + i * 4], cmd_reg[3 + i * 4]);
23392468 }
23402469 
2341
-void rga2_dump_read_back_reg(struct rga_scheduler_t *scheduler)
2470
+static void rga2_dump_read_back_reg(struct rga_scheduler_t *scheduler)
23422471 {
23432472 	rga2_dump_read_back_sys_reg(scheduler);
23442473 	rga2_dump_read_back_csc_reg(scheduler);
....@@ -2351,66 +2480,71 @@
23512480 
23522481 	if (job->pre_intr_info.read_intr_en) {
23532482 		reg = s_RGA2_READ_LINE_SW_INTR_LINE_RD_TH(job->pre_intr_info.read_threshold);
2354
-		rga_write(reg, RGA2_READ_LINE_CNT_OFFSET, scheduler);
2483
+		rga_write(reg, RGA2_READ_LINE_CNT, scheduler);
23552484 	}
23562485 
23572486 	if (job->pre_intr_info.write_intr_en) {
23582487 		reg = s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_START(job->pre_intr_info.write_start);
23592488 		reg = ((reg & (~m_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP)) |
23602489 		       (s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP(job->pre_intr_info.write_step)));
2361
-		rga_write(reg, RGA2_WRITE_LINE_CNT_OFFSET, scheduler);
2490
+		rga_write(reg, RGA2_WRITE_LINE_CNT, scheduler);
23622491 	}
23632492 
2364
-	reg = rga_read(RGA2_SYS_CTRL_OFFSET, scheduler);
2365
-	reg = ((reg & (~m_RGA2_SYS_HOLD_MODE_EN)) |
2366
-	       (s_RGA2_SYS_HOLD_MODE_EN(job->pre_intr_info.read_hold_en)));
2367
-	rga_write(reg, RGA2_SYS_CTRL_OFFSET, scheduler);
2493
+	reg = rga_read(RGA2_SYS_CTRL, scheduler);
2494
+	reg = ((reg & (~m_RGA2_SYS_CTRL_HOLD_MODE_EN)) |
2495
+	       (s_RGA2_SYS_CTRL_HOLD_MODE_EN(job->pre_intr_info.read_hold_en)));
2496
+	rga_write(reg, RGA2_SYS_CTRL, scheduler);
23682497 
2369
-	reg = rga_read(RGA2_INT_OFFSET, scheduler);
2498
+	reg = rga_read(RGA2_INT, scheduler);
23702499 	reg = (reg | s_RGA2_INT_LINE_RD_CLEAR(0x1) | s_RGA2_INT_LINE_WR_CLEAR(0x1));
23712500 	reg = ((reg & (~m_RGA2_INT_LINE_RD_EN)) |
23722501 	       (s_RGA2_INT_LINE_RD_EN(job->pre_intr_info.read_intr_en)));
23732502 	reg = ((reg & (~m_RGA2_INT_LINE_WR_EN)) |
23742503 	       (s_RGA2_INT_LINE_WR_EN(job->pre_intr_info.write_intr_en)));
2375
-	rga_write(reg, RGA2_INT_OFFSET, scheduler);
2504
+	rga_write(reg, RGA2_INT, scheduler);
23762505 }
23772506 
23782507 static void rga2_set_reg_full_csc(struct rga_job *job, struct rga_scheduler_t *scheduler)
23792508 {
2380
-	uint8_t clip_y_max, clip_y_min;
2381
-	uint8_t clip_uv_max, clip_uv_min;
2382
-
2383
-	clip_y_max = 0xff;
2384
-	clip_y_min = 0x0;
2385
-	clip_uv_max = 0xff;
2386
-	clip_uv_min = 0;
2387
-
23882509 	/* full csc coefficient */
23892510 	/* Y coefficient */
2390
-	rga_write(job->full_csc.coe_y.r_v | (clip_y_max << 16) | (clip_y_min << 24),
2391
-		  RGA2_DST_CSC_00_OFFSET, scheduler);
2392
-	rga_write(job->full_csc.coe_y.g_y | (clip_uv_max << 16) | (clip_uv_min << 24),
2393
-		  RGA2_DST_CSC_01_OFFSET, scheduler);
2394
-	rga_write(job->full_csc.coe_y.b_u, RGA2_DST_CSC_02_OFFSET, scheduler);
2395
-	rga_write(job->full_csc.coe_y.off, RGA2_DST_CSC_OFF0_OFFSET, scheduler);
2511
+	rga_write(job->full_csc.coe_y.r_v |
2512
+		  (job->full_csc_clip.y.max << 16) | (job->full_csc_clip.y.min << 24),
2513
+		  RGA2_DST_CSC_00, scheduler);
2514
+	rga_write(job->full_csc.coe_y.g_y |
2515
+		  (job->full_csc_clip.uv.max << 16) | (job->full_csc_clip.uv.min << 24),
2516
+		  RGA2_DST_CSC_01, scheduler);
2517
+	rga_write(job->full_csc.coe_y.b_u, RGA2_DST_CSC_02, scheduler);
2518
+	rga_write(job->full_csc.coe_y.off, RGA2_DST_CSC_OFF0, scheduler);
23962519 
23972520 	/* U coefficient */
2398
-	rga_write(job->full_csc.coe_u.r_v, RGA2_DST_CSC_10_OFFSET, scheduler);
2399
-	rga_write(job->full_csc.coe_u.g_y, RGA2_DST_CSC_11_OFFSET, scheduler);
2400
-	rga_write(job->full_csc.coe_u.b_u, RGA2_DST_CSC_12_OFFSET, scheduler);
2401
-	rga_write(job->full_csc.coe_u.off, RGA2_DST_CSC_OFF1_OFFSET, scheduler);
2521
+	rga_write(job->full_csc.coe_u.r_v, RGA2_DST_CSC_10, scheduler);
2522
+	rga_write(job->full_csc.coe_u.g_y, RGA2_DST_CSC_11, scheduler);
2523
+	rga_write(job->full_csc.coe_u.b_u, RGA2_DST_CSC_12, scheduler);
2524
+	rga_write(job->full_csc.coe_u.off, RGA2_DST_CSC_OFF1, scheduler);
24022525 
24032526 	/* V coefficient */
2404
-	rga_write(job->full_csc.coe_v.r_v, RGA2_DST_CSC_20_OFFSET, scheduler);
2405
-	rga_write(job->full_csc.coe_v.g_y, RGA2_DST_CSC_21_OFFSET, scheduler);
2406
-	rga_write(job->full_csc.coe_v.b_u, RGA2_DST_CSC_22_OFFSET, scheduler);
2407
-	rga_write(job->full_csc.coe_v.off, RGA2_DST_CSC_OFF2_OFFSET, scheduler);
2527
+	rga_write(job->full_csc.coe_v.r_v, RGA2_DST_CSC_20, scheduler);
2528
+	rga_write(job->full_csc.coe_v.g_y, RGA2_DST_CSC_21, scheduler);
2529
+	rga_write(job->full_csc.coe_v.b_u, RGA2_DST_CSC_22, scheduler);
2530
+	rga_write(job->full_csc.coe_v.off, RGA2_DST_CSC_OFF2, scheduler);
24082531 }
24092532 
2410
-int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
2533
+static int rga2_set_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
24112534 {
2412
-	ktime_t now = ktime_get();
24132535 	int i;
2536
+	bool master_mode_en;
2537
+	uint32_t sys_ctrl;
2538
+	ktime_t now = ktime_get();
2539
+
2540
+	/*
2541
+	 * Currently there is no iova allocated for storing cmd for the IOMMU device,
2542
+	 * so the iommu device needs to use the slave mode.
2543
+	 */
2544
+	if (scheduler->data->mmu != RGA_IOMMU)
2545
+		master_mode_en = true;
2546
+	else
2547
+		master_mode_en = false;
24142548 
24152549 	if (job->pre_intr_info.enable)
24162550 		rga2_set_pre_intr_reg(job, scheduler);
....@@ -2419,7 +2553,7 @@
24192553 		rga2_set_reg_full_csc(job, scheduler);
24202554 
24212555 	if (DEBUGGER_EN(REG)) {
2422
-		int32_t *p;
2556
+		uint32_t *p;
24232557 
24242558 		rga2_dump_read_back_sys_reg(scheduler);
24252559 		rga2_dump_read_back_csc_reg(scheduler);
....@@ -2434,42 +2568,44 @@
24342568 
24352569 	/* All CMD finish int */
24362570 	rga_write(rga_read(RGA2_INT, scheduler) |
2437
-		  (0x1 << 10) | (0x1 << 9) | (0x1 << 8), RGA2_INT, scheduler);
2571
+		  m_RGA2_INT_ERROR_ENABLE_MASK | m_RGA2_INT_ALL_CMD_DONE_INT_EN,
2572
+		  RGA2_INT, scheduler);
24382573 
24392574 	/* sys_reg init */
2440
-	rga_write((0x1 << 2) | (0x1 << 5) | (0x1 << 6) | (0x1 << 11) | (0x1 << 12),
2441
-		  RGA2_SYS_CTRL, scheduler);
2575
+	sys_ctrl = m_RGA2_SYS_CTRL_AUTO_CKG | m_RGA2_SYS_CTRL_AUTO_RST |
2576
+		   m_RGA2_SYS_CTRL_RST_PROTECT_P | m_RGA2_SYS_CTRL_DST_WR_OPT_DIS |
2577
+		   m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS;
24422578 
2443
-	if (RGA2_USE_MASTER_MODE) {
2579
+	if (master_mode_en) {
24442580 		/* master mode */
2445
-		rga_write(rga_read(RGA2_SYS_CTRL, scheduler) | (0x1 << 1),
2446
-			  RGA2_SYS_CTRL, scheduler);
2581
+		sys_ctrl |= s_RGA2_SYS_CTRL_CMD_MODE(1);
24472582 
24482583 		/* cmd buffer flush cache to ddr */
24492584 		rga_dma_sync_flush_range(&job->cmd_reg[0], &job->cmd_reg[32], scheduler);
24502585 
24512586 		/* set cmd_addr */
24522587 		rga_write(virt_to_phys(job->cmd_reg), RGA2_CMD_BASE, scheduler);
2453
-
2454
-		rga_write(1, RGA2_CMD_CTRL, scheduler);
2588
+		rga_write(sys_ctrl, RGA2_SYS_CTRL, scheduler);
2589
+		rga_write(m_RGA2_CMD_CTRL_CMD_LINE_ST_P, RGA2_CMD_CTRL, scheduler);
24552590 	} else {
24562591 		/* slave mode */
2457
-		rga_write(rga_read(RGA2_SYS_CTRL, scheduler) | (0x0 << 1),
2458
-			  RGA2_SYS_CTRL, scheduler);
2592
+		sys_ctrl |= s_RGA2_SYS_CTRL_CMD_MODE(0) | m_RGA2_SYS_CTRL_CMD_OP_ST_P;
24592593 
24602594 		/* set cmd_reg */
24612595 		for (i = 0; i <= 32; i++)
24622596 			rga_write(job->cmd_reg[i], 0x100 + i * 4, scheduler);
24632597 
2464
-		rga_write(rga_read(RGA2_SYS_CTRL, scheduler) | 0x1, RGA2_SYS_CTRL, scheduler);
2598
+		rga_write(sys_ctrl, RGA2_SYS_CTRL, scheduler);
24652599 	}
24662600 
2467
-	if (DEBUGGER_EN(TIME)) {
2468
-		pr_info("sys_ctrl = %x, int = %x, set cmd use time = %lld\n",
2601
+	if (DEBUGGER_EN(REG))
2602
+		pr_info("sys_ctrl = %x, int = %x\n",
24692603 			rga_read(RGA2_SYS_CTRL, scheduler),
2470
-			rga_read(RGA2_INT, scheduler),
2471
-			ktime_us_delta(now, job->timestamp));
2472
-	}
2604
+			rga_read(RGA2_INT, scheduler));
2605
+
2606
+	if (DEBUGGER_EN(TIME))
2607
+		pr_info("request[%d], set register cost time %lld us\n",
2608
+			job->request_id, ktime_us_delta(now, job->timestamp));
24732609 
24742610 	job->hw_running_time = now;
24752611 	job->hw_recoder_time = now;
....@@ -2480,7 +2616,7 @@
24802616 	return 0;
24812617 }
24822618 
2483
-int rga2_get_version(struct rga_scheduler_t *scheduler)
2619
+static int rga2_get_version(struct rga_scheduler_t *scheduler)
24842620 {
24852621 	u32 major_version, minor_version, svn_version;
24862622 	u32 reg_version;
....@@ -2511,3 +2647,96 @@
25112647 
25122648 	return 0;
25132649 }
2650
+
2651
+static int rga2_read_back_reg(struct rga_job *job, struct rga_scheduler_t *scheduler)
2652
+{
2653
+	if (job->rga_command_base.osd_info.enable) {
2654
+		job->rga_command_base.osd_info.cur_flags0 = rga_read(RGA2_OSD_CUR_FLAGS0,
2655
+								     scheduler);
2656
+		job->rga_command_base.osd_info.cur_flags1 = rga_read(RGA2_OSD_CUR_FLAGS1,
2657
+								     scheduler);
2658
+	}
2659
+
2660
+	return 0;
2661
+}
2662
+
2663
+static int rga2_irq(struct rga_scheduler_t *scheduler)
2664
+{
2665
+	struct rga_job *job = scheduler->running_job;
2666
+
2667
+	/* The hardware interrupt top-half don't need to lock the scheduler. */
2668
+	if (job == NULL)
2669
+		return IRQ_HANDLED;
2670
+
2671
+	if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state))
2672
+		return IRQ_WAKE_THREAD;
2673
+
2674
+	job->intr_status = rga_read(RGA2_INT, scheduler);
2675
+	job->hw_status = rga_read(RGA2_STATUS2, scheduler);
2676
+	job->cmd_status = rga_read(RGA2_STATUS1, scheduler);
2677
+
2678
+	if (DEBUGGER_EN(INT_FLAG))
2679
+		pr_info("irq handler, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2680
+			job->intr_status, job->hw_status, job->cmd_status);
2681
+
2682
+	if (job->intr_status &
2683
+	    (m_RGA2_INT_CUR_CMD_DONE_INT_FLAG | m_RGA2_INT_ALL_CMD_DONE_INT_FLAG)) {
2684
+		set_bit(RGA_JOB_STATE_FINISH, &job->state);
2685
+	} else if (job->intr_status & m_RGA2_INT_ERROR_FLAG_MASK) {
2686
+		set_bit(RGA_JOB_STATE_INTR_ERR, &job->state);
2687
+
2688
+		pr_err("irq handler err! INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2689
+		       job->intr_status, job->hw_status, job->cmd_status);
2690
+		scheduler->ops->soft_reset(scheduler);
2691
+	}
2692
+
2693
+	/*clear INTR */
2694
+	rga_write(rga_read(RGA2_INT, scheduler) |
2695
+		  (m_RGA2_INT_ERROR_CLEAR_MASK |
2696
+		   m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR | m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR |
2697
+		   m_RGA2_INT_LINE_RD_CLEAR | m_RGA2_INT_LINE_WR_CLEAR),
2698
+		  RGA2_INT, scheduler);
2699
+
2700
+	return IRQ_WAKE_THREAD;
2701
+}
2702
+
2703
+static int rga2_isr_thread(struct rga_job *job, struct rga_scheduler_t *scheduler)
2704
+{
2705
+	if (DEBUGGER_EN(INT_FLAG))
2706
+		pr_info("isr thread, INTR[0x%x], HW_STATUS[0x%x], CMD_STATUS[0x%x]\n",
2707
+			rga_read(RGA2_INT, scheduler),
2708
+			rga_read(RGA2_STATUS2, scheduler),
2709
+			rga_read(RGA2_STATUS1, scheduler));
2710
+
2711
+	if (test_bit(RGA_JOB_STATE_INTR_ERR, &job->state)) {
2712
+		if (job->hw_status & m_RGA2_STATUS2_RPP_ERROR)
2713
+			pr_err("RGA current status: rpp error!\n");
2714
+		if (job->hw_status & m_RGA2_STATUS2_BUS_ERROR)
2715
+			pr_err("RGA current status: bus error!\n");
2716
+
2717
+		if (job->intr_status & m_RGA2_INT_ERROR_INT_FLAG) {
2718
+			pr_err("RGA bus error intr, please check your configuration and buffer.\n");
2719
+			job->ret = -EFAULT;
2720
+		} else if (job->intr_status & m_RGA2_INT_MMU_INT_FLAG) {
2721
+			pr_err("mmu failed, please check size of the buffer or whether the buffer has been freed.\n");
2722
+			job->ret = -EACCES;
2723
+		}
2724
+
2725
+		if (job->ret == 0) {
2726
+			pr_err("rga intr error[0x%x]!\n", job->intr_status);
2727
+			job->ret = -EFAULT;
2728
+		}
2729
+	}
2730
+
2731
+	return IRQ_HANDLED;
2732
+}
2733
+
2734
+const struct rga_backend_ops rga2_ops = {
2735
+	.get_version = rga2_get_version,
2736
+	.set_reg = rga2_set_reg,
2737
+	.init_reg = rga2_init_reg,
2738
+	.soft_reset = rga2_soft_reset,
2739
+	.read_back_reg = rga2_read_back_reg,
2740
+	.irq = rga2_irq,
2741
+	.isr_thread = rga2_isr_thread,
2742
+};