.. | .. |
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11 | 11 | #include <linux/usb/composite.h> |
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12 | 12 | |
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13 | 13 | #include "mtu3.h" |
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| 14 | +#include "mtu3_debug.h" |
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| 15 | +#include "mtu3_trace.h" |
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14 | 16 | |
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15 | 17 | /* ep0 is always mtu3->in_eps[0] */ |
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16 | 18 | #define next_ep0_request(mtu) next_request((mtu)->ep0) |
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.. | .. |
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151 | 153 | set ? "SEND" : "CLEAR", decode_ep0_state(mtu)); |
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152 | 154 | } |
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153 | 155 | |
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| 156 | +static void ep0_do_status_stage(struct mtu3 *mtu) |
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| 157 | +{ |
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| 158 | + void __iomem *mbase = mtu->mac_base; |
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| 159 | + u32 value; |
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| 160 | + |
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| 161 | + value = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; |
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| 162 | + mtu3_writel(mbase, U3D_EP0CSR, value | EP0_SETUPPKTRDY | EP0_DATAEND); |
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| 163 | +} |
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| 164 | + |
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154 | 165 | static int ep0_queue(struct mtu3_ep *mep0, struct mtu3_request *mreq); |
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155 | 166 | |
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156 | 167 | static void ep0_dummy_complete(struct usb_ep *ep, struct usb_request *req) |
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.. | .. |
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267 | 278 | u32 value; |
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268 | 279 | |
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269 | 280 | switch (le16_to_cpu(setup->wIndex) >> 8) { |
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270 | | - case TEST_J: |
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271 | | - dev_dbg(mtu->dev, "TEST_J\n"); |
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| 281 | + case USB_TEST_J: |
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| 282 | + dev_dbg(mtu->dev, "USB_TEST_J\n"); |
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272 | 283 | mtu->test_mode_nr = TEST_J_MODE; |
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273 | 284 | break; |
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274 | | - case TEST_K: |
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275 | | - dev_dbg(mtu->dev, "TEST_K\n"); |
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| 285 | + case USB_TEST_K: |
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| 286 | + dev_dbg(mtu->dev, "USB_TEST_K\n"); |
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276 | 287 | mtu->test_mode_nr = TEST_K_MODE; |
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277 | 288 | break; |
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278 | | - case TEST_SE0_NAK: |
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279 | | - dev_dbg(mtu->dev, "TEST_SE0_NAK\n"); |
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| 289 | + case USB_TEST_SE0_NAK: |
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| 290 | + dev_dbg(mtu->dev, "USB_TEST_SE0_NAK\n"); |
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280 | 291 | mtu->test_mode_nr = TEST_SE0_NAK_MODE; |
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281 | 292 | break; |
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282 | | - case TEST_PACKET: |
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283 | | - dev_dbg(mtu->dev, "TEST_PACKET\n"); |
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| 293 | + case USB_TEST_PACKET: |
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| 294 | + dev_dbg(mtu->dev, "USB_TEST_PACKET\n"); |
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284 | 295 | mtu->test_mode_nr = TEST_PACKET_MODE; |
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285 | 296 | break; |
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286 | 297 | default: |
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.. | .. |
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295 | 306 | ep0_load_test_packet(mtu); |
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296 | 307 | |
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297 | 308 | /* send status before entering test mode. */ |
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298 | | - value = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS; |
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299 | | - mtu3_writel(mbase, U3D_EP0CSR, value | EP0_SETUPPKTRDY | EP0_DATAEND); |
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| 309 | + ep0_do_status_stage(mtu); |
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300 | 310 | |
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301 | 311 | /* wait for ACK status sent by host */ |
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302 | 312 | readl_poll_timeout_atomic(mbase + U3D_EP0CSR, value, |
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.. | .. |
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407 | 417 | |
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408 | 418 | handled = 1; |
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409 | 419 | /* ignore request if endpoint is wedged */ |
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410 | | - if (mep->wedged) |
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| 420 | + if (mep->flags & MTU3_EP_WEDGE) |
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411 | 421 | break; |
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412 | 422 | |
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413 | 423 | mtu3_ep_stall_set(mep, set); |
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.. | .. |
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630 | 640 | { |
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631 | 641 | struct usb_ctrlrequest setup; |
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632 | 642 | struct mtu3_request *mreq; |
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633 | | - void __iomem *mbase = mtu->mac_base; |
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634 | 643 | int handled = 0; |
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635 | 644 | |
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636 | 645 | ep0_read_setup(mtu, &setup); |
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| 646 | + trace_mtu3_handle_setup(&setup); |
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637 | 647 | |
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638 | 648 | if ((setup.bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) |
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639 | 649 | handled = handle_standard_request(mtu, &setup); |
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.. | .. |
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661 | 671 | if (mtu->test_mode) { |
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662 | 672 | ; /* nothing to do */ |
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663 | 673 | } else if (handled == USB_GADGET_DELAYED_STATUS) { |
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664 | | - /* handle the delay STATUS phase till receive ep_queue on ep0 */ |
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665 | | - mtu->delayed_status = true; |
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| 674 | + |
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| 675 | + mreq = next_ep0_request(mtu); |
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| 676 | + if (mreq) { |
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| 677 | + /* already asked us to continue delayed status */ |
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| 678 | + ep0_do_status_stage(mtu); |
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| 679 | + ep0_req_giveback(mtu, &mreq->request); |
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| 680 | + } else { |
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| 681 | + /* do delayed STATUS stage till receive ep0_queue */ |
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| 682 | + mtu->delayed_status = true; |
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| 683 | + } |
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666 | 684 | } else if (le16_to_cpu(setup.wLength) == 0) { /* no data stage */ |
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667 | 685 | |
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668 | | - mtu3_writel(mbase, U3D_EP0CSR, |
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669 | | - (mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS) |
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670 | | - | EP0_SETUPPKTRDY | EP0_DATAEND); |
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671 | | - |
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| 686 | + ep0_do_status_stage(mtu); |
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672 | 687 | /* complete zlp request directly */ |
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673 | 688 | mreq = next_ep0_request(mtu); |
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674 | 689 | if (mreq && !mreq->request.length) |
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.. | .. |
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692 | 707 | mtu3_writel(mbase, U3D_EPISR, int_status); /* W1C */ |
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693 | 708 | |
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694 | 709 | /* only handle ep0's */ |
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695 | | - if (!(int_status & EP0ISR)) |
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| 710 | + if (!(int_status & (EP0ISR | SETUPENDISR))) |
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696 | 711 | return IRQ_NONE; |
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| 712 | + |
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| 713 | + /* abort current SETUP, and process new one */ |
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| 714 | + if (int_status & SETUPENDISR) |
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| 715 | + mtu->ep0_state = MU3D_EP0_STATE_SETUP; |
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697 | 716 | |
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698 | 717 | csr = mtu3_readl(mbase, U3D_EP0CSR); |
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699 | 718 | |
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.. | .. |
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706 | 725 | ret = IRQ_HANDLED; |
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707 | 726 | } |
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708 | 727 | dev_dbg(mtu->dev, "ep0_state: %s\n", decode_ep0_state(mtu)); |
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| 728 | + mtu3_dbg_trace(mtu->dev, "ep0_state %s", decode_ep0_state(mtu)); |
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709 | 729 | |
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710 | 730 | switch (mtu->ep0_state) { |
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711 | 731 | case MU3D_EP0_STATE_TX: |
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.. | .. |
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794 | 814 | } |
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795 | 815 | |
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796 | 816 | if (mtu->delayed_status) { |
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797 | | - u32 csr; |
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798 | 817 | |
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799 | 818 | mtu->delayed_status = false; |
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800 | | - csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS; |
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801 | | - csr |= EP0_SETUPPKTRDY | EP0_DATAEND; |
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802 | | - mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr); |
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| 819 | + ep0_do_status_stage(mtu); |
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803 | 820 | /* needn't giveback the request for handling delay STATUS */ |
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804 | 821 | return 0; |
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805 | 822 | } |
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