forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/usb/dwc2/hcd.c
....@@ -97,196 +97,6 @@
9797 	dwc2_writel(hsotg, intmsk, GINTMSK);
9898 }
9999 
100
-/*
101
- * Initializes the FSLSPClkSel field of the HCFG register depending on the
102
- * PHY type
103
- */
104
-static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
105
-{
106
-	u32 hcfg, val;
107
-
108
-	if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
109
-	     hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
110
-	     hsotg->params.ulpi_fs_ls) ||
111
-	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
112
-		/* Full speed PHY */
113
-		val = HCFG_FSLSPCLKSEL_48_MHZ;
114
-	} else {
115
-		/* High speed PHY running at full speed or high speed */
116
-		val = HCFG_FSLSPCLKSEL_30_60_MHZ;
117
-	}
118
-
119
-	dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
120
-	hcfg = dwc2_readl(hsotg, HCFG);
121
-	hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
122
-	hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
123
-	dwc2_writel(hsotg, hcfg, HCFG);
124
-}
125
-
126
-static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
127
-{
128
-	u32 usbcfg, ggpio, i2cctl;
129
-	int retval = 0;
130
-
131
-	/*
132
-	 * core_init() is now called on every switch so only call the
133
-	 * following for the first time through
134
-	 */
135
-	if (select_phy) {
136
-		dev_dbg(hsotg->dev, "FS PHY selected\n");
137
-
138
-		usbcfg = dwc2_readl(hsotg, GUSBCFG);
139
-		if (!(usbcfg & GUSBCFG_PHYSEL)) {
140
-			usbcfg |= GUSBCFG_PHYSEL;
141
-			dwc2_writel(hsotg, usbcfg, GUSBCFG);
142
-
143
-			/* Reset after a PHY select */
144
-			retval = dwc2_core_reset(hsotg, false);
145
-
146
-			if (retval) {
147
-				dev_err(hsotg->dev,
148
-					"%s: Reset failed, aborting", __func__);
149
-				return retval;
150
-			}
151
-		}
152
-
153
-		if (hsotg->params.activate_stm_fs_transceiver) {
154
-			ggpio = dwc2_readl(hsotg, GGPIO);
155
-			if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
156
-				dev_dbg(hsotg->dev, "Activating transceiver\n");
157
-				/*
158
-				 * STM32F4x9 uses the GGPIO register as general
159
-				 * core configuration register.
160
-				 */
161
-				ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
162
-				dwc2_writel(hsotg, ggpio, GGPIO);
163
-			}
164
-		}
165
-	}
166
-
167
-	/*
168
-	 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
169
-	 * do this on HNP Dev/Host mode switches (done in dev_init and
170
-	 * host_init).
171
-	 */
172
-	if (dwc2_is_host_mode(hsotg))
173
-		dwc2_init_fs_ls_pclk_sel(hsotg);
174
-
175
-	if (hsotg->params.i2c_enable) {
176
-		dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
177
-
178
-		/* Program GUSBCFG.OtgUtmiFsSel to I2C */
179
-		usbcfg = dwc2_readl(hsotg, GUSBCFG);
180
-		usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
181
-		dwc2_writel(hsotg, usbcfg, GUSBCFG);
182
-
183
-		/* Program GI2CCTL.I2CEn */
184
-		i2cctl = dwc2_readl(hsotg, GI2CCTL);
185
-		i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
186
-		i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
187
-		i2cctl &= ~GI2CCTL_I2CEN;
188
-		dwc2_writel(hsotg, i2cctl, GI2CCTL);
189
-		i2cctl |= GI2CCTL_I2CEN;
190
-		dwc2_writel(hsotg, i2cctl, GI2CCTL);
191
-	}
192
-
193
-	return retval;
194
-}
195
-
196
-static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
197
-{
198
-	u32 usbcfg, usbcfg_old;
199
-	int retval = 0;
200
-
201
-	if (!select_phy)
202
-		return 0;
203
-
204
-	usbcfg = dwc2_readl(hsotg, GUSBCFG);
205
-	usbcfg_old = usbcfg;
206
-
207
-	/*
208
-	 * HS PHY parameters. These parameters are preserved during soft reset
209
-	 * so only program the first time. Do a soft reset immediately after
210
-	 * setting phyif.
211
-	 */
212
-	switch (hsotg->params.phy_type) {
213
-	case DWC2_PHY_TYPE_PARAM_ULPI:
214
-		/* ULPI interface */
215
-		dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
216
-		usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
217
-		usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
218
-		if (hsotg->params.phy_ulpi_ddr)
219
-			usbcfg |= GUSBCFG_DDRSEL;
220
-
221
-		/* Set external VBUS indicator as needed. */
222
-		if (hsotg->params.oc_disable)
223
-			usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
224
-				   GUSBCFG_INDICATORPASSTHROUGH);
225
-		break;
226
-	case DWC2_PHY_TYPE_PARAM_UTMI:
227
-		/* UTMI+ interface */
228
-		dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
229
-		usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
230
-		if (hsotg->params.phy_utmi_width == 16)
231
-			usbcfg |= GUSBCFG_PHYIF16;
232
-		break;
233
-	default:
234
-		dev_err(hsotg->dev, "FS PHY selected at HS!\n");
235
-		break;
236
-	}
237
-
238
-	if (usbcfg != usbcfg_old) {
239
-		dwc2_writel(hsotg, usbcfg, GUSBCFG);
240
-
241
-		/* Reset after setting the PHY parameters */
242
-		retval = dwc2_core_reset(hsotg, false);
243
-		if (retval) {
244
-			dev_err(hsotg->dev,
245
-				"%s: Reset failed, aborting", __func__);
246
-			return retval;
247
-		}
248
-	}
249
-
250
-	return retval;
251
-}
252
-
253
-static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
254
-{
255
-	u32 usbcfg;
256
-	int retval = 0;
257
-
258
-	if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
259
-	     hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
260
-	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
261
-		/* If FS/LS mode with FS/LS PHY */
262
-		retval = dwc2_fs_phy_init(hsotg, select_phy);
263
-		if (retval)
264
-			return retval;
265
-	} else {
266
-		/* High speed PHY */
267
-		retval = dwc2_hs_phy_init(hsotg, select_phy);
268
-		if (retval)
269
-			return retval;
270
-	}
271
-
272
-	if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
273
-	    hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
274
-	    hsotg->params.ulpi_fs_ls) {
275
-		dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
276
-		usbcfg = dwc2_readl(hsotg, GUSBCFG);
277
-		usbcfg |= GUSBCFG_ULPI_FS_LS;
278
-		usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
279
-		dwc2_writel(hsotg, usbcfg, GUSBCFG);
280
-	} else {
281
-		usbcfg = dwc2_readl(hsotg, GUSBCFG);
282
-		usbcfg &= ~GUSBCFG_ULPI_FS_LS;
283
-		usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
284
-		dwc2_writel(hsotg, usbcfg, GUSBCFG);
285
-	}
286
-
287
-	return retval;
288
-}
289
-
290100 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
291101 {
292102 	u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
....@@ -358,16 +168,10 @@
358168 
359169 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
360170 {
361
-	int ret;
171
+	if (hsotg->vbus_supply)
172
+		return regulator_enable(hsotg->vbus_supply);
362173 
363
-	hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
364
-	if (IS_ERR(hsotg->vbus_supply)) {
365
-		ret = PTR_ERR(hsotg->vbus_supply);
366
-		hsotg->vbus_supply = NULL;
367
-		return ret == -ENODEV ? 0 : ret;
368
-	}
369
-
370
-	return regulator_enable(hsotg->vbus_supply);
174
+	return 0;
371175 }
372176 
373177 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
....@@ -1330,13 +1134,10 @@
13301134 	u32 remaining_count;
13311135 	u32 byte_count;
13321136 	u32 dword_count;
1333
-	u32 __iomem *data_fifo;
13341137 	u32 *data_buf = (u32 *)chan->xfer_buf;
13351138 
13361139 	if (dbg_hc(chan))
13371140 		dev_vdbg(hsotg->dev, "%s()\n", __func__);
1338
-
1339
-	data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
13401141 
13411142 	remaining_count = chan->xfer_len - chan->xfer_count;
13421143 	if (remaining_count > chan->max_packet)
....@@ -2451,25 +2252,31 @@
24512252 		num_channels = hsotg->params.host_channels;
24522253 		for (i = 0; i < num_channels; i++) {
24532254 			hcchar = dwc2_readl(hsotg, HCCHAR(i));
2454
-			hcchar &= ~HCCHAR_CHENA;
2455
-			hcchar |= HCCHAR_CHDIS;
2456
-			hcchar &= ~HCCHAR_EPDIR;
2457
-			dwc2_writel(hsotg, hcchar, HCCHAR(i));
2255
+			if (hcchar & HCCHAR_CHENA) {
2256
+				hcchar &= ~HCCHAR_CHENA;
2257
+				hcchar |= HCCHAR_CHDIS;
2258
+				hcchar &= ~HCCHAR_EPDIR;
2259
+				dwc2_writel(hsotg, hcchar, HCCHAR(i));
2260
+			}
24582261 		}
24592262 
24602263 		/* Halt all channels to put them into a known state */
24612264 		for (i = 0; i < num_channels; i++) {
24622265 			hcchar = dwc2_readl(hsotg, HCCHAR(i));
2463
-			hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2464
-			hcchar &= ~HCCHAR_EPDIR;
2465
-			dwc2_writel(hsotg, hcchar, HCCHAR(i));
2466
-			dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2467
-				__func__, i);
2266
+			if (hcchar & HCCHAR_CHENA) {
2267
+				hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2268
+				hcchar &= ~HCCHAR_EPDIR;
2269
+				dwc2_writel(hsotg, hcchar, HCCHAR(i));
2270
+				dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2271
+					__func__, i);
24682272 
2469
-			if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2470
-						      HCCHAR_CHENA, 1000)) {
2471
-				dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
2472
-					 i);
2273
+				if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2274
+							      HCCHAR_CHENA,
2275
+							      1000)) {
2276
+					dev_warn(hsotg->dev,
2277
+						 "Unable to clear enable on channel %d\n",
2278
+						 i);
2279
+				}
24732280 			}
24742281 		}
24752282 	}
....@@ -3844,7 +3651,7 @@
38443651 				"SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
38453652 			if (windex != hsotg->otg_port)
38463653 				goto error;
3847
-			if (hsotg->params.power_down == 2)
3654
+			if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION)
38483655 				dwc2_enter_hibernation(hsotg, 1);
38493656 			else
38503657 				dwc2_port_suspend(hsotg, windex);
....@@ -3862,7 +3669,7 @@
38623669 			break;
38633670 
38643671 		case USB_PORT_FEAT_RESET:
3865
-			if (hsotg->params.power_down == 2 &&
3672
+			if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION &&
38663673 			    hsotg->hibernated)
38673674 				dwc2_exit_hibernation(hsotg, 0, 1, 1);
38683675 			hprt0 = dwc2_read_hprt0(hsotg);
....@@ -4017,10 +3824,8 @@
40173824 					       gfp_t mem_flags)
40183825 {
40193826 	struct dwc2_hcd_urb *urb;
4020
-	u32 size = sizeof(*urb) + iso_desc_count *
4021
-		   sizeof(struct dwc2_hcd_iso_packet_desc);
40223827 
4023
-	urb = kzalloc(size, mem_flags);
3828
+	urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags);
40243829 	if (urb)
40253830 		urb->packet_count = iso_desc_count;
40263831 	return urb;
....@@ -4417,6 +4222,17 @@
44174222 	spin_unlock_irqrestore(&hsotg->lock, flags);
44184223 }
44194224 
4225
+static void dwc2_hcd_phy_reset_func(struct work_struct *work)
4226
+{
4227
+	struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4228
+						phy_reset_work);
4229
+	int ret;
4230
+
4231
+	ret = phy_reset(hsotg->phy);
4232
+	if (ret)
4233
+		dev_warn(hsotg->dev, "PHY reset failed\n");
4234
+}
4235
+
44204236 /*
44214237  * =========================================================================
44224238  *  Linux HC Driver Functions
....@@ -4528,6 +4344,10 @@
45284344 	if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
45294345 		goto unlock;
45304346 
4347
+	if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL ||
4348
+	    hsotg->flags.b.port_connect_status == 0)
4349
+		goto skip_power_saving;
4350
+
45314351 	/*
45324352 	 * Drive USB suspend and disable port Power
45334353 	 * if usb bus is not suspended.
....@@ -4536,20 +4356,18 @@
45364356 		hprt0 = dwc2_read_hprt0(hsotg);
45374357 		if (hprt0 & HPRT0_CONNSTS) {
45384358 			hprt0 |= HPRT0_SUSP;
4539
-			if (hsotg->params.power_down ==
4540
-			    DWC2_POWER_DOWN_PARAM_PARTIAL)
4359
+			if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL)
45414360 				hprt0 &= ~HPRT0_PWR;
45424361 			dwc2_writel(hsotg, hprt0, HPRT0);
4543
-			hsotg->bus_suspended = true;
45444362 		}
45454363 		if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
45464364 			spin_unlock_irqrestore(&hsotg->lock, flags);
45474365 			dwc2_vbus_supply_exit(hsotg);
45484366 			spin_lock_irqsave(&hsotg->lock, flags);
45494367 		} else {
4550
-			pcgctl = dwc2_readl(hsotg, PCGCTL);
4368
+			pcgctl = readl(hsotg->regs + PCGCTL);
45514369 			pcgctl |= PCGCTL_STOPPCLK;
4552
-			dwc2_writel(hsotg, pcgctl, PCGCTL);
4370
+			writel(pcgctl, hsotg->regs + PCGCTL);
45534371 		}
45544372 	}
45554373 
....@@ -4563,10 +4381,7 @@
45634381 			goto skip_power_saving;
45644382 		}
45654383 
4566
-		/*
4567
-		 * After entering partial_power_down,
4568
-		 * hardware is no more accessible.
4569
-		 */
4384
+		/* After entering partial_power_down, hardware is no more accessible */
45704385 		clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
45714386 	}
45724387 
....@@ -4589,8 +4404,8 @@
45894404 {
45904405 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
45914406 	unsigned long flags;
4592
-	int ret = 0;
45934407 	u32 pcgctl;
4408
+	int ret = 0;
45944409 
45954410 	spin_lock_irqsave(&hsotg->lock, flags);
45964411 
....@@ -4599,6 +4414,11 @@
45994414 
46004415 	if (hsotg->lx_state != DWC2_L2)
46014416 		goto unlock;
4417
+
4418
+	if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) {
4419
+		hsotg->lx_state = DWC2_L0;
4420
+		goto unlock;
4421
+	}
46024422 
46034423 	/*
46044424 	 * Enable power if not already done.
....@@ -4618,14 +4438,15 @@
46184438 		 */
46194439 		set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
46204440 
4441
+
46214442 		/* Exit partial_power_down */
46224443 		ret = dwc2_exit_partial_power_down(hsotg, true);
46234444 		if (ret && (ret != -ENOTSUPP))
46244445 			dev_err(hsotg->dev, "exit partial_power_down failed\n");
46254446 	} else {
4626
-		pcgctl = dwc2_readl(hsotg, PCGCTL);
4447
+		pcgctl = readl(hsotg->regs + PCGCTL);
46274448 		pcgctl &= ~PCGCTL_STOPPCLK;
4628
-		dwc2_writel(hsotg, pcgctl, PCGCTL);
4449
+		writel(pcgctl, hsotg->regs + PCGCTL);
46294450 	}
46304451 
46314452 	hsotg->lx_state = DWC2_L0;
....@@ -4641,10 +4462,7 @@
46414462 		if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
46424463 			dwc2_vbus_supply_init(hsotg);
46434464 
4644
-			/*
4645
-			 * Wait for controller to correctly
4646
-			 * update D+/D- level.
4647
-			 */
4465
+			/* Wait for controller to correctly update D+/D- level */
46484466 			usleep_range(3000, 5000);
46494467 		}
46504468 
....@@ -4814,7 +4632,7 @@
48144632 
48154633 	buf = urb->transfer_buffer;
48164634 
4817
-	if (hcd->self.uses_dma) {
4635
+	if (hcd_uses_dma(hcd)) {
48184636 		if (!buf && (urb->transfer_dma & 3)) {
48194637 			dev_err(hsotg->dev,
48204638 				"%s: unaligned transfer with no transfer_buffer",
....@@ -4891,7 +4709,6 @@
48914709 	spin_unlock_irqrestore(&hsotg->lock, flags);
48924710 	urb->hcpriv = NULL;
48934711 	kfree(qtd);
4894
-	qtd = NULL;
48954712 fail1:
48964713 	if (qh_allocated) {
48974714 		struct dwc2_qtd *qtd2, *qtd2_tmp;
....@@ -5194,6 +5011,8 @@
51945011 		destroy_workqueue(hsotg->wq_otg);
51955012 	}
51965013 
5014
+	cancel_work_sync(&hsotg->phy_reset_work);
5015
+
51975016 	del_timer(&hsotg->wkp_timer);
51985017 }
51995018 
....@@ -5267,19 +5086,19 @@
52675086 		dwc2_hc_driver.reset_device = dwc2_reset_device;
52685087 	}
52695088 
5089
+	if (hsotg->params.host_dma)
5090
+		dwc2_hc_driver.flags |= HCD_DMA;
5091
+
52705092 	hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
52715093 	if (!hcd)
52725094 		goto error1;
5273
-
5274
-	if (!hsotg->params.host_dma)
5275
-		hcd->self.uses_dma = 0;
52765095 
52775096 	hcd->has_tt = 1;
52785097 
52795098 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
52805099 	if (!res) {
52815100 		retval = -EINVAL;
5282
-		goto error1;
5101
+		goto error2;
52835102 	}
52845103 	hcd->rsrc_start = res->start;
52855104 	hcd->rsrc_len = resource_size(res);
....@@ -5339,11 +5158,10 @@
53395158 		hsotg->hc_ptr_array[i] = channel;
53405159 	}
53415160 
5342
-	/* Initialize hsotg start work */
5161
+	/* Initialize work */
53435162 	INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5344
-
5345
-	/* Initialize port reset work */
53465163 	INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5164
+	INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
53475165 
53485166 	/*
53495167 	 * Allocate space for storing data on status transactions. Normally no
....@@ -5811,3 +5629,22 @@
58115629 	dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
58125630 	return ret;
58135631 }
5632
+
5633
+bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
5634
+{
5635
+	struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub;
5636
+
5637
+	/* If the controller isn't allowed to wakeup then we can power off. */
5638
+	if (!device_may_wakeup(dwc2->dev))
5639
+		return true;
5640
+
5641
+	/*
5642
+	 * We don't want to power off the PHY if something under the
5643
+	 * root hub has wakeup enabled.
5644
+	 */
5645
+	if (usb_wakeup_enabled_descendants(root_hub))
5646
+		return false;
5647
+
5648
+	/* No reason to keep the PHY powered, so allow poweroff */
5649
+	return true;
5650
+}