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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/usb/dwc2/core.h
....@@ -1,4 +1,4 @@
1
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
1
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
22 /*
33  * core.h - DesignWare HS OTG Controller common declarations
44  *
....@@ -68,9 +68,6 @@
6868 /* Maximum number of Endpoints/HostChannels */
6969 #define MAX_EPS_CHANNELS	16
7070 
71
-/* Maximum number of dwc2 clocks */
72
-#define DWC2_MAX_CLKS 3
73
-
7471 /* dwc2-hsotg declarations */
7572 static const char * const dwc2_hsotg_supply_names[] = {
7673 	"vusb_d",               /* digital USB supply, 1.2V */
....@@ -138,7 +135,7 @@
138135  * @target_frame: Targeted frame num to setup next ISOC transfer
139136  * @frame_overrun: Indicates SOF number overrun in DSTS
140137  *
141
- * This is the driver's state for each registered enpoint, allowing it
138
+ * This is the driver's state for each registered endpoint, allowing it
142139  * to keep track of transactions that need doing. Each endpoint has a
143140  * lock to protect the state, to try and avoid using an overall lock
144141  * for the host controller as much as possible.
....@@ -398,10 +395,28 @@
398395  *			0 - No
399396  *			1 - Yes
400397  * @hird_threshold:	Value of BESL or HIRD Threshold.
398
+ * @ref_clk_per:        Indicates in terms of pico seconds the period
399
+ *                      of ref_clk.
400
+ *			62500 - 16MHz
401
+ *                      58823 - 17MHz
402
+ *                      52083 - 19.2MHz
403
+ *			50000 - 20MHz
404
+ *			41666 - 24MHz
405
+ *			33333 - 30MHz (default)
406
+ *			25000 - 40MHz
407
+ * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
408
+ *                      the controller should generate an interrupt if the
409
+ *                      device had been in L1 state until that period.
410
+ *                      This is used by SW to initiate Remote WakeUp in the
411
+ *                      controller so as to sync to the uF number from the host.
401412  * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
402413  *			register.
403414  *			0 - Deactivate the transceiver (default)
404415  *			1 - Activate the transceiver
416
+ * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
417
+ *			detection using GGPIO register.
418
+ *			0 - Deactivate the external level detection (default)
419
+ *			1 - Activate the external level detection
405420  * @g_dma:              Enables gadget dma usage (default: autodetect).
406421  * @g_dma_desc:         Enables gadget descriptor DMA (default: autodetect).
407422  * @g_rx_fifo_size:	The periodic rx fifo size for the device, in
....@@ -421,6 +436,9 @@
421436  *                      back to DWC2_SPEED_PARAM_HIGH while device is gone.
422437  *			0 - No (default)
423438  *			1 - Yes
439
+ * @service_interval:   Enable service interval based scheduling.
440
+ *                      0 - No
441
+ *                      1 - Yes
424442  *
425443  * The following parameters may be specified when starting the module. These
426444  * parameters define how the DWC_otg controller should be configured. A
....@@ -466,12 +484,18 @@
466484 	bool lpm_clock_gating;
467485 	bool besl;
468486 	bool hird_threshold_en;
487
+	bool service_interval;
469488 	u8 hird_threshold;
470489 	bool activate_stm_fs_transceiver;
490
+	bool activate_stm_id_vb_detection;
471491 	bool ipg_isoc_en;
472492 	u16 max_packet_count;
473493 	u32 max_transfer_size;
474494 	u32 ahbcfg;
495
+
496
+	/* GREFCLK parameters */
497
+	u32 ref_clk_per;
498
+	u16 sof_cnt_wkup_alert;
475499 
476500 	/* Host parameters */
477501 	bool host_dma;
....@@ -610,6 +634,10 @@
610634  *			FIFO sizing is enabled 16 to 32768
611635  *			Actual maximum value is autodetected and also
612636  *			the default.
637
+ * @service_interval_mode: For enabling service interval based scheduling in the
638
+ *                         controller.
639
+ *                           0 - Disable
640
+ *                           1 - Enable
613641  */
614642 struct dwc2_hw_params {
615643 	unsigned op_mode:3;
....@@ -640,6 +668,7 @@
640668 	unsigned utmi_phy_data_width:2;
641669 	unsigned lpm_mode:1;
642670 	unsigned ipg_isoc_en:1;
671
+	unsigned service_interval_mode:1;
643672 	u32 snpsid;
644673 	u32 dev_ep_dirs;
645674 	u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
....@@ -833,11 +862,17 @@
833862  *                      - USB_DR_MODE_PERIPHERAL
834863  *                      - USB_DR_MODE_HOST
835864  *                      - USB_DR_MODE_OTG
865
+ * @role_sw:		usb_role_switch handle
836866  * @hcd_enabled:	Host mode sub-driver initialization indicator.
837867  * @gadget_enabled:	Peripheral mode sub-driver initialization indicator.
838868  * @ll_hw_enabled:	Status of low-level hardware resources.
839869  * @ll_phy_enabled	Status of low-level PHY resources.
840870  * @hibernated:		True if core is hibernated
871
+ * @reset_phy_on_wake:	Quirk saying that we should assert PHY reset on a
872
+ *			remote wakeup.
873
+ * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
874
+ * @need_phy_for_wake:	Quirk saying that we should keep the PHY on at
875
+ *			suspend if we need USB to wake us up.
841876  * @frame_number:       Frame number read from the core. For both device
842877  *			and host modes. The value ranges are from 0
843878  *			to HFNUM_MAX_FRNUM.
....@@ -848,7 +883,8 @@
848883  *                      removed once all SoCs support usb transceiver.
849884  * @supplies:           Definition of USB power supplies
850885  * @vbus_supply:        Regulator supplying vbus.
851
- * @phyif:              PHY interface width
886
+ * @usb33d:		Optional 3.3v regulator used on some stm32 devices to
887
+ *			supply ID and VBUS detection hardware.
852888  * @lock:		Spinlock that protects all the driver data structures
853889  * @priv:		Stores a pointer to the struct usb_hcd
854890  * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
....@@ -951,6 +987,7 @@
951987  * @status_buf_dma:     DMA address for status_buf
952988  * @start_work:         Delayed work for handling host A-cable connection
953989  * @reset_work:         Delayed work for handling a port reset
990
+ * @phy_reset_work:     Work structure for doing a PHY reset
954991  * @otg_port:           OTG port number
955992  * @frame_list:         Frame list
956993  * @frame_list_dma:     Frame list DMA address
....@@ -970,6 +1007,7 @@
9701007  * @ctrl_buff:          Buffer for EP0 control requests.
9711008  * @ctrl_req:           Request for EP0 control packets.
9721009  * @ep0_state:          EP0 control transfers state
1010
+ * @delayed_status:		true when gadget driver asks for delayed status
9731011  * @test_mode:          USB test mode requested by the host
9741012  * @remote_wakeup_allowed: True if device is allowed to wake-up host by
9751013  *                      remote-wakeup signalling
....@@ -1002,7 +1040,7 @@
10021040  * @fifo_mem:			Total internal RAM for FIFOs (bytes)
10031041  * @fifo_map:		Each bit intend for concrete fifo. If that bit is set,
10041042  *			then that fifo is used
1005
- * @gadget:		Represents a usb slave device
1043
+ * @gadget:		Represents a usb gadget device
10061044  * @connected:		Used in slave mode. True if device connected with host
10071045  * @eps_in:		The IN endpoints being supplied to the gadget framework
10081046  * @eps_out:		The OUT endpoints being supplied to the gadget framework
....@@ -1020,26 +1058,29 @@
10201058 	struct dwc2_core_params params;
10211059 	enum usb_otg_state op_state;
10221060 	enum usb_dr_mode dr_mode;
1061
+	struct usb_role_switch *role_sw;
10231062 	unsigned int hcd_enabled:1;
10241063 	unsigned int gadget_enabled:1;
10251064 	unsigned int ll_hw_enabled:1;
10261065 	unsigned int ll_phy_enabled:1;
10271066 	unsigned int hibernated:1;
1028
-	bool bus_suspended;
1067
+	unsigned int reset_phy_on_wake:1;
1068
+	unsigned int need_phy_for_wake:1;
1069
+	unsigned int phy_off_for_suspend:1;
10291070 	u16 frame_number;
10301071 
10311072 	struct phy *phy;
1032
-	struct work_struct phy_rst_work;
10331073 	struct usb_phy *uphy;
10341074 	struct dwc2_hsotg_plat *plat;
10351075 	struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
10361076 	struct regulator *vbus_supply;
1037
-	u32 phyif;
1077
+	struct regulator *usb33d;
10381078 
10391079 	spinlock_t lock;
10401080 	void *priv;
10411081 	int     irq;
1042
-	struct clk *clks[DWC2_MAX_CLKS];
1082
+	struct clk_bulk_data *clks;
1083
+	int num_clks;
10431084 	struct reset_control *reset;
10441085 	struct reset_control *reset_ecc;
10451086 
....@@ -1069,8 +1110,10 @@
10691110 #define DWC2_CORE_REV_3_00a	0x4f54300a
10701111 #define DWC2_CORE_REV_3_10a	0x4f54310a
10711112 #define DWC2_CORE_REV_4_00a	0x4f54400a
1113
+#define DWC2_CORE_REV_4_20a	0x4f54420a
10721114 #define DWC2_FS_IOT_REV_1_00a	0x5531100a
10731115 #define DWC2_HS_IOT_REV_1_00a	0x5532100a
1116
+#define DWC2_CORE_REV_MASK	0x0000ffff
10741117 
10751118 	/* DWC OTG HW Core ID */
10761119 #define DWC2_OTG_ID		0x4f540000
....@@ -1105,6 +1148,7 @@
11051148 	unsigned long hs_periodic_bitmap[
11061149 		DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
11071150 	u16 periodic_qh_count;
1151
+	bool bus_suspended;
11081152 	bool new_connection;
11091153 
11101154 	u16 last_frame_num;
....@@ -1128,6 +1172,7 @@
11281172 
11291173 	struct delayed_work start_work;
11301174 	struct delayed_work reset_work;
1175
+	struct work_struct phy_reset_work;
11311176 	u8 otg_port;
11321177 	u32 *frame_list;
11331178 	dma_addr_t frame_list_dma;
....@@ -1153,6 +1198,7 @@
11531198 	void *ep0_buff;
11541199 	void *ctrl_buff;
11551200 	enum dwc2_ep0_state ep0_state;
1201
+	unsigned delayed_status : 1;
11561202 	u8 test_mode;
11571203 
11581204 	dma_addr_t setup_desc_dma[2];
....@@ -1264,11 +1310,15 @@
12641310 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
12651311 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
12661312 		int reset, int is_host);
1313
+void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1314
+int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
12671315 
12681316 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
12691317 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
12701318 
12711319 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1320
+
1321
+int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
12721322 
12731323 /*
12741324  * Common core Functions.
....@@ -1336,6 +1386,11 @@
13361386 	return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
13371387 }
13381388 
1389
+int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1390
+void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1391
+void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1392
+void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1393
+
13391394 /*
13401395  * Dump core registers and SPRAM
13411396  */
....@@ -1352,10 +1407,12 @@
13521407 int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
13531408 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
13541409 				       bool reset);
1410
+void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
13551411 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
13561412 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
13571413 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
13581414 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1415
+#define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
13591416 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
13601417 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
13611418 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
....@@ -1365,6 +1422,7 @@
13651422 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
13661423 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
13671424 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1425
+void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
13681426 #else
13691427 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
13701428 { return 0; }
....@@ -1376,12 +1434,14 @@
13761434 { return 0; }
13771435 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
13781436 						     bool reset) {}
1437
+static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
13791438 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
13801439 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
13811440 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
13821441 					   int testmode)
13831442 { return 0; }
13841443 #define dwc2_is_device_connected(hsotg) (0)
1444
+#define dwc2_is_device_enabled(hsotg) (0)
13851445 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
13861446 { return 0; }
13871447 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
....@@ -1399,6 +1459,7 @@
13991459 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
14001460 { return 0; }
14011461 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
1462
+static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
14021463 #endif
14031464 
14041465 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
....@@ -1413,6 +1474,9 @@
14131474 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
14141475 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
14151476 			       int rem_wakeup, int reset);
1477
+bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
1478
+static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1479
+{ schedule_work(&hsotg->phy_reset_work); }
14161480 #else
14171481 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
14181482 { return 0; }
....@@ -1436,6 +1500,9 @@
14361500 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
14371501 					     int rem_wakeup, int reset)
14381502 { return 0; }
1503
+static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1504
+{ return false; }
1505
+static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
14391506 
14401507 #endif
14411508