.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd |
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3 | 4 | * Caesar Wang <wxt@rock-chips.com> |
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4 | | - * |
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5 | | - * This program is free software; you can redistribute it and/or modify it |
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6 | | - * under the terms and conditions of the GNU General Public License, |
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7 | | - * version 2, as published by the Free Software Foundation. |
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8 | | - * |
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9 | | - * This program is distributed in the hope it will be useful, but WITHOUT |
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10 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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12 | | - * more details. |
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13 | 5 | */ |
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14 | 6 | |
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15 | 7 | #include <linux/clk.h> |
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.. | .. |
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29 | 21 | #include <linux/pinctrl/consumer.h> |
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30 | 22 | #include <linux/nvmem-consumer.h> |
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31 | 23 | |
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32 | | -/** |
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| 24 | +/* |
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33 | 25 | * If the temperature over a period of time High, |
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34 | 26 | * the resulting TSHUT gave CRU module,let it reset the entire chip, |
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35 | 27 | * or via GPIO give PMIC. |
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.. | .. |
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39 | 31 | TSHUT_MODE_OTP, |
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40 | 32 | }; |
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41 | 33 | |
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42 | | -/** |
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| 34 | +/* |
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43 | 35 | * The system Temperature Sensors tshut(tshut) polarity |
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44 | 36 | * the bit 8 is tshut polarity. |
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45 | 37 | * 0: low active, 1: high active |
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.. | .. |
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49 | 41 | TSHUT_HIGH_ACTIVE, |
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50 | 42 | }; |
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51 | 43 | |
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52 | | -/** |
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| 44 | +/* |
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53 | 45 | * The system has two Temperature Sensors. |
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54 | 46 | * sensor0 is for CPU, and sensor1 is for GPU. |
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55 | 47 | */ |
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.. | .. |
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58 | 50 | SENSOR_GPU, |
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59 | 51 | }; |
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60 | 52 | |
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61 | | -/** |
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| 53 | +/* |
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62 | 54 | * The conversion table has the adc value and temperature. |
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63 | 55 | * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) |
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64 | 56 | * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) |
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.. | .. |
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67 | 59 | ADC_DECREMENT = 0, |
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68 | 60 | ADC_INCREMENT, |
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69 | 61 | }; |
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| 62 | + |
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| 63 | +#include "thermal_hwmon.h" |
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70 | 64 | |
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71 | 65 | /** |
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72 | 66 | * The max sensors is seven in rockchip SoCs. |
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.. | .. |
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78 | 72 | * @id: conversion table |
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79 | 73 | * @length: size of conversion table |
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80 | 74 | * @data_mask: mask to apply on data inputs |
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| 75 | + * @kNum: linear parameter k |
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| 76 | + * @bNum: linear parameter b |
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81 | 77 | * @mode: sort mode of this adc variant (incrementing or decrementing) |
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82 | 78 | */ |
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83 | 79 | struct chip_tsadc_table { |
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.. | .. |
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92 | 88 | |
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93 | 89 | /** |
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94 | 90 | * struct rockchip_tsadc_chip - hold the private data of tsadc chip |
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95 | | - * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel |
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| 91 | + * @chn_id: array of sensor ids of chip corresponding to the channel |
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96 | 92 | * @chn_num: the channel number of tsadc chip |
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97 | 93 | * @conversion_time: the conversion time of tsadc |
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98 | 94 | * @trim_slope: use to conversion trim code to trim temp |
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.. | .. |
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101 | 97 | * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) |
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102 | 98 | * @initialize: SoC special initialize tsadc controller method |
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103 | 99 | * @irq_ack: clear the interrupt |
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| 100 | + * @control: enable/disable method for the tsadc controller |
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104 | 101 | * @get_temp: get the temperature |
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105 | 102 | * @set_alarm_temp: set the high temperature interrupt |
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106 | 103 | * @set_tshut_temp: set the hardware-controlled shutdown temperature |
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.. | .. |
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169 | 166 | * @chip: pointer to the platform/configuration data |
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170 | 167 | * @pdev: platform device of thermal |
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171 | 168 | * @reset: the reset controller of tsadc |
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172 | | - * @sensors[SOC_MAX_SENSORS]: the thermal sensor |
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173 | | - * @clk: the controller clock is divided by the exteral 24MHz |
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174 | | - * @pclk: the advanced peripherals bus clock |
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| 169 | + * @sensors: array of thermal sensors |
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| 170 | + * @clk: the bulk clk of tsadc, include controller clock and peripherals bus clock |
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| 171 | + * @num_clks: the number of tsadc clks |
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175 | 172 | * @grf: the general register file will be used to do static set by software |
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176 | 173 | * @regs: the base address of tsadc controller |
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177 | 174 | * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) |
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178 | 175 | * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) |
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| 176 | + * @pinctrl: the pinctrl of tsadc |
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| 177 | + * @gpio_state: pinctrl select gpio function |
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| 178 | + * @otp_state: pinctrl select otp out function |
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| 179 | + * @panic_nb: panic notifier block |
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179 | 180 | */ |
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180 | 181 | struct rockchip_thermal_data { |
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181 | 182 | const struct rockchip_tsadc_chip *chip; |
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.. | .. |
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230 | 231 | #define TSADCV2_AUTO_PERIOD_HT 0x6c |
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231 | 232 | #define TSADCV3_AUTO_PERIOD 0x154 |
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232 | 233 | #define TSADCV3_AUTO_PERIOD_HT 0x158 |
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233 | | -#define TSADCV3_Q_MAX 0x210 |
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| 234 | +#define TSADCV9_Q_MAX 0x210 |
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| 235 | +#define TSADCV9_FLOW_CON 0x218 |
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234 | 236 | |
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235 | 237 | #define TSADCV2_AUTO_EN BIT(0) |
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236 | 238 | #define TSADCV2_AUTO_EN_MASK BIT(16) |
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.. | .. |
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269 | 271 | #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ |
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270 | 272 | #define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */ |
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271 | 273 | #define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ |
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| 274 | +#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */ |
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| 275 | +#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */ |
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272 | 276 | #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */ |
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| 277 | +#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */ |
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273 | 278 | |
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274 | 279 | #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ |
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275 | 280 | #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ |
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| 281 | + |
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| 282 | +#define TSADCV9_AUTO_SRC (0x10001 << 0) |
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| 283 | +#define TSADCV9_PD_MODE (0x10001 << 4) |
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| 284 | +#define TSADCV9_Q_MAX_VAL (0xffff0400 << 0) |
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276 | 285 | |
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277 | 286 | #define GRF_SARADC_TESTBIT 0x0e644 |
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278 | 287 | #define GRF_TSADC_TESTBIT_L 0x0e648 |
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.. | .. |
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283 | 292 | |
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284 | 293 | #define RK1808_BUS_GRF_SOC_CON0 0x0400 |
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285 | 294 | |
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286 | | -#define RK3568_GRF_TSADC_CON 0x0600 |
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287 | 295 | #define RK3528_GRF_TSADC_CON 0x40030 |
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| 296 | + |
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| 297 | +#define RK3562_GRF_TSADC_CON 0x0580 |
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| 298 | + |
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| 299 | +#define RK3568_GRF_TSADC_CON 0x0600 |
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288 | 300 | #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) |
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289 | 301 | #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) |
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290 | 302 | #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) |
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291 | 303 | #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) |
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| 304 | + |
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| 305 | +#define RV1106_VOGRF_TSADC_CON 0x6000C |
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| 306 | +#define RV1106_VOGRF_TSADC_TSEN (0x10001 << 8) |
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| 307 | +#define RV1106_VOGRF_TSADC_ANA (0xff0007 << 0) |
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292 | 308 | |
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293 | 309 | #define RV1126_GRF0_TSADC_CON 0x0100 |
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294 | 310 | |
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.. | .. |
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309 | 325 | |
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310 | 326 | /* -40 to 125 is reliable, outside the range existed unreliability */ |
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311 | 327 | #define MIN_TEMP (-60000) |
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312 | | -#define LOWEST_TEMP (-273000) |
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313 | 328 | #define MAX_TEMP (180000) |
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314 | | -#define MAX_ENV_TEMP (85000) |
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315 | | - |
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316 | | -#define BASE (1024) |
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317 | | -#define BASE_SHIFT (10) |
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318 | | -#define START_DEBOUNCE_COUNT (100) |
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319 | | -#define HIGHER_DEBOUNCE_TEMP (30000) |
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320 | | -#define LOWER_DEBOUNCE_TEMP (15000) |
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321 | 329 | |
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322 | 330 | /** |
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323 | 331 | * struct tsadc_table - code to temperature conversion table |
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.. | .. |
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332 | 340 | struct tsadc_table { |
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333 | 341 | u32 code; |
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334 | 342 | int temp; |
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| 343 | +}; |
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| 344 | + |
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| 345 | +static const struct tsadc_table rv1106_code_table[] = { |
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| 346 | + {0, MIN_TEMP}, |
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| 347 | + {363, MIN_TEMP}, |
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| 348 | + {396, -40000}, |
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| 349 | + {504, 25000}, |
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| 350 | + {605, 85000}, |
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| 351 | + {673, 125000}, |
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| 352 | + {758, MAX_TEMP}, |
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| 353 | + {TSADCV2_DATA_MASK, MAX_TEMP}, |
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335 | 354 | }; |
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336 | 355 | |
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337 | 356 | static const struct tsadc_table rv1108_table[] = { |
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.. | .. |
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627 | 646 | static const struct tsadc_table rk3528_code_table[] = { |
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628 | 647 | {0, MIN_TEMP}, |
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629 | 648 | {1386, MIN_TEMP}, |
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630 | | - {1419, -40000}, |
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631 | | - {1427, -35000}, |
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632 | | - {1435, -30000}, |
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633 | | - {1443, -25000}, |
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634 | | - {1452, -20000}, |
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635 | | - {1460, -15000}, |
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636 | | - {1468, -10000}, |
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637 | | - {1477, -5000}, |
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638 | | - {1486, 0}, |
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639 | | - {1494, 5000}, |
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640 | | - {1502, 10000}, |
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641 | | - {1510, 15000}, |
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642 | | - {1519, 20000}, |
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643 | | - {1527, 25000}, |
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644 | | - {1535, 30000}, |
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645 | | - {1544, 35000}, |
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646 | | - {1552, 40000}, |
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647 | | - {1561, 45000}, |
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648 | | - {1569, 50000}, |
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649 | | - {1578, 55000}, |
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650 | | - {1586, 60000}, |
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651 | | - {1594, 65000}, |
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652 | | - {1603, 70000}, |
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653 | | - {1612, 75000}, |
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654 | | - {1620, 80000}, |
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| 649 | + {1410, -40000}, |
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| 650 | + {1419, -35000}, |
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| 651 | + {1428, -30000}, |
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| 652 | + {1436, -25000}, |
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| 653 | + {1445, -20000}, |
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| 654 | + {1454, -15000}, |
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| 655 | + {1463, -10000}, |
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| 656 | + {1471, -5000}, |
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| 657 | + {1480, 0}, |
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| 658 | + {1489, 5000}, |
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| 659 | + {1498, 10000}, |
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| 660 | + {1506, 15000}, |
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| 661 | + {1515, 20000}, |
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| 662 | + {1524, 25000}, |
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| 663 | + {1533, 30000}, |
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| 664 | + {1541, 35000}, |
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| 665 | + {1550, 40000}, |
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| 666 | + {1558, 45000}, |
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| 667 | + {1567, 50000}, |
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| 668 | + {1575, 55000}, |
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| 669 | + {1584, 60000}, |
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| 670 | + {1593, 65000}, |
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| 671 | + {1602, 70000}, |
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| 672 | + {1610, 75000}, |
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| 673 | + {1619, 80000}, |
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655 | 674 | {1628, 85000}, |
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656 | 675 | {1637, 90000}, |
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657 | 676 | {1646, 95000}, |
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658 | 677 | {1654, 100000}, |
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659 | | - {1662, 105000}, |
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660 | | - {1671, 110000}, |
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661 | | - {1679, 115000}, |
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662 | | - {1688, 120000}, |
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663 | | - {1696, 125000}, |
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| 678 | + {1663, 105000}, |
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| 679 | + {1672, 110000}, |
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| 680 | + {1680, 115000}, |
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| 681 | + {1689, 120000}, |
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| 682 | + {1697, 125000}, |
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664 | 683 | {1790, MAX_TEMP}, |
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665 | 684 | {TSADCV5_DATA_MASK, MAX_TEMP}, |
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| 685 | +}; |
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| 686 | + |
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| 687 | +static const struct tsadc_table rk3562_code_table[] = { |
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| 688 | + {0, MIN_TEMP}, |
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| 689 | + {1385, MIN_TEMP}, |
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| 690 | + {1419, -40000}, |
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| 691 | + {1428, -35000}, |
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| 692 | + {1436, -30000}, |
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| 693 | + {1445, -25000}, |
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| 694 | + {1453, -20000}, |
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| 695 | + {1462, -15000}, |
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| 696 | + {1470, -10000}, |
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| 697 | + {1479, -5000}, |
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| 698 | + {1487, 0}, |
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| 699 | + {1496, 5000}, |
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| 700 | + {1504, 10000}, |
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| 701 | + {1512, 15000}, |
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| 702 | + {1521, 20000}, |
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| 703 | + {1529, 25000}, |
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| 704 | + {1538, 30000}, |
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| 705 | + {1546, 35000}, |
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| 706 | + {1555, 40000}, |
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| 707 | + {1563, 45000}, |
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| 708 | + {1572, 50000}, |
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| 709 | + {1580, 55000}, |
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| 710 | + {1589, 60000}, |
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| 711 | + {1598, 65000}, |
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| 712 | + {1606, 70000}, |
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| 713 | + {1615, 75000}, |
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| 714 | + {1623, 80000}, |
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| 715 | + {1632, 85000}, |
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| 716 | + {1640, 90000}, |
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| 717 | + {1648, 95000}, |
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| 718 | + {1657, 100000}, |
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| 719 | + {1666, 105000}, |
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| 720 | + {1674, 110000}, |
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| 721 | + {1682, 115000}, |
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| 722 | + {1691, 120000}, |
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| 723 | + {1699, 125000}, |
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| 724 | + {1793, MAX_TEMP}, |
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| 725 | + {TSADCV2_DATA_MASK, MAX_TEMP}, |
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666 | 726 | }; |
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667 | 727 | |
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668 | 728 | static const struct tsadc_table rk3568_code_table[] = { |
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.. | .. |
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846 | 906 | |
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847 | 907 | /** |
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848 | 908 | * rk_tsadcv2_initialize - initialize TASDC Controller. |
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| 909 | + * @grf: the general register file will be used to do static set by software |
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| 910 | + * @regs: the base address of tsadc controller |
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| 911 | + * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) |
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849 | 912 | * |
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850 | 913 | * (1) Set TSADC_V2_AUTO_PERIOD: |
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851 | 914 | * Configure the interleave between every two accessing of |
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.. | .. |
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880 | 943 | |
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881 | 944 | /** |
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882 | 945 | * rk_tsadcv3_initialize - initialize TASDC Controller. |
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| 946 | + * @grf: the general register file will be used to do static set by software |
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| 947 | + * @regs: the base address of tsadc controller |
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| 948 | + * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) |
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883 | 949 | * |
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884 | 950 | * (1) The tsadc control power sequence. |
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885 | 951 | * |
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.. | .. |
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945 | 1011 | enum tshut_polarity tshut_polarity) |
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946 | 1012 | { |
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947 | 1013 | rk_tsadcv2_initialize(grf, regs, tshut_polarity); |
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948 | | - if (!IS_ERR(grf)) |
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949 | | - regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV); |
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| 1014 | + regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV); |
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950 | 1015 | } |
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951 | 1016 | |
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952 | 1017 | static void rk_tsadcv5_initialize(struct regmap *grf, void __iomem *regs, |
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.. | .. |
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1003 | 1068 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
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1004 | 1069 | regs + TSADCV2_AUTO_CON); |
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1005 | 1070 | |
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| 1071 | + /* |
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| 1072 | + * The general register file will is optional |
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| 1073 | + * and might not be available. |
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| 1074 | + */ |
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1006 | 1075 | if (!IS_ERR(grf)) { |
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1007 | 1076 | regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); |
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| 1077 | + /* |
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| 1078 | + * RK3568 TRM, section 18.5. requires a delay no less |
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| 1079 | + * than 10us between the rising edge of tsadc_tsen_en |
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| 1080 | + * and the rising edge of tsadc_ana_reg_0/1/2. |
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| 1081 | + */ |
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1008 | 1082 | udelay(15); |
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1009 | 1083 | regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); |
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1010 | 1084 | regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); |
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1011 | 1085 | regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); |
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| 1086 | + |
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| 1087 | + /* |
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| 1088 | + * RK3568 TRM, section 18.5. requires a delay no less |
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| 1089 | + * than 90us after the rising edge of tsadc_ana_reg_0/1/2. |
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| 1090 | + */ |
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1012 | 1091 | usleep_range(100, 200); |
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1013 | 1092 | } |
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1014 | 1093 | } |
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.. | .. |
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1035 | 1114 | static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs, |
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1036 | 1115 | enum tshut_polarity tshut_polarity) |
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1037 | 1116 | { |
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| 1117 | + regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN); |
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| 1118 | + udelay(10); |
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| 1119 | + regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA); |
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| 1120 | + udelay(100); |
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| 1121 | + |
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| 1122 | + writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); |
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| 1123 | + writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, |
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| 1124 | + regs + TSADCV3_AUTO_PERIOD_HT); |
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| 1125 | + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, |
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| 1126 | + regs + TSADCV3_HIGHT_INT_DEBOUNCE); |
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| 1127 | + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, |
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| 1128 | + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); |
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| 1129 | + writel_relaxed(TSADCV9_AUTO_SRC, regs + TSADCV2_INT_PD); |
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| 1130 | + writel_relaxed(TSADCV9_PD_MODE, regs + TSADCV9_FLOW_CON); |
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| 1131 | + writel_relaxed(TSADCV9_Q_MAX_VAL, regs + TSADCV9_Q_MAX); |
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| 1132 | + if (tshut_polarity == TSHUT_HIGH_ACTIVE) |
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| 1133 | + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | |
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| 1134 | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, |
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| 1135 | + regs + TSADCV2_AUTO_CON); |
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| 1136 | + else |
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| 1137 | + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, |
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| 1138 | + regs + TSADCV2_AUTO_CON); |
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| 1139 | + writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | (TSADCV3_AUTO_Q_SEL_EN << 16), |
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| 1140 | + regs + TSADCV2_AUTO_CON); |
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| 1141 | +} |
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| 1142 | + |
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| 1143 | +static void rk_tsadcv10_initialize(struct regmap *grf, void __iomem *regs, |
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| 1144 | + enum tshut_polarity tshut_polarity) |
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| 1145 | +{ |
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1038 | 1146 | rk_tsadcv2_initialize(grf, regs, tshut_polarity); |
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1039 | 1147 | if (!IS_ERR(grf)) { |
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1040 | 1148 | regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TDC_MODE); |
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.. | .. |
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1052 | 1160 | regs + TSADCV3_HIGHT_INT_DEBOUNCE); |
---|
1053 | 1161 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, |
---|
1054 | 1162 | regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); |
---|
1055 | | - writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV3_Q_MAX); |
---|
| 1163 | + writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV9_Q_MAX); |
---|
1056 | 1164 | writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, |
---|
1057 | 1165 | regs + TSADCV2_AUTO_CON); |
---|
1058 | 1166 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) |
---|
.. | .. |
---|
1069 | 1177 | regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); |
---|
1070 | 1178 | regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); |
---|
1071 | 1179 | regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); |
---|
| 1180 | + usleep_range(100, 200); |
---|
| 1181 | + } |
---|
| 1182 | +} |
---|
| 1183 | + |
---|
| 1184 | +static void rk_tsadcv12_initialize(struct regmap *grf, void __iomem *regs, |
---|
| 1185 | + enum tshut_polarity tshut_polarity) |
---|
| 1186 | +{ |
---|
| 1187 | + writel_relaxed(TSADCV12_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); |
---|
| 1188 | + writel_relaxed(TSADCV12_AUTO_PERIOD_HT_TIME, |
---|
| 1189 | + regs + TSADCV3_AUTO_PERIOD_HT); |
---|
| 1190 | + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, |
---|
| 1191 | + regs + TSADCV3_HIGHT_INT_DEBOUNCE); |
---|
| 1192 | + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, |
---|
| 1193 | + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); |
---|
| 1194 | + writel_relaxed(TSADCV12_Q_MAX_VAL, regs + TSADCV9_Q_MAX); |
---|
| 1195 | + writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK, |
---|
| 1196 | + regs + TSADCV2_AUTO_CON); |
---|
| 1197 | + if (tshut_polarity == TSHUT_HIGH_ACTIVE) |
---|
| 1198 | + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | |
---|
| 1199 | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, |
---|
| 1200 | + regs + TSADCV2_AUTO_CON); |
---|
| 1201 | + else |
---|
| 1202 | + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, |
---|
| 1203 | + regs + TSADCV2_AUTO_CON); |
---|
| 1204 | + |
---|
| 1205 | + if (!IS_ERR(grf)) { |
---|
| 1206 | + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); |
---|
| 1207 | + udelay(15); |
---|
| 1208 | + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); |
---|
| 1209 | + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); |
---|
| 1210 | + regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); |
---|
1072 | 1211 | usleep_range(100, 200); |
---|
1073 | 1212 | } |
---|
1074 | 1213 | } |
---|
.. | .. |
---|
1115 | 1254 | |
---|
1116 | 1255 | /** |
---|
1117 | 1256 | * rk_tsadcv3_control - the tsadc controller is enabled or disabled. |
---|
| 1257 | + * @regs: the base address of tsadc controller |
---|
| 1258 | + * @enable: boolean flag to enable the controller |
---|
1118 | 1259 | * |
---|
1119 | 1260 | * NOTE: TSADC controller works at auto mode, and some SoCs need set the |
---|
1120 | 1261 | * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output |
---|
.. | .. |
---|
1153 | 1294 | val = readl_relaxed(regs + TSADCV2_DATA(chn)); |
---|
1154 | 1295 | |
---|
1155 | 1296 | return rk_tsadcv2_code_to_temp(table, val, temp); |
---|
1156 | | -} |
---|
1157 | | - |
---|
1158 | | -static int predict_temp(int temp) |
---|
1159 | | -{ |
---|
1160 | | - /* |
---|
1161 | | - * The deviation of prediction. the temperature will not change rapidly, |
---|
1162 | | - * so this cov_q is small |
---|
1163 | | - */ |
---|
1164 | | - int cov_q = 18; |
---|
1165 | | - /* |
---|
1166 | | - * The deviation of tsadc's reading, deviation of tsadc is very big when |
---|
1167 | | - * abnormal temperature is get |
---|
1168 | | - */ |
---|
1169 | | - int cov_r = 542; |
---|
1170 | | - |
---|
1171 | | - int gain; |
---|
1172 | | - int temp_mid; |
---|
1173 | | - int temp_now; |
---|
1174 | | - int prob_mid; |
---|
1175 | | - int prob_now; |
---|
1176 | | - static int temp_last = LOWEST_TEMP; |
---|
1177 | | - static int prob_last = 160; |
---|
1178 | | - static int bounding_cnt; |
---|
1179 | | - |
---|
1180 | | - /* |
---|
1181 | | - * init temp_last with a more suitable value, which mostly equals to |
---|
1182 | | - * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the |
---|
1183 | | - * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal |
---|
1184 | | - * value and temp_last is adjusted to MAX_ENV_TEMP. |
---|
1185 | | - */ |
---|
1186 | | - if (temp_last == LOWEST_TEMP) |
---|
1187 | | - temp_last = min(temp, MAX_ENV_TEMP); |
---|
1188 | | - |
---|
1189 | | - /* |
---|
1190 | | - * Before START_DEBOUNCE_COUNT's samples of temperature, we consider |
---|
1191 | | - * tsadc is stable, i.e. after that, the temperature may be not stable |
---|
1192 | | - * and may have abnormal reading, so we set a bounding temperature. If |
---|
1193 | | - * the reading from tsadc is too big, we set the delta temperature of |
---|
1194 | | - * DEBOUNCE_TEMP/3 comparing to the last temperature. |
---|
1195 | | - */ |
---|
1196 | | - |
---|
1197 | | - if (bounding_cnt++ > START_DEBOUNCE_COUNT) { |
---|
1198 | | - bounding_cnt = START_DEBOUNCE_COUNT; |
---|
1199 | | - if (temp - temp_last > HIGHER_DEBOUNCE_TEMP) |
---|
1200 | | - temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3; |
---|
1201 | | - if (temp_last - temp > LOWER_DEBOUNCE_TEMP) |
---|
1202 | | - temp = temp_last - LOWER_DEBOUNCE_TEMP / 3; |
---|
1203 | | - } |
---|
1204 | | - |
---|
1205 | | - temp_mid = temp_last; |
---|
1206 | | - |
---|
1207 | | - /* calculate the probability of this time's prediction */ |
---|
1208 | | - prob_mid = prob_last + cov_q; |
---|
1209 | | - |
---|
1210 | | - /* calculate the Kalman Gain */ |
---|
1211 | | - gain = (prob_mid * BASE) / (prob_mid + cov_r); |
---|
1212 | | - |
---|
1213 | | - /* calculate the prediction of temperature */ |
---|
1214 | | - temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT; |
---|
1215 | | - |
---|
1216 | | - /* |
---|
1217 | | - * Base on this time's Kalman Gain, ajust our probability of prediction |
---|
1218 | | - * for next time calculation |
---|
1219 | | - */ |
---|
1220 | | - prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT; |
---|
1221 | | - |
---|
1222 | | - prob_last = prob_now; |
---|
1223 | | - temp_last = temp_now; |
---|
1224 | | - |
---|
1225 | | - return temp_last; |
---|
1226 | | -} |
---|
1227 | | - |
---|
1228 | | -static int rk_tsadcv3_get_temp(const struct chip_tsadc_table *table, |
---|
1229 | | - int chn, void __iomem *regs, int *temp) |
---|
1230 | | -{ |
---|
1231 | | - u32 val; |
---|
1232 | | - int ret; |
---|
1233 | | - |
---|
1234 | | - val = readl_relaxed(regs + TSADCV2_DATA(chn)); |
---|
1235 | | - |
---|
1236 | | - ret = rk_tsadcv2_code_to_temp(table, val, temp); |
---|
1237 | | - if (!ret) |
---|
1238 | | - *temp = predict_temp(*temp); |
---|
1239 | | - |
---|
1240 | | - return ret; |
---|
1241 | 1297 | } |
---|
1242 | 1298 | |
---|
1243 | 1299 | static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table, |
---|
.. | .. |
---|
1426 | 1482 | return code - base_code; |
---|
1427 | 1483 | } |
---|
1428 | 1484 | |
---|
| 1485 | +static int rk_tsadcv3_get_trim_code(const struct chip_tsadc_table *table, |
---|
| 1486 | + int code, int trim_base, int trim_base_frac) |
---|
| 1487 | +{ |
---|
| 1488 | + int temp = trim_base * 1000 + trim_base_frac * 100; |
---|
| 1489 | + u32 base_code = rk_tsadcv2_temp_to_code(table, temp); |
---|
| 1490 | + |
---|
| 1491 | + return (TSADCV3_Q_MAX_VAL - code) - base_code; |
---|
| 1492 | +} |
---|
| 1493 | + |
---|
1429 | 1494 | static int rk_tsadcv1_set_clk_rate(struct platform_device *pdev) |
---|
1430 | 1495 | { |
---|
1431 | 1496 | struct clk *clk; |
---|
.. | .. |
---|
1448 | 1513 | |
---|
1449 | 1514 | return 0; |
---|
1450 | 1515 | } |
---|
| 1516 | + |
---|
| 1517 | +static const struct rockchip_tsadc_chip px30_tsadc_data = { |
---|
| 1518 | + .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
---|
| 1519 | + .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
---|
| 1520 | + .chn_num = 2, /* 2 channels for tsadc */ |
---|
| 1521 | + |
---|
| 1522 | + .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ |
---|
| 1523 | + .tshut_temp = 95000, |
---|
| 1524 | + |
---|
| 1525 | + .initialize = rk_tsadcv4_initialize, |
---|
| 1526 | + .irq_ack = rk_tsadcv3_irq_ack, |
---|
| 1527 | + .control = rk_tsadcv3_control, |
---|
| 1528 | + .get_temp = rk_tsadcv2_get_temp, |
---|
| 1529 | + .set_alarm_temp = rk_tsadcv2_alarm_temp, |
---|
| 1530 | + .set_tshut_temp = rk_tsadcv2_tshut_temp, |
---|
| 1531 | + .set_tshut_mode = rk_tsadcv2_tshut_mode, |
---|
| 1532 | + |
---|
| 1533 | + .table = { |
---|
| 1534 | + .id = rk3328_code_table, |
---|
| 1535 | + .length = ARRAY_SIZE(rk3328_code_table), |
---|
| 1536 | + .data_mask = TSADCV2_DATA_MASK, |
---|
| 1537 | + .mode = ADC_INCREMENT, |
---|
| 1538 | + }, |
---|
| 1539 | +}; |
---|
| 1540 | + |
---|
| 1541 | +static const struct rockchip_tsadc_chip px30s_tsadc_data = { |
---|
| 1542 | + .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
---|
| 1543 | + .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
---|
| 1544 | + .chn_num = 2, /* 1 channels for tsadc */ |
---|
| 1545 | + .conversion_time = 2100, /* us */ |
---|
| 1546 | + .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ |
---|
| 1547 | + .tshut_temp = 95000, |
---|
| 1548 | + .initialize = rk_tsadcv10_initialize, |
---|
| 1549 | + .irq_ack = rk_tsadcv3_irq_ack, |
---|
| 1550 | + .control = rk_tsadcv2_control, |
---|
| 1551 | + .get_temp = rk_tsadcv2_get_temp, |
---|
| 1552 | + .set_alarm_temp = rk_tsadcv2_alarm_temp, |
---|
| 1553 | + .set_tshut_temp = rk_tsadcv2_tshut_temp, |
---|
| 1554 | + .set_tshut_mode = rk_tsadcv2_tshut_mode, |
---|
| 1555 | + .set_clk_rate = rk_tsadcv1_set_clk_rate, |
---|
| 1556 | + .table = { |
---|
| 1557 | + .kNum = 2699, |
---|
| 1558 | + .bNum = 2796, |
---|
| 1559 | + .data_mask = TSADCV2_DATA_MASK, |
---|
| 1560 | + .mode = ADC_INCREMENT, |
---|
| 1561 | + }, |
---|
| 1562 | +}; |
---|
| 1563 | + |
---|
| 1564 | +static const struct rockchip_tsadc_chip rv1106_tsadc_data = { |
---|
| 1565 | + /* top, big_core0, big_core1, little_core, center, gpu, npu */ |
---|
| 1566 | + .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
---|
| 1567 | + .chn_num = 1, /* seven channels for tsadc */ |
---|
| 1568 | + .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ |
---|
| 1569 | + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
---|
| 1570 | + .tshut_temp = 95000, |
---|
| 1571 | + .initialize = rk_tsadcv9_initialize, |
---|
| 1572 | + .irq_ack = rk_tsadcv4_irq_ack, |
---|
| 1573 | + .control = rk_tsadcv4_control, |
---|
| 1574 | + .get_temp = rk_tsadcv4_get_temp, |
---|
| 1575 | + .set_alarm_temp = rk_tsadcv3_alarm_temp, |
---|
| 1576 | + .set_tshut_temp = rk_tsadcv3_tshut_temp, |
---|
| 1577 | + .set_tshut_mode = rk_tsadcv4_tshut_mode, |
---|
| 1578 | + .table = { |
---|
| 1579 | + .id = rv1106_code_table, |
---|
| 1580 | + .length = ARRAY_SIZE(rv1106_code_table), |
---|
| 1581 | + .data_mask = TSADCV2_DATA_MASK, |
---|
| 1582 | + .mode = ADC_INCREMENT, |
---|
| 1583 | + }, |
---|
| 1584 | +}; |
---|
1451 | 1585 | |
---|
1452 | 1586 | static const struct rockchip_tsadc_chip rv1108_tsadc_data = { |
---|
1453 | 1587 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
---|
.. | .. |
---|
1559 | 1693 | .initialize = rk_tsadcv2_initialize, |
---|
1560 | 1694 | .irq_ack = rk_tsadcv2_irq_ack, |
---|
1561 | 1695 | .control = rk_tsadcv2_control, |
---|
1562 | | - .get_temp = rk_tsadcv3_get_temp, |
---|
| 1696 | + .get_temp = rk_tsadcv2_get_temp, |
---|
1563 | 1697 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
---|
1564 | 1698 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
---|
1565 | 1699 | .set_tshut_mode = rk_tsadcv2_tshut_mode, |
---|
.. | .. |
---|
1580 | 1714 | .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ |
---|
1581 | 1715 | .tshut_temp = 95000, |
---|
1582 | 1716 | |
---|
1583 | | - .initialize = rk_tsadcv4_initialize, |
---|
| 1717 | + .initialize = rk_tsadcv2_initialize, |
---|
1584 | 1718 | .irq_ack = rk_tsadcv3_irq_ack, |
---|
1585 | 1719 | .control = rk_tsadcv3_control, |
---|
1586 | 1720 | .get_temp = rk_tsadcv2_get_temp, |
---|
.. | .. |
---|
1596 | 1730 | }, |
---|
1597 | 1731 | }; |
---|
1598 | 1732 | |
---|
1599 | | -static const struct rockchip_tsadc_chip px30_tsadc_data = { |
---|
| 1733 | +static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = { |
---|
1600 | 1734 | .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
---|
1601 | | - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
---|
1602 | | - .chn_num = 2, /* 2 channels for tsadc */ |
---|
| 1735 | + .chn_num = 1, /* 1 channels for tsadc */ |
---|
1603 | 1736 | |
---|
1604 | | - .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ |
---|
1605 | | - .tshut_temp = 95000, |
---|
1606 | | - |
---|
1607 | | - .initialize = rk_tsadcv4_initialize, |
---|
1608 | | - .irq_ack = rk_tsadcv3_irq_ack, |
---|
1609 | | - .control = rk_tsadcv3_control, |
---|
1610 | | - .get_temp = rk_tsadcv2_get_temp, |
---|
1611 | | - .set_alarm_temp = rk_tsadcv2_alarm_temp, |
---|
1612 | | - .set_tshut_temp = rk_tsadcv2_tshut_temp, |
---|
1613 | | - .set_tshut_mode = rk_tsadcv2_tshut_mode, |
---|
1614 | | - |
---|
1615 | | - .table = { |
---|
1616 | | - .id = rk3328_code_table, |
---|
1617 | | - .length = ARRAY_SIZE(rk3328_code_table), |
---|
1618 | | - .data_mask = TSADCV2_DATA_MASK, |
---|
1619 | | - .mode = ADC_INCREMENT, |
---|
1620 | | - }, |
---|
1621 | | -}; |
---|
1622 | | - |
---|
1623 | | -static const struct rockchip_tsadc_chip px30s_tsadc_data = { |
---|
1624 | | - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
---|
1625 | | - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ |
---|
1626 | | - .chn_num = 2, /* 1 channels for tsadc */ |
---|
1627 | 1737 | .conversion_time = 2100, /* us */ |
---|
| 1738 | + |
---|
1628 | 1739 | .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ |
---|
1629 | 1740 | .tshut_temp = 95000, |
---|
1630 | | - .initialize = rk_tsadcv9_initialize, |
---|
| 1741 | + |
---|
| 1742 | + .initialize = rk_tsadcv2_initialize, |
---|
1631 | 1743 | .irq_ack = rk_tsadcv3_irq_ack, |
---|
1632 | 1744 | .control = rk_tsadcv2_control, |
---|
1633 | 1745 | .get_temp = rk_tsadcv2_get_temp, |
---|
.. | .. |
---|
1635 | 1747 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
---|
1636 | 1748 | .set_tshut_mode = rk_tsadcv2_tshut_mode, |
---|
1637 | 1749 | .set_clk_rate = rk_tsadcv1_set_clk_rate, |
---|
| 1750 | + |
---|
1638 | 1751 | .table = { |
---|
1639 | 1752 | .kNum = 2699, |
---|
1640 | 1753 | .bNum = 2796, |
---|
.. | .. |
---|
1756 | 1869 | .set_alarm_temp = rk_tsadcv3_alarm_temp, |
---|
1757 | 1870 | .set_tshut_temp = rk_tsadcv3_tshut_temp, |
---|
1758 | 1871 | .set_tshut_mode = rk_tsadcv4_tshut_mode, |
---|
| 1872 | + .get_trim_code = rk_tsadcv3_get_trim_code, |
---|
| 1873 | + .trim_slope = 574, |
---|
1759 | 1874 | |
---|
1760 | 1875 | .table = { |
---|
1761 | 1876 | .id = rk3528_code_table, |
---|
1762 | 1877 | .length = ARRAY_SIZE(rk3528_code_table), |
---|
| 1878 | + .data_mask = TSADCV2_DATA_MASK, |
---|
| 1879 | + .mode = ADC_INCREMENT, |
---|
| 1880 | + }, |
---|
| 1881 | +}; |
---|
| 1882 | + |
---|
| 1883 | +static const struct rockchip_tsadc_chip rk3562_tsadc_data = { |
---|
| 1884 | + .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ |
---|
| 1885 | + .chn_num = 1, /* one channels for tsadc */ |
---|
| 1886 | + |
---|
| 1887 | + .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */ |
---|
| 1888 | + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ |
---|
| 1889 | + .tshut_temp = 95000, |
---|
| 1890 | + |
---|
| 1891 | + .initialize = rk_tsadcv12_initialize, |
---|
| 1892 | + .irq_ack = rk_tsadcv4_irq_ack, |
---|
| 1893 | + .control = rk_tsadcv4_control, |
---|
| 1894 | + .get_temp = rk_tsadcv4_get_temp, |
---|
| 1895 | + .set_alarm_temp = rk_tsadcv3_alarm_temp, |
---|
| 1896 | + .set_tshut_temp = rk_tsadcv3_tshut_temp, |
---|
| 1897 | + .set_tshut_mode = rk_tsadcv4_tshut_mode, |
---|
| 1898 | + .get_trim_code = rk_tsadcv3_get_trim_code, |
---|
| 1899 | + .trim_slope = 588, |
---|
| 1900 | + |
---|
| 1901 | + .table = { |
---|
| 1902 | + .id = rk3562_code_table, |
---|
| 1903 | + .length = ARRAY_SIZE(rk3562_code_table), |
---|
1763 | 1904 | .data_mask = TSADCV2_DATA_MASK, |
---|
1764 | 1905 | .mode = ADC_INCREMENT, |
---|
1765 | 1906 | }, |
---|
.. | .. |
---|
1815 | 1956 | }; |
---|
1816 | 1957 | |
---|
1817 | 1958 | static const struct of_device_id of_rockchip_thermal_match[] = { |
---|
1818 | | -#ifdef CONFIG_CPU_RV110X |
---|
| 1959 | +#ifdef CONFIG_CPU_PX30 |
---|
| 1960 | + { .compatible = "rockchip,px30-tsadc", |
---|
| 1961 | + .data = (void *)&px30_tsadc_data, |
---|
| 1962 | + }, |
---|
| 1963 | + { .compatible = "rockchip,px30s-tsadc", |
---|
| 1964 | + .data = (void *)&px30s_tsadc_data, |
---|
| 1965 | + }, |
---|
| 1966 | +#endif |
---|
| 1967 | +#ifdef CONFIG_CPU_RV1106 |
---|
| 1968 | + { |
---|
| 1969 | + .compatible = "rockchip,rv1106-tsadc", |
---|
| 1970 | + .data = (void *)&rv1106_tsadc_data, |
---|
| 1971 | + }, |
---|
| 1972 | +#endif |
---|
| 1973 | +#ifdef CONFIG_CPU_RV1108 |
---|
1819 | 1974 | { |
---|
1820 | 1975 | .compatible = "rockchip,rv1108-tsadc", |
---|
1821 | 1976 | .data = (void *)&rv1108_tsadc_data, |
---|
.. | .. |
---|
1825 | 1980 | { |
---|
1826 | 1981 | .compatible = "rockchip,rv1126-tsadc", |
---|
1827 | 1982 | .data = (void *)&rv1126_tsadc_data, |
---|
1828 | | - }, |
---|
1829 | | -#endif |
---|
1830 | | -#ifdef CONFIG_CPU_PX30 |
---|
1831 | | - { .compatible = "rockchip,px30-tsadc", |
---|
1832 | | - .data = (void *)&px30_tsadc_data, |
---|
1833 | | - }, |
---|
1834 | | - { .compatible = "rockchip,px30s-tsadc", |
---|
1835 | | - .data = (void *)&px30s_tsadc_data, |
---|
1836 | 1983 | }, |
---|
1837 | 1984 | #endif |
---|
1838 | 1985 | #ifdef CONFIG_CPU_RK1808 |
---|
.. | .. |
---|
1857 | 2004 | { |
---|
1858 | 2005 | .compatible = "rockchip,rk3308-tsadc", |
---|
1859 | 2006 | .data = (void *)&rk3308_tsadc_data, |
---|
| 2007 | + }, |
---|
| 2008 | + { |
---|
| 2009 | + .compatible = "rockchip,rk3308bs-tsadc", |
---|
| 2010 | + .data = (void *)&rk3308bs_tsadc_data, |
---|
1860 | 2011 | }, |
---|
1861 | 2012 | #endif |
---|
1862 | 2013 | #ifdef CONFIG_CPU_RK3328 |
---|
.. | .. |
---|
1889 | 2040 | .data = (void *)&rk3528_tsadc_data, |
---|
1890 | 2041 | }, |
---|
1891 | 2042 | #endif |
---|
| 2043 | +#ifdef CONFIG_CPU_RK3562 |
---|
| 2044 | + { |
---|
| 2045 | + .compatible = "rockchip,rk3562-tsadc", |
---|
| 2046 | + .data = (void *)&rk3562_tsadc_data, |
---|
| 2047 | + }, |
---|
| 2048 | +#endif |
---|
1892 | 2049 | #ifdef CONFIG_CPU_RK3568 |
---|
1893 | 2050 | { |
---|
1894 | 2051 | .compatible = "rockchip,rk3568-tsadc", |
---|
.. | .. |
---|
1910 | 2067 | { |
---|
1911 | 2068 | struct thermal_zone_device *tzd = sensor->tzd; |
---|
1912 | 2069 | |
---|
1913 | | - tzd->ops->set_mode(tzd, |
---|
1914 | | - on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); |
---|
| 2070 | + if (on) |
---|
| 2071 | + thermal_zone_device_enable(tzd); |
---|
| 2072 | + else |
---|
| 2073 | + thermal_zone_device_disable(tzd); |
---|
1915 | 2074 | } |
---|
1916 | 2075 | |
---|
1917 | 2076 | static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) |
---|
.. | .. |
---|
2021 | 2180 | * The tsadc won't to handle the error in here |
---|
2022 | 2181 | * since some SoCs didn't need this property. |
---|
2023 | 2182 | */ |
---|
2024 | | - if (rockchip_get_efuse_value(np, "trim_base", &trim_base)) { |
---|
2025 | | - dev_info(dev, "Missing trim_base property\n"); |
---|
2026 | | - return 0; |
---|
2027 | | - } |
---|
| 2183 | + rockchip_get_efuse_value(np, "trim_base", &trim_base); |
---|
2028 | 2184 | if (!trim_base) |
---|
2029 | | - return 0; |
---|
| 2185 | + trim_base = 30; |
---|
2030 | 2186 | rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac); |
---|
2031 | 2187 | /* |
---|
2032 | 2188 | * If the tsadc node contains trim_h and trim_l property, |
---|
.. | .. |
---|
2182 | 2338 | |
---|
2183 | 2339 | /** |
---|
2184 | 2340 | * Reset TSADC Controller, reset all tsadc registers. |
---|
| 2341 | + * @reset: the reset controller of tsadc |
---|
2185 | 2342 | */ |
---|
2186 | 2343 | static void rockchip_thermal_reset_controller(struct reset_control *reset) |
---|
2187 | 2344 | { |
---|
.. | .. |
---|
2242 | 2399 | return -ENXIO; |
---|
2243 | 2400 | |
---|
2244 | 2401 | irq = platform_get_irq(pdev, 0); |
---|
2245 | | - if (irq < 0) { |
---|
2246 | | - dev_err(&pdev->dev, "no irq resource?\n"); |
---|
| 2402 | + if (irq < 0) |
---|
2247 | 2403 | return -EINVAL; |
---|
2248 | | - } |
---|
2249 | 2404 | |
---|
2250 | 2405 | thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), |
---|
2251 | 2406 | GFP_KERNEL); |
---|
.. | .. |
---|
2259 | 2414 | return -EINVAL; |
---|
2260 | 2415 | if (soc_is_px30s()) |
---|
2261 | 2416 | thermal->chip = &px30s_tsadc_data; |
---|
| 2417 | + if (soc_is_rk3308bs()) |
---|
| 2418 | + thermal->chip = &rk3308bs_tsadc_data; |
---|
2262 | 2419 | |
---|
2263 | 2420 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
---|
2264 | 2421 | thermal->regs = devm_ioremap_resource(&pdev->dev, res); |
---|
.. | .. |
---|
2346 | 2503 | usleep_range(thermal->chip->conversion_time, |
---|
2347 | 2504 | thermal->chip->conversion_time + 50); |
---|
2348 | 2505 | |
---|
2349 | | - for (i = 0; i < thermal->chip->chn_num; i++) |
---|
| 2506 | + for (i = 0; i < thermal->chip->chn_num; i++) { |
---|
2350 | 2507 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
---|
| 2508 | + thermal->sensors[i].tzd->tzp->no_hwmon = false; |
---|
| 2509 | + error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd); |
---|
| 2510 | + if (error) |
---|
| 2511 | + dev_warn(&pdev->dev, |
---|
| 2512 | + "failed to register sensor %d with hwmon: %d\n", |
---|
| 2513 | + i, error); |
---|
| 2514 | + } |
---|
2351 | 2515 | |
---|
2352 | 2516 | thermal->panic_nb.notifier_call = rockchip_thermal_panic; |
---|
2353 | 2517 | atomic_notifier_chain_register(&panic_notifier_list, |
---|
.. | .. |
---|
2371 | 2535 | for (i = 0; i < thermal->chip->chn_num; i++) { |
---|
2372 | 2536 | struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; |
---|
2373 | 2537 | |
---|
| 2538 | + thermal_remove_hwmon_sysfs(sensor->tzd); |
---|
2374 | 2539 | rockchip_thermal_toggle_sensor(sensor, false); |
---|
2375 | 2540 | } |
---|
2376 | 2541 | |
---|
.. | .. |
---|
2400 | 2565 | |
---|
2401 | 2566 | static int __maybe_unused rockchip_thermal_suspend(struct device *dev) |
---|
2402 | 2567 | { |
---|
2403 | | - struct platform_device *pdev = to_platform_device(dev); |
---|
2404 | | - struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); |
---|
| 2568 | + struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); |
---|
2405 | 2569 | int i; |
---|
2406 | 2570 | |
---|
2407 | 2571 | for (i = 0; i < thermal->chip->chn_num; i++) |
---|
.. | .. |
---|
2419 | 2583 | |
---|
2420 | 2584 | static int __maybe_unused rockchip_thermal_resume(struct device *dev) |
---|
2421 | 2585 | { |
---|
2422 | | - struct platform_device *pdev = to_platform_device(dev); |
---|
2423 | | - struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); |
---|
| 2586 | + struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); |
---|
2424 | 2587 | int i; |
---|
2425 | 2588 | int error; |
---|
2426 | 2589 | |
---|
2427 | 2590 | error = clk_bulk_enable(thermal->num_clks, thermal->clks); |
---|
2428 | 2591 | if (error) { |
---|
2429 | | - dev_err(&pdev->dev, "failed to enable tsadc bulk clks: %d\n", |
---|
| 2592 | + dev_err(dev, "failed to enable tsadc bulk clks: %d\n", |
---|
2430 | 2593 | error); |
---|
2431 | 2594 | return error; |
---|
2432 | 2595 | } |
---|
.. | .. |
---|
2447 | 2610 | id, thermal->regs, |
---|
2448 | 2611 | tshut_temp); |
---|
2449 | 2612 | if (error) |
---|
2450 | | - dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", |
---|
| 2613 | + dev_err(dev, "%s: invalid tshut=%d, error=%d\n", |
---|
2451 | 2614 | __func__, tshut_temp, error); |
---|
2452 | 2615 | } |
---|
2453 | 2616 | |
---|
.. | .. |
---|
2479 | 2642 | .shutdown = rockchip_thermal_shutdown, |
---|
2480 | 2643 | }; |
---|
2481 | 2644 | |
---|
2482 | | -module_platform_driver(rockchip_thermal_driver); |
---|
| 2645 | +static int __init rockchip_thermal_driver_init(void) |
---|
| 2646 | +{ |
---|
| 2647 | + return platform_driver_register(&rockchip_thermal_driver); |
---|
| 2648 | +} |
---|
| 2649 | +rootfs_initcall(rockchip_thermal_driver_init); |
---|
| 2650 | + |
---|
| 2651 | +static void __exit rockchip_thermal_driver_exit(void) |
---|
| 2652 | +{ |
---|
| 2653 | + platform_driver_unregister(&rockchip_thermal_driver); |
---|
| 2654 | +} |
---|
| 2655 | +module_exit(rockchip_thermal_driver_exit); |
---|
2483 | 2656 | |
---|
2484 | 2657 | MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); |
---|
2485 | 2658 | MODULE_AUTHOR("Rockchip, Inc."); |
---|