forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e
kernel/drivers/thermal/rockchip_thermal.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
34 * Caesar Wang <wxt@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12
- * more details.
135 */
146
157 #include <linux/clk.h>
....@@ -29,7 +21,7 @@
2921 #include <linux/pinctrl/consumer.h>
3022 #include <linux/nvmem-consumer.h>
3123
32
-/**
24
+/*
3325 * If the temperature over a period of time High,
3426 * the resulting TSHUT gave CRU module,let it reset the entire chip,
3527 * or via GPIO give PMIC.
....@@ -39,7 +31,7 @@
3931 TSHUT_MODE_OTP,
4032 };
4133
42
-/**
34
+/*
4335 * The system Temperature Sensors tshut(tshut) polarity
4436 * the bit 8 is tshut polarity.
4537 * 0: low active, 1: high active
....@@ -49,7 +41,7 @@
4941 TSHUT_HIGH_ACTIVE,
5042 };
5143
52
-/**
44
+/*
5345 * The system has two Temperature Sensors.
5446 * sensor0 is for CPU, and sensor1 is for GPU.
5547 */
....@@ -58,7 +50,7 @@
5850 SENSOR_GPU,
5951 };
6052
61
-/**
53
+/*
6254 * The conversion table has the adc value and temperature.
6355 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
6456 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
....@@ -67,6 +59,8 @@
6759 ADC_DECREMENT = 0,
6860 ADC_INCREMENT,
6961 };
62
+
63
+#include "thermal_hwmon.h"
7064
7165 /**
7266 * The max sensors is seven in rockchip SoCs.
....@@ -78,6 +72,8 @@
7872 * @id: conversion table
7973 * @length: size of conversion table
8074 * @data_mask: mask to apply on data inputs
75
+ * @kNum: linear parameter k
76
+ * @bNum: linear parameter b
8177 * @mode: sort mode of this adc variant (incrementing or decrementing)
8278 */
8379 struct chip_tsadc_table {
....@@ -92,7 +88,7 @@
9288
9389 /**
9490 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
95
- * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel
91
+ * @chn_id: array of sensor ids of chip corresponding to the channel
9692 * @chn_num: the channel number of tsadc chip
9793 * @conversion_time: the conversion time of tsadc
9894 * @trim_slope: use to conversion trim code to trim temp
....@@ -101,6 +97,7 @@
10197 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
10298 * @initialize: SoC special initialize tsadc controller method
10399 * @irq_ack: clear the interrupt
100
+ * @control: enable/disable method for the tsadc controller
104101 * @get_temp: get the temperature
105102 * @set_alarm_temp: set the high temperature interrupt
106103 * @set_tshut_temp: set the hardware-controlled shutdown temperature
....@@ -169,13 +166,17 @@
169166 * @chip: pointer to the platform/configuration data
170167 * @pdev: platform device of thermal
171168 * @reset: the reset controller of tsadc
172
- * @sensors[SOC_MAX_SENSORS]: the thermal sensor
173
- * @clk: the controller clock is divided by the exteral 24MHz
174
- * @pclk: the advanced peripherals bus clock
169
+ * @sensors: array of thermal sensors
170
+ * @clk: the bulk clk of tsadc, include controller clock and peripherals bus clock
171
+ * @num_clks: the number of tsadc clks
175172 * @grf: the general register file will be used to do static set by software
176173 * @regs: the base address of tsadc controller
177174 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
178175 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
176
+ * @pinctrl: the pinctrl of tsadc
177
+ * @gpio_state: pinctrl select gpio function
178
+ * @otp_state: pinctrl select otp out function
179
+ * @panic_nb: panic notifier block
179180 */
180181 struct rockchip_thermal_data {
181182 const struct rockchip_tsadc_chip *chip;
....@@ -230,7 +231,8 @@
230231 #define TSADCV2_AUTO_PERIOD_HT 0x6c
231232 #define TSADCV3_AUTO_PERIOD 0x154
232233 #define TSADCV3_AUTO_PERIOD_HT 0x158
233
-#define TSADCV3_Q_MAX 0x210
234
+#define TSADCV9_Q_MAX 0x210
235
+#define TSADCV9_FLOW_CON 0x218
234236
235237 #define TSADCV2_AUTO_EN BIT(0)
236238 #define TSADCV2_AUTO_EN_MASK BIT(16)
....@@ -269,10 +271,17 @@
269271 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
270272 #define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
271273 #define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
274
+#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */
275
+#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
272276 #define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
277
+#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
273278
274279 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
275280 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
281
+
282
+#define TSADCV9_AUTO_SRC (0x10001 << 0)
283
+#define TSADCV9_PD_MODE (0x10001 << 4)
284
+#define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
276285
277286 #define GRF_SARADC_TESTBIT 0x0e644
278287 #define GRF_TSADC_TESTBIT_L 0x0e648
....@@ -283,12 +292,19 @@
283292
284293 #define RK1808_BUS_GRF_SOC_CON0 0x0400
285294
286
-#define RK3568_GRF_TSADC_CON 0x0600
287295 #define RK3528_GRF_TSADC_CON 0x40030
296
+
297
+#define RK3562_GRF_TSADC_CON 0x0580
298
+
299
+#define RK3568_GRF_TSADC_CON 0x0600
288300 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
289301 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
290302 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
291303 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
304
+
305
+#define RV1106_VOGRF_TSADC_CON 0x6000C
306
+#define RV1106_VOGRF_TSADC_TSEN (0x10001 << 8)
307
+#define RV1106_VOGRF_TSADC_ANA (0xff0007 << 0)
292308
293309 #define RV1126_GRF0_TSADC_CON 0x0100
294310
....@@ -309,15 +325,7 @@
309325
310326 /* -40 to 125 is reliable, outside the range existed unreliability */
311327 #define MIN_TEMP (-60000)
312
-#define LOWEST_TEMP (-273000)
313328 #define MAX_TEMP (180000)
314
-#define MAX_ENV_TEMP (85000)
315
-
316
-#define BASE (1024)
317
-#define BASE_SHIFT (10)
318
-#define START_DEBOUNCE_COUNT (100)
319
-#define HIGHER_DEBOUNCE_TEMP (30000)
320
-#define LOWER_DEBOUNCE_TEMP (15000)
321329
322330 /**
323331 * struct tsadc_table - code to temperature conversion table
....@@ -332,6 +340,17 @@
332340 struct tsadc_table {
333341 u32 code;
334342 int temp;
343
+};
344
+
345
+static const struct tsadc_table rv1106_code_table[] = {
346
+ {0, MIN_TEMP},
347
+ {363, MIN_TEMP},
348
+ {396, -40000},
349
+ {504, 25000},
350
+ {605, 85000},
351
+ {673, 125000},
352
+ {758, MAX_TEMP},
353
+ {TSADCV2_DATA_MASK, MAX_TEMP},
335354 };
336355
337356 static const struct tsadc_table rv1108_table[] = {
....@@ -627,42 +646,83 @@
627646 static const struct tsadc_table rk3528_code_table[] = {
628647 {0, MIN_TEMP},
629648 {1386, MIN_TEMP},
630
- {1419, -40000},
631
- {1427, -35000},
632
- {1435, -30000},
633
- {1443, -25000},
634
- {1452, -20000},
635
- {1460, -15000},
636
- {1468, -10000},
637
- {1477, -5000},
638
- {1486, 0},
639
- {1494, 5000},
640
- {1502, 10000},
641
- {1510, 15000},
642
- {1519, 20000},
643
- {1527, 25000},
644
- {1535, 30000},
645
- {1544, 35000},
646
- {1552, 40000},
647
- {1561, 45000},
648
- {1569, 50000},
649
- {1578, 55000},
650
- {1586, 60000},
651
- {1594, 65000},
652
- {1603, 70000},
653
- {1612, 75000},
654
- {1620, 80000},
649
+ {1410, -40000},
650
+ {1419, -35000},
651
+ {1428, -30000},
652
+ {1436, -25000},
653
+ {1445, -20000},
654
+ {1454, -15000},
655
+ {1463, -10000},
656
+ {1471, -5000},
657
+ {1480, 0},
658
+ {1489, 5000},
659
+ {1498, 10000},
660
+ {1506, 15000},
661
+ {1515, 20000},
662
+ {1524, 25000},
663
+ {1533, 30000},
664
+ {1541, 35000},
665
+ {1550, 40000},
666
+ {1558, 45000},
667
+ {1567, 50000},
668
+ {1575, 55000},
669
+ {1584, 60000},
670
+ {1593, 65000},
671
+ {1602, 70000},
672
+ {1610, 75000},
673
+ {1619, 80000},
655674 {1628, 85000},
656675 {1637, 90000},
657676 {1646, 95000},
658677 {1654, 100000},
659
- {1662, 105000},
660
- {1671, 110000},
661
- {1679, 115000},
662
- {1688, 120000},
663
- {1696, 125000},
678
+ {1663, 105000},
679
+ {1672, 110000},
680
+ {1680, 115000},
681
+ {1689, 120000},
682
+ {1697, 125000},
664683 {1790, MAX_TEMP},
665684 {TSADCV5_DATA_MASK, MAX_TEMP},
685
+};
686
+
687
+static const struct tsadc_table rk3562_code_table[] = {
688
+ {0, MIN_TEMP},
689
+ {1385, MIN_TEMP},
690
+ {1419, -40000},
691
+ {1428, -35000},
692
+ {1436, -30000},
693
+ {1445, -25000},
694
+ {1453, -20000},
695
+ {1462, -15000},
696
+ {1470, -10000},
697
+ {1479, -5000},
698
+ {1487, 0},
699
+ {1496, 5000},
700
+ {1504, 10000},
701
+ {1512, 15000},
702
+ {1521, 20000},
703
+ {1529, 25000},
704
+ {1538, 30000},
705
+ {1546, 35000},
706
+ {1555, 40000},
707
+ {1563, 45000},
708
+ {1572, 50000},
709
+ {1580, 55000},
710
+ {1589, 60000},
711
+ {1598, 65000},
712
+ {1606, 70000},
713
+ {1615, 75000},
714
+ {1623, 80000},
715
+ {1632, 85000},
716
+ {1640, 90000},
717
+ {1648, 95000},
718
+ {1657, 100000},
719
+ {1666, 105000},
720
+ {1674, 110000},
721
+ {1682, 115000},
722
+ {1691, 120000},
723
+ {1699, 125000},
724
+ {1793, MAX_TEMP},
725
+ {TSADCV2_DATA_MASK, MAX_TEMP},
666726 };
667727
668728 static const struct tsadc_table rk3568_code_table[] = {
....@@ -846,6 +906,9 @@
846906
847907 /**
848908 * rk_tsadcv2_initialize - initialize TASDC Controller.
909
+ * @grf: the general register file will be used to do static set by software
910
+ * @regs: the base address of tsadc controller
911
+ * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
849912 *
850913 * (1) Set TSADC_V2_AUTO_PERIOD:
851914 * Configure the interleave between every two accessing of
....@@ -880,6 +943,9 @@
880943
881944 /**
882945 * rk_tsadcv3_initialize - initialize TASDC Controller.
946
+ * @grf: the general register file will be used to do static set by software
947
+ * @regs: the base address of tsadc controller
948
+ * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
883949 *
884950 * (1) The tsadc control power sequence.
885951 *
....@@ -945,8 +1011,7 @@
9451011 enum tshut_polarity tshut_polarity)
9461012 {
9471013 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
948
- if (!IS_ERR(grf))
949
- regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
1014
+ regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
9501015 }
9511016
9521017 static void rk_tsadcv5_initialize(struct regmap *grf, void __iomem *regs,
....@@ -1003,12 +1068,26 @@
10031068 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
10041069 regs + TSADCV2_AUTO_CON);
10051070
1071
+ /*
1072
+ * The general register file will is optional
1073
+ * and might not be available.
1074
+ */
10061075 if (!IS_ERR(grf)) {
10071076 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1077
+ /*
1078
+ * RK3568 TRM, section 18.5. requires a delay no less
1079
+ * than 10us between the rising edge of tsadc_tsen_en
1080
+ * and the rising edge of tsadc_ana_reg_0/1/2.
1081
+ */
10081082 udelay(15);
10091083 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
10101084 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
10111085 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1086
+
1087
+ /*
1088
+ * RK3568 TRM, section 18.5. requires a delay no less
1089
+ * than 90us after the rising edge of tsadc_ana_reg_0/1/2.
1090
+ */
10121091 usleep_range(100, 200);
10131092 }
10141093 }
....@@ -1035,6 +1114,35 @@
10351114 static void rk_tsadcv9_initialize(struct regmap *grf, void __iomem *regs,
10361115 enum tshut_polarity tshut_polarity)
10371116 {
1117
+ regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_TSEN);
1118
+ udelay(10);
1119
+ regmap_write(grf, RV1106_VOGRF_TSADC_CON, RV1106_VOGRF_TSADC_ANA);
1120
+ udelay(100);
1121
+
1122
+ writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1123
+ writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
1124
+ regs + TSADCV3_AUTO_PERIOD_HT);
1125
+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1126
+ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1127
+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1128
+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1129
+ writel_relaxed(TSADCV9_AUTO_SRC, regs + TSADCV2_INT_PD);
1130
+ writel_relaxed(TSADCV9_PD_MODE, regs + TSADCV9_FLOW_CON);
1131
+ writel_relaxed(TSADCV9_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
1132
+ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1133
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1134
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1135
+ regs + TSADCV2_AUTO_CON);
1136
+ else
1137
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1138
+ regs + TSADCV2_AUTO_CON);
1139
+ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | (TSADCV3_AUTO_Q_SEL_EN << 16),
1140
+ regs + TSADCV2_AUTO_CON);
1141
+}
1142
+
1143
+static void rk_tsadcv10_initialize(struct regmap *grf, void __iomem *regs,
1144
+ enum tshut_polarity tshut_polarity)
1145
+{
10381146 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
10391147 if (!IS_ERR(grf)) {
10401148 regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TDC_MODE);
....@@ -1052,7 +1160,7 @@
10521160 regs + TSADCV3_HIGHT_INT_DEBOUNCE);
10531161 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
10541162 regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1055
- writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV3_Q_MAX);
1163
+ writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
10561164 writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
10571165 regs + TSADCV2_AUTO_CON);
10581166 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
....@@ -1069,6 +1177,37 @@
10691177 regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
10701178 regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
10711179 regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
1180
+ usleep_range(100, 200);
1181
+ }
1182
+}
1183
+
1184
+static void rk_tsadcv12_initialize(struct regmap *grf, void __iomem *regs,
1185
+ enum tshut_polarity tshut_polarity)
1186
+{
1187
+ writel_relaxed(TSADCV12_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
1188
+ writel_relaxed(TSADCV12_AUTO_PERIOD_HT_TIME,
1189
+ regs + TSADCV3_AUTO_PERIOD_HT);
1190
+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
1191
+ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
1192
+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
1193
+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
1194
+ writel_relaxed(TSADCV12_Q_MAX_VAL, regs + TSADCV9_Q_MAX);
1195
+ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
1196
+ regs + TSADCV2_AUTO_CON);
1197
+ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
1198
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
1199
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1200
+ regs + TSADCV2_AUTO_CON);
1201
+ else
1202
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
1203
+ regs + TSADCV2_AUTO_CON);
1204
+
1205
+ if (!IS_ERR(grf)) {
1206
+ regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
1207
+ udelay(15);
1208
+ regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
1209
+ regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
1210
+ regmap_write(grf, RK3562_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
10721211 usleep_range(100, 200);
10731212 }
10741213 }
....@@ -1115,6 +1254,8 @@
11151254
11161255 /**
11171256 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
1257
+ * @regs: the base address of tsadc controller
1258
+ * @enable: boolean flag to enable the controller
11181259 *
11191260 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
11201261 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
....@@ -1153,91 +1294,6 @@
11531294 val = readl_relaxed(regs + TSADCV2_DATA(chn));
11541295
11551296 return rk_tsadcv2_code_to_temp(table, val, temp);
1156
-}
1157
-
1158
-static int predict_temp(int temp)
1159
-{
1160
- /*
1161
- * The deviation of prediction. the temperature will not change rapidly,
1162
- * so this cov_q is small
1163
- */
1164
- int cov_q = 18;
1165
- /*
1166
- * The deviation of tsadc's reading, deviation of tsadc is very big when
1167
- * abnormal temperature is get
1168
- */
1169
- int cov_r = 542;
1170
-
1171
- int gain;
1172
- int temp_mid;
1173
- int temp_now;
1174
- int prob_mid;
1175
- int prob_now;
1176
- static int temp_last = LOWEST_TEMP;
1177
- static int prob_last = 160;
1178
- static int bounding_cnt;
1179
-
1180
- /*
1181
- * init temp_last with a more suitable value, which mostly equals to
1182
- * temp reading from tsadc, but not higher than MAX_ENV_TEMP. If the
1183
- * temp is higher than MAX_ENV_TEMP, it is assumed to be abnormal
1184
- * value and temp_last is adjusted to MAX_ENV_TEMP.
1185
- */
1186
- if (temp_last == LOWEST_TEMP)
1187
- temp_last = min(temp, MAX_ENV_TEMP);
1188
-
1189
- /*
1190
- * Before START_DEBOUNCE_COUNT's samples of temperature, we consider
1191
- * tsadc is stable, i.e. after that, the temperature may be not stable
1192
- * and may have abnormal reading, so we set a bounding temperature. If
1193
- * the reading from tsadc is too big, we set the delta temperature of
1194
- * DEBOUNCE_TEMP/3 comparing to the last temperature.
1195
- */
1196
-
1197
- if (bounding_cnt++ > START_DEBOUNCE_COUNT) {
1198
- bounding_cnt = START_DEBOUNCE_COUNT;
1199
- if (temp - temp_last > HIGHER_DEBOUNCE_TEMP)
1200
- temp = temp_last + HIGHER_DEBOUNCE_TEMP / 3;
1201
- if (temp_last - temp > LOWER_DEBOUNCE_TEMP)
1202
- temp = temp_last - LOWER_DEBOUNCE_TEMP / 3;
1203
- }
1204
-
1205
- temp_mid = temp_last;
1206
-
1207
- /* calculate the probability of this time's prediction */
1208
- prob_mid = prob_last + cov_q;
1209
-
1210
- /* calculate the Kalman Gain */
1211
- gain = (prob_mid * BASE) / (prob_mid + cov_r);
1212
-
1213
- /* calculate the prediction of temperature */
1214
- temp_now = (temp_mid * BASE + gain * (temp - temp_mid)) >> BASE_SHIFT;
1215
-
1216
- /*
1217
- * Base on this time's Kalman Gain, ajust our probability of prediction
1218
- * for next time calculation
1219
- */
1220
- prob_now = ((BASE - gain) * prob_mid) >> BASE_SHIFT;
1221
-
1222
- prob_last = prob_now;
1223
- temp_last = temp_now;
1224
-
1225
- return temp_last;
1226
-}
1227
-
1228
-static int rk_tsadcv3_get_temp(const struct chip_tsadc_table *table,
1229
- int chn, void __iomem *regs, int *temp)
1230
-{
1231
- u32 val;
1232
- int ret;
1233
-
1234
- val = readl_relaxed(regs + TSADCV2_DATA(chn));
1235
-
1236
- ret = rk_tsadcv2_code_to_temp(table, val, temp);
1237
- if (!ret)
1238
- *temp = predict_temp(*temp);
1239
-
1240
- return ret;
12411297 }
12421298
12431299 static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
....@@ -1426,6 +1482,15 @@
14261482 return code - base_code;
14271483 }
14281484
1485
+static int rk_tsadcv3_get_trim_code(const struct chip_tsadc_table *table,
1486
+ int code, int trim_base, int trim_base_frac)
1487
+{
1488
+ int temp = trim_base * 1000 + trim_base_frac * 100;
1489
+ u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
1490
+
1491
+ return (TSADCV3_Q_MAX_VAL - code) - base_code;
1492
+}
1493
+
14291494 static int rk_tsadcv1_set_clk_rate(struct platform_device *pdev)
14301495 {
14311496 struct clk *clk;
....@@ -1448,6 +1513,75 @@
14481513
14491514 return 0;
14501515 }
1516
+
1517
+static const struct rockchip_tsadc_chip px30_tsadc_data = {
1518
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1519
+ .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1520
+ .chn_num = 2, /* 2 channels for tsadc */
1521
+
1522
+ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1523
+ .tshut_temp = 95000,
1524
+
1525
+ .initialize = rk_tsadcv4_initialize,
1526
+ .irq_ack = rk_tsadcv3_irq_ack,
1527
+ .control = rk_tsadcv3_control,
1528
+ .get_temp = rk_tsadcv2_get_temp,
1529
+ .set_alarm_temp = rk_tsadcv2_alarm_temp,
1530
+ .set_tshut_temp = rk_tsadcv2_tshut_temp,
1531
+ .set_tshut_mode = rk_tsadcv2_tshut_mode,
1532
+
1533
+ .table = {
1534
+ .id = rk3328_code_table,
1535
+ .length = ARRAY_SIZE(rk3328_code_table),
1536
+ .data_mask = TSADCV2_DATA_MASK,
1537
+ .mode = ADC_INCREMENT,
1538
+ },
1539
+};
1540
+
1541
+static const struct rockchip_tsadc_chip px30s_tsadc_data = {
1542
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1543
+ .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1544
+ .chn_num = 2, /* 1 channels for tsadc */
1545
+ .conversion_time = 2100, /* us */
1546
+ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1547
+ .tshut_temp = 95000,
1548
+ .initialize = rk_tsadcv10_initialize,
1549
+ .irq_ack = rk_tsadcv3_irq_ack,
1550
+ .control = rk_tsadcv2_control,
1551
+ .get_temp = rk_tsadcv2_get_temp,
1552
+ .set_alarm_temp = rk_tsadcv2_alarm_temp,
1553
+ .set_tshut_temp = rk_tsadcv2_tshut_temp,
1554
+ .set_tshut_mode = rk_tsadcv2_tshut_mode,
1555
+ .set_clk_rate = rk_tsadcv1_set_clk_rate,
1556
+ .table = {
1557
+ .kNum = 2699,
1558
+ .bNum = 2796,
1559
+ .data_mask = TSADCV2_DATA_MASK,
1560
+ .mode = ADC_INCREMENT,
1561
+ },
1562
+};
1563
+
1564
+static const struct rockchip_tsadc_chip rv1106_tsadc_data = {
1565
+ /* top, big_core0, big_core1, little_core, center, gpu, npu */
1566
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1567
+ .chn_num = 1, /* seven channels for tsadc */
1568
+ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1569
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1570
+ .tshut_temp = 95000,
1571
+ .initialize = rk_tsadcv9_initialize,
1572
+ .irq_ack = rk_tsadcv4_irq_ack,
1573
+ .control = rk_tsadcv4_control,
1574
+ .get_temp = rk_tsadcv4_get_temp,
1575
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
1576
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
1577
+ .set_tshut_mode = rk_tsadcv4_tshut_mode,
1578
+ .table = {
1579
+ .id = rv1106_code_table,
1580
+ .length = ARRAY_SIZE(rv1106_code_table),
1581
+ .data_mask = TSADCV2_DATA_MASK,
1582
+ .mode = ADC_INCREMENT,
1583
+ },
1584
+};
14511585
14521586 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
14531587 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
....@@ -1559,7 +1693,7 @@
15591693 .initialize = rk_tsadcv2_initialize,
15601694 .irq_ack = rk_tsadcv2_irq_ack,
15611695 .control = rk_tsadcv2_control,
1562
- .get_temp = rk_tsadcv3_get_temp,
1696
+ .get_temp = rk_tsadcv2_get_temp,
15631697 .set_alarm_temp = rk_tsadcv2_alarm_temp,
15641698 .set_tshut_temp = rk_tsadcv2_tshut_temp,
15651699 .set_tshut_mode = rk_tsadcv2_tshut_mode,
....@@ -1580,7 +1714,7 @@
15801714 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
15811715 .tshut_temp = 95000,
15821716
1583
- .initialize = rk_tsadcv4_initialize,
1717
+ .initialize = rk_tsadcv2_initialize,
15841718 .irq_ack = rk_tsadcv3_irq_ack,
15851719 .control = rk_tsadcv3_control,
15861720 .get_temp = rk_tsadcv2_get_temp,
....@@ -1596,38 +1730,16 @@
15961730 },
15971731 };
15981732
1599
-static const struct rockchip_tsadc_chip px30_tsadc_data = {
1733
+static const struct rockchip_tsadc_chip rk3308bs_tsadc_data = {
16001734 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1601
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1602
- .chn_num = 2, /* 2 channels for tsadc */
1735
+ .chn_num = 1, /* 1 channels for tsadc */
16031736
1604
- .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1605
- .tshut_temp = 95000,
1606
-
1607
- .initialize = rk_tsadcv4_initialize,
1608
- .irq_ack = rk_tsadcv3_irq_ack,
1609
- .control = rk_tsadcv3_control,
1610
- .get_temp = rk_tsadcv2_get_temp,
1611
- .set_alarm_temp = rk_tsadcv2_alarm_temp,
1612
- .set_tshut_temp = rk_tsadcv2_tshut_temp,
1613
- .set_tshut_mode = rk_tsadcv2_tshut_mode,
1614
-
1615
- .table = {
1616
- .id = rk3328_code_table,
1617
- .length = ARRAY_SIZE(rk3328_code_table),
1618
- .data_mask = TSADCV2_DATA_MASK,
1619
- .mode = ADC_INCREMENT,
1620
- },
1621
-};
1622
-
1623
-static const struct rockchip_tsadc_chip px30s_tsadc_data = {
1624
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1625
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1626
- .chn_num = 2, /* 1 channels for tsadc */
16271737 .conversion_time = 2100, /* us */
1738
+
16281739 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
16291740 .tshut_temp = 95000,
1630
- .initialize = rk_tsadcv9_initialize,
1741
+
1742
+ .initialize = rk_tsadcv2_initialize,
16311743 .irq_ack = rk_tsadcv3_irq_ack,
16321744 .control = rk_tsadcv2_control,
16331745 .get_temp = rk_tsadcv2_get_temp,
....@@ -1635,6 +1747,7 @@
16351747 .set_tshut_temp = rk_tsadcv2_tshut_temp,
16361748 .set_tshut_mode = rk_tsadcv2_tshut_mode,
16371749 .set_clk_rate = rk_tsadcv1_set_clk_rate,
1750
+
16381751 .table = {
16391752 .kNum = 2699,
16401753 .bNum = 2796,
....@@ -1756,10 +1869,38 @@
17561869 .set_alarm_temp = rk_tsadcv3_alarm_temp,
17571870 .set_tshut_temp = rk_tsadcv3_tshut_temp,
17581871 .set_tshut_mode = rk_tsadcv4_tshut_mode,
1872
+ .get_trim_code = rk_tsadcv3_get_trim_code,
1873
+ .trim_slope = 574,
17591874
17601875 .table = {
17611876 .id = rk3528_code_table,
17621877 .length = ARRAY_SIZE(rk3528_code_table),
1878
+ .data_mask = TSADCV2_DATA_MASK,
1879
+ .mode = ADC_INCREMENT,
1880
+ },
1881
+};
1882
+
1883
+static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
1884
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1885
+ .chn_num = 1, /* one channels for tsadc */
1886
+
1887
+ .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
1888
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1889
+ .tshut_temp = 95000,
1890
+
1891
+ .initialize = rk_tsadcv12_initialize,
1892
+ .irq_ack = rk_tsadcv4_irq_ack,
1893
+ .control = rk_tsadcv4_control,
1894
+ .get_temp = rk_tsadcv4_get_temp,
1895
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
1896
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
1897
+ .set_tshut_mode = rk_tsadcv4_tshut_mode,
1898
+ .get_trim_code = rk_tsadcv3_get_trim_code,
1899
+ .trim_slope = 588,
1900
+
1901
+ .table = {
1902
+ .id = rk3562_code_table,
1903
+ .length = ARRAY_SIZE(rk3562_code_table),
17631904 .data_mask = TSADCV2_DATA_MASK,
17641905 .mode = ADC_INCREMENT,
17651906 },
....@@ -1815,7 +1956,21 @@
18151956 };
18161957
18171958 static const struct of_device_id of_rockchip_thermal_match[] = {
1818
-#ifdef CONFIG_CPU_RV110X
1959
+#ifdef CONFIG_CPU_PX30
1960
+ { .compatible = "rockchip,px30-tsadc",
1961
+ .data = (void *)&px30_tsadc_data,
1962
+ },
1963
+ { .compatible = "rockchip,px30s-tsadc",
1964
+ .data = (void *)&px30s_tsadc_data,
1965
+ },
1966
+#endif
1967
+#ifdef CONFIG_CPU_RV1106
1968
+ {
1969
+ .compatible = "rockchip,rv1106-tsadc",
1970
+ .data = (void *)&rv1106_tsadc_data,
1971
+ },
1972
+#endif
1973
+#ifdef CONFIG_CPU_RV1108
18191974 {
18201975 .compatible = "rockchip,rv1108-tsadc",
18211976 .data = (void *)&rv1108_tsadc_data,
....@@ -1825,14 +1980,6 @@
18251980 {
18261981 .compatible = "rockchip,rv1126-tsadc",
18271982 .data = (void *)&rv1126_tsadc_data,
1828
- },
1829
-#endif
1830
-#ifdef CONFIG_CPU_PX30
1831
- { .compatible = "rockchip,px30-tsadc",
1832
- .data = (void *)&px30_tsadc_data,
1833
- },
1834
- { .compatible = "rockchip,px30s-tsadc",
1835
- .data = (void *)&px30s_tsadc_data,
18361983 },
18371984 #endif
18381985 #ifdef CONFIG_CPU_RK1808
....@@ -1857,6 +2004,10 @@
18572004 {
18582005 .compatible = "rockchip,rk3308-tsadc",
18592006 .data = (void *)&rk3308_tsadc_data,
2007
+ },
2008
+ {
2009
+ .compatible = "rockchip,rk3308bs-tsadc",
2010
+ .data = (void *)&rk3308bs_tsadc_data,
18602011 },
18612012 #endif
18622013 #ifdef CONFIG_CPU_RK3328
....@@ -1889,6 +2040,12 @@
18892040 .data = (void *)&rk3528_tsadc_data,
18902041 },
18912042 #endif
2043
+#ifdef CONFIG_CPU_RK3562
2044
+ {
2045
+ .compatible = "rockchip,rk3562-tsadc",
2046
+ .data = (void *)&rk3562_tsadc_data,
2047
+ },
2048
+#endif
18922049 #ifdef CONFIG_CPU_RK3568
18932050 {
18942051 .compatible = "rockchip,rk3568-tsadc",
....@@ -1910,8 +2067,10 @@
19102067 {
19112068 struct thermal_zone_device *tzd = sensor->tzd;
19122069
1913
- tzd->ops->set_mode(tzd,
1914
- on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
2070
+ if (on)
2071
+ thermal_zone_device_enable(tzd);
2072
+ else
2073
+ thermal_zone_device_disable(tzd);
19152074 }
19162075
19172076 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
....@@ -2021,12 +2180,9 @@
20212180 * The tsadc won't to handle the error in here
20222181 * since some SoCs didn't need this property.
20232182 */
2024
- if (rockchip_get_efuse_value(np, "trim_base", &trim_base)) {
2025
- dev_info(dev, "Missing trim_base property\n");
2026
- return 0;
2027
- }
2183
+ rockchip_get_efuse_value(np, "trim_base", &trim_base);
20282184 if (!trim_base)
2029
- return 0;
2185
+ trim_base = 30;
20302186 rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac);
20312187 /*
20322188 * If the tsadc node contains trim_h and trim_l property,
....@@ -2182,6 +2338,7 @@
21822338
21832339 /**
21842340 * Reset TSADC Controller, reset all tsadc registers.
2341
+ * @reset: the reset controller of tsadc
21852342 */
21862343 static void rockchip_thermal_reset_controller(struct reset_control *reset)
21872344 {
....@@ -2242,10 +2399,8 @@
22422399 return -ENXIO;
22432400
22442401 irq = platform_get_irq(pdev, 0);
2245
- if (irq < 0) {
2246
- dev_err(&pdev->dev, "no irq resource?\n");
2402
+ if (irq < 0)
22472403 return -EINVAL;
2248
- }
22492404
22502405 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
22512406 GFP_KERNEL);
....@@ -2259,6 +2414,8 @@
22592414 return -EINVAL;
22602415 if (soc_is_px30s())
22612416 thermal->chip = &px30s_tsadc_data;
2417
+ if (soc_is_rk3308bs())
2418
+ thermal->chip = &rk3308bs_tsadc_data;
22622419
22632420 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
22642421 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
....@@ -2346,8 +2503,15 @@
23462503 usleep_range(thermal->chip->conversion_time,
23472504 thermal->chip->conversion_time + 50);
23482505
2349
- for (i = 0; i < thermal->chip->chn_num; i++)
2506
+ for (i = 0; i < thermal->chip->chn_num; i++) {
23502507 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
2508
+ thermal->sensors[i].tzd->tzp->no_hwmon = false;
2509
+ error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
2510
+ if (error)
2511
+ dev_warn(&pdev->dev,
2512
+ "failed to register sensor %d with hwmon: %d\n",
2513
+ i, error);
2514
+ }
23512515
23522516 thermal->panic_nb.notifier_call = rockchip_thermal_panic;
23532517 atomic_notifier_chain_register(&panic_notifier_list,
....@@ -2371,6 +2535,7 @@
23712535 for (i = 0; i < thermal->chip->chn_num; i++) {
23722536 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
23732537
2538
+ thermal_remove_hwmon_sysfs(sensor->tzd);
23742539 rockchip_thermal_toggle_sensor(sensor, false);
23752540 }
23762541
....@@ -2400,8 +2565,7 @@
24002565
24012566 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
24022567 {
2403
- struct platform_device *pdev = to_platform_device(dev);
2404
- struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
2568
+ struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
24052569 int i;
24062570
24072571 for (i = 0; i < thermal->chip->chn_num; i++)
....@@ -2419,14 +2583,13 @@
24192583
24202584 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
24212585 {
2422
- struct platform_device *pdev = to_platform_device(dev);
2423
- struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
2586
+ struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
24242587 int i;
24252588 int error;
24262589
24272590 error = clk_bulk_enable(thermal->num_clks, thermal->clks);
24282591 if (error) {
2429
- dev_err(&pdev->dev, "failed to enable tsadc bulk clks: %d\n",
2592
+ dev_err(dev, "failed to enable tsadc bulk clks: %d\n",
24302593 error);
24312594 return error;
24322595 }
....@@ -2447,7 +2610,7 @@
24472610 id, thermal->regs,
24482611 tshut_temp);
24492612 if (error)
2450
- dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
2613
+ dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
24512614 __func__, tshut_temp, error);
24522615 }
24532616
....@@ -2479,7 +2642,17 @@
24792642 .shutdown = rockchip_thermal_shutdown,
24802643 };
24812644
2482
-module_platform_driver(rockchip_thermal_driver);
2645
+static int __init rockchip_thermal_driver_init(void)
2646
+{
2647
+ return platform_driver_register(&rockchip_thermal_driver);
2648
+}
2649
+rootfs_initcall(rockchip_thermal_driver_init);
2650
+
2651
+static void __exit rockchip_thermal_driver_exit(void)
2652
+{
2653
+ platform_driver_unregister(&rockchip_thermal_driver);
2654
+}
2655
+module_exit(rockchip_thermal_driver_exit);
24832656
24842657 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
24852658 MODULE_AUTHOR("Rockchip, Inc.");