modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/staging/mt7621-dts/mt7621.dtsi
..
..
@@ -1,4 +1,5 @@
1
1
 #include <dt-bindings/interrupt-controller/mips-gic.h>
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+#include <dt-bindings/gpio/gpio.h>
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3
 
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 / {
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 	#address-cells = <1>;
..
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@@ -40,6 +41,30 @@
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41
 
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 		/* This is normally 1/4 of cpuclock */
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 		clock-frequency = <220000000>;
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+	};
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+
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+	mmc_clock: mmc_clock@0 {
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+		#clock-cells = <0>;
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+		compatible = "fixed-clock";
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+		clock-frequency = <48000000>;
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+	};
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+
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+	mmc_fixed_3v3: fixedregulator@0 {
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+		compatible = "regulator-fixed";
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+		regulator-name = "mmc_power";
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+		regulator-min-microvolt = <3300000>;
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+		regulator-max-microvolt = <3300000>;
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+		enable-active-high;
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+		regulator-always-on;
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+	};
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+
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+	mmc_fixed_1v8_io: fixedregulator@1 {
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+		compatible = "regulator-fixed";
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+		regulator-name = "mmc_io";
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+		regulator-min-microvolt = <1800000>;
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+		regulator-max-microvolt = <1800000>;
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+		enable-active-high;
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+		regulator-always-on;
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 	};
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 	palmbus: palmbus@1E000000 {
..
..
@@ -113,7 +138,7 @@
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138
 
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 		memc: memc@5000 {
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 			compatible = "mtk,mt7621-memc";
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-			reg = <0x300 0x100>;
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+			reg = <0x5000 0x1000>;
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 		};
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143
 
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 		cpc: cpc@1fbf0000 {
..
..
@@ -202,84 +227,84 @@
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 		state_default: pinctrl0 {
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 		};
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229
 
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-		i2c_pins: i2c {
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-			i2c {
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-				group = "i2c";
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+		i2c_pins: i2c0 {
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+			i2c0 {
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+				groups = "i2c";
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 				function = "i2c";
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 			};
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 		};
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-		spi_pins: spi {
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-			spi {
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-				group = "spi";
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+		spi_pins: spi0 {
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+			spi0 {
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+				groups = "spi";
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 				function = "spi";
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 			};
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 		};
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 		uart1_pins: uart1 {
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 			uart1 {
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-				group = "uart1";
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+				groups = "uart1";
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 				function = "uart1";
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 			};
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 		};
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 		uart2_pins: uart2 {
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 			uart2 {
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-				group = "uart2";
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+				groups = "uart2";
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 				function = "uart2";
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 			};
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 		};
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 		uart3_pins: uart3 {
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 			uart3 {
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-				group = "uart3";
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+				groups = "uart3";
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 				function = "uart3";
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 			};
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 		};
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 		rgmii1_pins: rgmii1 {
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 			rgmii1 {
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-				group = "rgmii1";
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+				groups = "rgmii1";
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 				function = "rgmii1";
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 			};
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 		};
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 		rgmii2_pins: rgmii2 {
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 			rgmii2 {
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-				group = "rgmii2";
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+				groups = "rgmii2";
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 				function = "rgmii2";
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 			};
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 		};
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-		mdio_pins: mdio {
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-			mdio {
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-				group = "mdio";
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+		mdio_pins: mdio0 {
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+			mdio0 {
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+				groups = "mdio";
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 				function = "mdio";
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 			};
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 		};
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285
 
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-		pcie_pins: pcie {
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-			pcie {
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-				group = "pcie";
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-				function = "pcie rst";
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+		pcie_pins: pcie0 {
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+			pcie0 {
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+				groups = "pcie";
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+				function = "gpio";
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 			};
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 		};
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292
 
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-		nand_pins: nand {
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+		nand_pins: nand0 {
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 			spi-nand {
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-				group = "spi";
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+				groups = "spi";
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 				function = "nand1";
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 			};
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 			sdhci-nand {
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-				group = "sdhci";
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+				groups = "sdhci";
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 				function = "nand2";
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 			};
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 		};
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-		sdhci_pins: sdhci {
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-			sdhci {
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-				group = "sdhci";
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+		sdhci_pins: sdhci0 {
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+			sdhci0 {
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+				groups = "sdhci";
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 				function = "sdhci";
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 			};
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 		};
..
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@@ -298,8 +323,23 @@
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 	sdhci: sdhci@1E130000 {
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 		status = "disabled";
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-		compatible = "ralink,mt7620-sdhci";
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+		compatible = "mediatek,mt7620-mmc";
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 		reg = <0x1E130000 0x4000>;
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+
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+		bus-width = <4>;
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+		max-frequency = <48000000>;
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+		cap-sd-highspeed;
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+		cap-mmc-highspeed;
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+		vmmc-supply = <&mmc_fixed_3v3>;
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+		vqmmc-supply = <&mmc_fixed_1v8_io>;
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+		disable-wp;
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+
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+		pinctrl-names = "default", "state_uhs";
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+		pinctrl-0 = <&sdhci_pins>;
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+		pinctrl-1 = <&sdhci_pins>;
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+
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+		clocks = <&mmc_clock &mmc_clock>;
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+		clock-names = "source", "hclk";
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343
 
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 		interrupt-parent = <&gic>;
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 		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -372,15 +412,88 @@
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412
 
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 		mediatek,ethsys = <&ethsys>;
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414
 
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-		mediatek,switch = <&gsw>;
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+		pinctrl-names = "default";
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+		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
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+
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+		gmac0: mac@0 {
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+			compatible = "mediatek,eth-mac";
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+			reg = <0>;
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+			phy-mode = "rgmii";
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+
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+			fixed-link {
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+				speed = <1000>;
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+				full-duplex;
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+				pause;
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+			};
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+		};
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+
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+		gmac1: mac@1 {
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+			compatible = "mediatek,eth-mac";
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+			reg = <1>;
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+			status = "off";
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+			phy-mode = "rgmii-rxid";
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+		};
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436
 
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 		mdio-bus {
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 			#address-cells = <1>;
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 			#size-cells = <0>;
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440
 
381
-			phy1f: ethernet-phy@1f {
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-				reg = <0x1f>;
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-				phy-mode = "rgmii";
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+			switch0: switch0@0 {
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+				compatible = "mediatek,mt7621";
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+				reg = <0>;
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+				mediatek,mcm;
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+				resets = <&rstctrl 2>;
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+				reset-names = "mcm";
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+
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+				ports {
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+					#address-cells = <1>;
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+					#size-cells = <0>;
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+					reg = <0>;
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+
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+					port@0 {
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+						status = "off";
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+						reg = <0>;
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+						label = "lan0";
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+					};
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+
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+					port@1 {
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+						status = "off";
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+						reg = <1>;
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+						label = "lan1";
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+					};
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+
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+					port@2 {
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+						status = "off";
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+						reg = <2>;
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+						label = "lan2";
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+					};
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+
473
+					port@3 {
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+						status = "off";
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+						reg = <3>;
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+						label = "lan3";
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+					};
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+
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+					port@4 {
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+						status = "off";
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+						reg = <4>;
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+						label = "lan4";
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+					};
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+
485
+					port@6 {
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+						reg = <6>;
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+						label = "cpu";
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+						ethernet = <&gmac0>;
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+						phy-mode = "trgmii";
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+
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+						fixed-link {
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+							speed = <1000>;
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+							full-duplex;
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+						};
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+					};
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+				};
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 			};
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 		};
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 	};
..
..
@@ -398,7 +511,6 @@
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 			0x1e142000 0x100    /* pcie port 0 RC control registers */
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 			0x1e143000 0x100    /* pcie port 1 RC control registers */
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 			0x1e144000 0x100>;  /* pcie port 2 RC control registers */
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-
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 		#address-cells = <3>;
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 		#size-cells = <2>;
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..
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@@ -413,11 +525,10 @@
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 			0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
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526
 		>;
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527
 
416
-		#interrupt-cells = <1>;
417
-		interrupt-map-mask = <0xF0000 0 0 1>;
418
-		interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
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-				<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
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-				<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
528
+		interrupt-parent = <&gic>;
529
+		interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
530
+				GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
531
+				GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
421
532
 
422
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 		status = "disabled";
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534
 
..
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@@ -425,6 +536,10 @@
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 		reset-names = "pcie0", "pcie1", "pcie2";
426
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 		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
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 		clock-names = "pcie0", "pcie1", "pcie2";
539
+		phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
540
+		phy-names = "pcie-phy0", "pcie-phy2";
541
+
542
+		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
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543
 
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 		pcie@0,0 {
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 			reg = <0x0000 0 0 0 0>;
..
..
@@ -450,4 +565,16 @@
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 			bus-range = <0x00 0xff>;
451
566
 		};
452
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 	};
568
+
569
+	pcie0_phy: pcie-phy@1e149000 {
570
+		compatible = "mediatek,mt7621-pci-phy";
571
+		reg = <0x1e149000 0x0700>;
572
+		#phy-cells = <1>;
573
+	};
574
+
575
+	pcie2_phy: pcie-phy@1e14a000 {
576
+		compatible = "mediatek,mt7621-pci-phy";
577
+		reg = <0x1e14a000 0x0700>;
578
+		#phy-cells = <1>;
579
+	};
453
580
 };