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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/spi/spi-sun6i.c
....@@ -1,16 +1,13 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (C) 2012 - 2014 Allwinner Tech
34  * Pan Nan <pannan@allwinnertech.com>
45  *
56  * Copyright (C) 2014 Maxime Ripard
67  * Maxime Ripard <maxime.ripard@free-electrons.com>
7
- *
8
- * This program is free software; you can redistribute it and/or
9
- * modify it under the terms of the GNU General Public License as
10
- * published by the Free Software Foundation; either version 2 of
11
- * the License, or (at your option) any later version.
128  */
139 
10
+#include <linux/bitfield.h>
1411 #include <linux/clk.h>
1512 #include <linux/delay.h>
1613 #include <linux/device.h>
....@@ -62,10 +59,8 @@
6259 #define SUN6I_FIFO_CTL_TF_RST			BIT(31)
6360 
6461 #define SUN6I_FIFO_STA_REG		0x1c
65
-#define SUN6I_FIFO_STA_RF_CNT_MASK		0x7f
66
-#define SUN6I_FIFO_STA_RF_CNT_BITS		0
67
-#define SUN6I_FIFO_STA_TF_CNT_MASK		0x7f
68
-#define SUN6I_FIFO_STA_TF_CNT_BITS		16
62
+#define SUN6I_FIFO_STA_RF_CNT_MASK		GENMASK(7, 0)
63
+#define SUN6I_FIFO_STA_TF_CNT_MASK		GENMASK(23, 16)
6964 
7065 #define SUN6I_CLK_CTL_REG		0x24
7166 #define SUN6I_CLK_CTL_CDR2_MASK			0xff
....@@ -77,13 +72,10 @@
7772 #define SUN6I_MAX_XFER_SIZE		0xffffff
7873 
7974 #define SUN6I_BURST_CNT_REG		0x30
80
-#define SUN6I_BURST_CNT(cnt)			((cnt) & SUN6I_MAX_XFER_SIZE)
8175 
8276 #define SUN6I_XMIT_CNT_REG		0x34
83
-#define SUN6I_XMIT_CNT(cnt)			((cnt) & SUN6I_MAX_XFER_SIZE)
8477 
8578 #define SUN6I_BURST_CTL_CNT_REG		0x38
86
-#define SUN6I_BURST_CTL_CNT_STC(cnt)		((cnt) & SUN6I_MAX_XFER_SIZE)
8779 
8880 #define SUN6I_TXDATA_REG		0x200
8981 #define SUN6I_RXDATA_REG		0x300
....@@ -113,21 +105,18 @@
113105 	writel(value, sspi->base_addr + reg);
114106 }
115107 
108
+static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
109
+{
110
+	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
111
+
112
+	return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
113
+}
114
+
116115 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
117116 {
118117 	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
119118 
120
-	reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
121
-
122
-	return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
123
-}
124
-
125
-static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
126
-{
127
-	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
128
-
129
-	reg |= mask;
130
-	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
119
+	return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
131120 }
132121 
133122 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
....@@ -138,18 +127,13 @@
138127 	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
139128 }
140129 
141
-static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
130
+static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
142131 {
143
-	u32 reg, cnt;
132
+	u32 len;
144133 	u8 byte;
145134 
146135 	/* See how much data is available */
147
-	reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
148
-	reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
149
-	cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
150
-
151
-	if (len > cnt)
152
-		len = cnt;
136
+	len = sun6i_spi_get_rx_fifo_count(sspi);
153137 
154138 	while (len--) {
155139 		byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
....@@ -158,15 +142,16 @@
158142 	}
159143 }
160144 
161
-static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
145
+static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
162146 {
163147 	u32 cnt;
148
+	int len;
164149 	u8 byte;
165150 
166151 	/* See how much data we can fit */
167152 	cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
168153 
169
-	len = min3(len, (int)cnt, sspi->len);
154
+	len = min((int)cnt, sspi->len);
170155 
171156 	while (len--) {
172157 		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
....@@ -205,7 +190,7 @@
205190 	unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
206191 	unsigned int start, end, tx_time;
207192 	unsigned int trig_level;
208
-	unsigned int tx_len = 0;
193
+	unsigned int tx_len = 0, rx_len = 0;
209194 	int ret = 0;
210195 	u32 reg;
211196 
....@@ -260,10 +245,12 @@
260245 	 * If it's a TX only transfer, we don't want to fill the RX
261246 	 * FIFO with bogus data
262247 	 */
263
-	if (sspi->rx_buf)
248
+	if (sspi->rx_buf) {
264249 		reg &= ~SUN6I_TFR_CTL_DHB;
265
-	else
250
+		rx_len = tfr->len;
251
+	} else {
266252 		reg |= SUN6I_TFR_CTL_DHB;
253
+	}
267254 
268255 	/* We want to control the chip select manually */
269256 	reg |= SUN6I_TFR_CTL_CS_MANUAL;
....@@ -295,9 +282,11 @@
295282 	div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
296283 	if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
297284 		reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
285
+		tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
298286 	} else {
299287 		div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
300288 		reg = SUN6I_CLK_CTL_CDR1(div);
289
+		tfr->effective_speed_hz = mclk_rate / (1 << div);
301290 	}
302291 
303292 	sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
....@@ -311,20 +300,22 @@
311300 		tx_len = tfr->len;
312301 
313302 	/* Setup the counters */
314
-	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
315
-	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
316
-	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
317
-			SUN6I_BURST_CTL_CNT_STC(tx_len));
303
+	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
304
+	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
305
+	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
318306 
319307 	/* Fill the TX FIFO */
320
-	sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
308
+	sun6i_spi_fill_fifo(sspi);
321309 
322310 	/* Enable the interrupts */
323
-	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
324
-	sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
325
-					 SUN6I_INT_CTL_RF_RDY);
311
+	reg = SUN6I_INT_CTL_TC;
312
+
313
+	if (rx_len > sspi->fifo_depth)
314
+		reg |= SUN6I_INT_CTL_RF_RDY;
326315 	if (tx_len > sspi->fifo_depth)
327
-		sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
316
+		reg |= SUN6I_INT_CTL_TF_ERQ;
317
+
318
+	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
328319 
329320 	/* Start the transfer */
330321 	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
....@@ -341,10 +332,8 @@
341332 			 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
342333 			 jiffies_to_msecs(end - start), tx_time);
343334 		ret = -ETIMEDOUT;
344
-		goto out;
345335 	}
346336 
347
-out:
348337 	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
349338 
350339 	return ret;
....@@ -358,14 +347,14 @@
358347 	/* Transfer complete */
359348 	if (status & SUN6I_INT_CTL_TC) {
360349 		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
361
-		sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
350
+		sun6i_spi_drain_fifo(sspi);
362351 		complete(&sspi->done);
363352 		return IRQ_HANDLED;
364353 	}
365354 
366355 	/* Receive FIFO 3/4 full */
367356 	if (status & SUN6I_INT_CTL_RF_RDY) {
368
-		sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
357
+		sun6i_spi_drain_fifo(sspi);
369358 		/* Only clear the interrupt _after_ draining the FIFO */
370359 		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
371360 		return IRQ_HANDLED;
....@@ -373,7 +362,7 @@
373362 
374363 	/* Transmit FIFO 3/4 empty */
375364 	if (status & SUN6I_INT_CTL_TF_ERQ) {
376
-		sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
365
+		sun6i_spi_fill_fifo(sspi);
377366 
378367 		if (!sspi->len)
379368 			/* nothing left to transmit */
....@@ -441,7 +430,6 @@
441430 {
442431 	struct spi_master *master;
443432 	struct sun6i_spi *sspi;
444
-	struct resource	*res;
445433 	int ret = 0, irq;
446434 
447435 	master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
....@@ -453,8 +441,7 @@
453441 	platform_set_drvdata(pdev, master);
454442 	sspi = spi_master_get_devdata(master);
455443 
456
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457
-	sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
444
+	sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
458445 	if (IS_ERR(sspi->base_addr)) {
459446 		ret = PTR_ERR(sspi->base_addr);
460447 		goto err_free_master;
....@@ -462,7 +449,6 @@
462449 
463450 	irq = platform_get_irq(pdev, 0);
464451 	if (irq < 0) {
465
-		dev_err(&pdev->dev, "No spi IRQ specified\n");
466452 		ret = -ENXIO;
467453 		goto err_free_master;
468454 	}
....@@ -479,6 +465,7 @@
479465 
480466 	master->max_speed_hz = 100 * 1000 * 1000;
481467 	master->min_speed_hz = 3 * 1000;
468
+	master->use_gpio_descriptors = true;
482469 	master->set_cs = sun6i_spi_set_cs;
483470 	master->transfer_one = sun6i_spi_transfer_one;
484471 	master->num_chipselect = 4;