modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/spi/spi-mt65xx.c
..
..
@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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2
 /*
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  * Copyright (c) 2015 MediaTek Inc.
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  * Author: Leilk Liu <leilk.liu@mediatek.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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5
  */
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6
 
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 #include <linux/clk.h>
..
..
@@ -25,6 +17,7 @@
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 #include <linux/platform_data/spi-mt65xx.h>
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 #include <linux/pm_runtime.h>
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19
 #include <linux/spi/spi.h>
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+#include <linux/dma-mapping.h>
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21
 
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 #define SPI_CFG0_REG                      0x0000
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 #define SPI_CFG1_REG                      0x0004
..
..
@@ -36,6 +29,8 @@
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 #define SPI_STATUS0_REG                   0x001c
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 #define SPI_PAD_SEL_REG                   0x0024
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 #define SPI_CFG2_REG                      0x0028
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+#define SPI_TX_SRC_REG_64                 0x002c
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+#define SPI_RX_DST_REG_64                 0x0030
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34
 
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 #define SPI_CFG0_SCK_HIGH_OFFSET          0
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 #define SPI_CFG0_SCK_LOW_OFFSET           8
..
..
@@ -82,6 +77,10 @@
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77
 
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 #define MTK_SPI_MAX_FIFO_SIZE 32U
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 #define MTK_SPI_PACKET_SIZE 1024
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+#define MTK_SPI_32BITS_MASK  (0xffffffff)
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+
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+#define DMA_ADDR_EXT_BITS (36)
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+#define DMA_ADDR_DEF_BITS (32)
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84
 
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 struct mtk_spi_compatible {
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 	bool need_pad_sel;
..
..
@@ -89,6 +88,8 @@
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 	bool must_tx;
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 	/* some IC design adjust cfg register to enhance time accuracy */
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 	bool enhance_timing;
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+	/* some IC support DMA addr extension */
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+	bool dma_ext;
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 };
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94
 
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 struct mtk_spi {
..
..
@@ -111,6 +112,13 @@
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 	.must_tx = true,
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 };
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114
 
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+static const struct mtk_spi_compatible mt6765_compat = {
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+	.need_pad_sel = true,
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+	.must_tx = true,
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+	.enhance_timing = true,
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+	.dma_ext = true,
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+};
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+
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 static const struct mtk_spi_compatible mt7622_compat = {
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 	.must_tx = true,
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 	.enhance_timing = true,
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..
@@ -121,14 +129,17 @@
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 	.must_tx = true,
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 };
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131
 
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+static const struct mtk_spi_compatible mt8183_compat = {
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+	.need_pad_sel = true,
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+	.must_tx = true,
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+	.enhance_timing = true,
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+};
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+
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 /*
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  * A piece of default chip info unless the platform
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  * supplies it.
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  */
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 static const struct mtk_chip_config mtk_default_chip_info = {
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-	.rx_mlsb = 1,
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-	.tx_mlsb = 1,
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-	.cs_pol = 0,
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143
 	.sample_sel = 0,
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 };
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145
 
..
..
@@ -142,7 +153,13 @@
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 	{ .compatible = "mediatek,mt6589-spi",
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 		.data = (void *)&mtk_common_compat,
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 	},
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+	{ .compatible = "mediatek,mt6765-spi",
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+		.data = (void *)&mt6765_compat,
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+	},
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 	{ .compatible = "mediatek,mt7622-spi",
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+		.data = (void *)&mt7622_compat,
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+	},
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+	{ .compatible = "mediatek,mt7629-spi",
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 		.data = (void *)&mt7622_compat,
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 	},
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 	{ .compatible = "mediatek,mt8135-spi",
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..
@@ -150,6 +167,12 @@
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 	},
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 	{ .compatible = "mediatek,mt8173-spi",
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 		.data = (void *)&mt8173_compat,
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+	},
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+	{ .compatible = "mediatek,mt8183-spi",
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+		.data = (void *)&mt8183_compat,
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+	},
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+	{ .compatible = "mediatek,mt8192-spi",
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+		.data = (void *)&mt6765_compat,
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 	},
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 	{}
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178
 };
..
..
@@ -192,14 +215,13 @@
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 		reg_val &= ~SPI_CMD_CPOL;
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216
 
194
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 	/* set the mlsbx and mlsbtx */
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-	if (chip_config->tx_mlsb)
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-		reg_val |= SPI_CMD_TXMSBF;
197
-	else
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+	if (spi->mode & SPI_LSB_FIRST) {
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219
 		reg_val &= ~SPI_CMD_TXMSBF;
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-	if (chip_config->rx_mlsb)
200
-		reg_val |= SPI_CMD_RXMSBF;
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-	else
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220
 		reg_val &= ~SPI_CMD_RXMSBF;
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+	} else {
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+		reg_val |= SPI_CMD_TXMSBF;
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+		reg_val |= SPI_CMD_RXMSBF;
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+	}
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225
 
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 	/* set the tx/rx endian */
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 #ifdef __LITTLE_ENDIAN
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..
@@ -211,10 +233,12 @@
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 #endif
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234
 
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 	if (mdata->dev_comp->enhance_timing) {
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-		if (chip_config->cs_pol)
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+		/* set CS polarity */
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+		if (spi->mode & SPI_CS_HIGH)
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 			reg_val |= SPI_CMD_CS_POL;
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 		else
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 			reg_val &= ~SPI_CMD_CS_POL;
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+
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 		if (chip_config->sample_sel)
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 			reg_val |= SPI_CMD_SAMPLE_SEL;
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 		else
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..
@@ -244,6 +268,9 @@
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 {
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 	u32 reg_val;
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270
 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
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+
272
+	if (spi->mode & SPI_CS_HIGH)
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+		enable = !enable;
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274
 
248
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 	reg_val = readl(mdata->base + SPI_CMD_REG);
249
276
 	if (!enable) {
..
..
@@ -371,10 +398,25 @@
371
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 {
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 	struct mtk_spi *mdata = spi_master_get_devdata(master);
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400
 
374
-	if (mdata->tx_sgl)
375
-		writel(xfer->tx_dma, mdata->base + SPI_TX_SRC_REG);
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-	if (mdata->rx_sgl)
377
-		writel(xfer->rx_dma, mdata->base + SPI_RX_DST_REG);
401
+	if (mdata->tx_sgl) {
402
+		writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
403
+		       mdata->base + SPI_TX_SRC_REG);
404
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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+		if (mdata->dev_comp->dma_ext)
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+			writel((u32)(xfer->tx_dma >> 32),
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+			       mdata->base + SPI_TX_SRC_REG_64);
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+#endif
409
+	}
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+
411
+	if (mdata->rx_sgl) {
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+		writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
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+		       mdata->base + SPI_RX_DST_REG);
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+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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+		if (mdata->dev_comp->dma_ext)
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+			writel((u32)(xfer->rx_dma >> 32),
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+			       mdata->base + SPI_RX_DST_REG_64);
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+#endif
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+	}
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 }
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421
 
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 static int mtk_spi_fifo_transfer(struct spi_master *master,
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@@ -586,8 +628,7 @@
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 	struct spi_master *master;
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629
 	struct mtk_spi *mdata;
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630
 	const struct of_device_id *of_id;
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-	struct resource *res;
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-	int i, irq, ret;
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+	int i, irq, ret, addr_bits;
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632
 
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 	master = spi_alloc_master(&pdev->dev, sizeof(*mdata));
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 	if (!master) {
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@@ -597,7 +638,7 @@
597
638
 
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 	master->auto_runtime_pm = true;
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 	master->dev.of_node = pdev->dev.of_node;
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-	master->mode_bits = SPI_CPOL | SPI_CPHA;
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+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
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642
 
602
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 	master->set_cs = mtk_spi_set_cs;
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644
 	master->prepare_message = mtk_spi_prepare_message;
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@@ -614,6 +655,10 @@
614
655
 
615
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 	mdata = spi_master_get_devdata(master);
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 	mdata->dev_comp = of_id->data;
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+
659
+	if (mdata->dev_comp->enhance_timing)
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+		master->mode_bits |= SPI_CS_HIGH;
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+
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 	if (mdata->dev_comp->must_tx)
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 		master->flags = SPI_MASTER_MUST_TX;
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@@ -649,15 +694,7 @@
649
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 	}
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695
 
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 	platform_set_drvdata(pdev, master);
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-
653
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
654
-	if (!res) {
655
-		ret = -ENODEV;
656
-		dev_err(&pdev->dev, "failed to determine base address\n");
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-		goto err_put_master;
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-	}
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-
660
-	mdata->base = devm_ioremap_resource(&pdev->dev, res);
697
+	mdata->base = devm_platform_ioremap_resource(pdev, 0);
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698
 	if (IS_ERR(mdata->base)) {
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699
 		ret = PTR_ERR(mdata->base);
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 		goto err_put_master;
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@@ -665,7 +702,6 @@
665
702
 
666
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 	irq = platform_get_irq(pdev, 0);
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 	if (irq < 0) {
668
-		dev_err(&pdev->dev, "failed to get irq (%d)\n", irq);
669
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 		ret = irq;
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 		goto err_put_master;
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 	}
..
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@@ -754,6 +790,15 @@
754
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 		}
755
791
 	}
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792
 
793
+	if (mdata->dev_comp->dma_ext)
794
+		addr_bits = DMA_ADDR_EXT_BITS;
795
+	else
796
+		addr_bits = DMA_ADDR_DEF_BITS;
797
+	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits));
798
+	if (ret)
799
+		dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
800
+			   addr_bits, ret);
801
+
757
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 	return 0;
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803
 
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 err_disable_runtime_pm: