~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,14 +1,19 @@
	1	+// SPDX-License-Identifier: GPL-2.0-only
1	2	/*
2	3	* QLogic Fibre Channel HBA Driver
3	4	* Copyright (c) 2003-2014 QLogic Corporation
4		- *
5		- * See LICENSE.qla2xxx for copyright and licensing details.
6	5	*/
7	6	#include "qla_def.h"
8	7	#include "qla_target.h"
9	8
10	9	#include <linux/delay.h>
11	10	#include <linux/gfp.h>
	11	+
	12	+#ifdef CONFIG_PPC
	13	+#define IS_PPCARCH true
	14	+#else
	15	+#define IS_PPCARCH false
	16	+#endif
12	17
13	18	static struct mb_cmd_name {
14	19	uint16_t cmd;
..	..	@@ -59,7 +64,9 @@
59	64	{ MBC_IOCB_COMMAND_A64 },
60	65	{ MBC_GET_ADAPTER_LOOP_ID },
61	66	{ MBC_READ_SFP },
	67	+ { MBC_SET_RNID_PARAMS },
62	68	{ MBC_GET_RNID_PARAMS },
	69	+ { MBC_GET_SET_ZIO_THRESHOLD },
63	70	};
64	71
65	72	static int is_rom_cmd(uint16_t cmd)
..	..	@@ -105,7 +112,7 @@
105	112	uint8_t io_lock_on;
106	113	uint16_t command = 0;
107	114	uint16_t *iptr;
108		- uint16_t __iomem *optr;
	115	+ __le16 __iomem *optr;
109	116	uint32_t cnt;
110	117	uint32_t mboxes;
111	118	unsigned long wait_time;
..	..	@@ -116,10 +123,9 @@
116	123
117	124	ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
118	125
119		- if (ha->pdev->error_state > pci_channel_io_frozen) {
	126	+ if (ha->pdev->error_state == pci_channel_io_perm_failure) {
120	127	ql_log(ql_log_warn, vha, 0x1001,
121		- "error_state is greater than pci_channel_io_frozen, "
122		- "exiting.\n");
	128	+ "PCI channel failed permanently, exiting.\n");
123	129	return QLA_FUNCTION_TIMEOUT;
124	130	}
125	131
..	..	@@ -161,7 +167,8 @@
161	167	/* check if ISP abort is active and return cmd with timeout */
162	168	if ((test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) \|\|
163	169	test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) \|\|
164		- test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) &&
	170	+ test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) \|\|
	171	+ ha->flags.eeh_busy) &&
165	172	!is_rom_cmd(mcp->mb[0])) {
166	173	ql_log(ql_log_info, vha, 0x1005,
167	174	"Cmd 0x%x aborted with timeout since ISP Abort is pending\n",
..	..	@@ -189,7 +196,7 @@
189	196	goto premature_exit;
190	197	}
191	198
192		- ha->flags.mbox_busy = 1;
	199	+
193	200	/* Save mailbox command for debug */
194	201	ha->mcp = mcp;
195	202
..	..	@@ -198,20 +205,21 @@
198	205
199	206	spin_lock_irqsave(&ha->hardware_lock, flags);
200	207
201		- if (ha->flags.purge_mbox \|\| chip_reset != ha->chip_reset) {
	208	+ if (ha->flags.purge_mbox \|\| chip_reset != ha->chip_reset \|\|
	209	+ ha->flags.mbox_busy) {
202	210	rval = QLA_ABORTED;
203		- ha->flags.mbox_busy = 0;
204	211	spin_unlock_irqrestore(&ha->hardware_lock, flags);
205	212	goto premature_exit;
206	213	}
	214	+ ha->flags.mbox_busy = 1;
207	215
208	216	/* Load mailbox registers. */
209	217	if (IS_P3P_TYPE(ha))
210		- optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
	218	+ optr = &reg->isp82.mailbox_in[0];
211	219	else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
212		- optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
	220	+ optr = &reg->isp24.mailbox0;
213	221	else
214		- optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
	222	+ optr = MAILBOX_REG(ha, &reg->isp, 0);
215	223
216	224	iptr = mcp->mb;
217	225	command = mcp->mb[0];
..	..	@@ -221,12 +229,13 @@
221	229	"Mailbox registers (OUT):\n");
222	230	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
223	231	if (IS_QLA2200(ha) && cnt == 8)
224		- optr =
225		- (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
	232	+ optr = MAILBOX_REG(ha, &reg->isp, 8);
226	233	if (mboxes & BIT_0) {
227	234	ql_dbg(ql_dbg_mbx, vha, 0x1112,
228	235	"mbox[%d]<-0x%04x\n", cnt, *iptr);
229		- WRT_REG_WORD(optr, *iptr);
	236	+ wrt_reg_word(optr, *iptr);
	237	+ } else {
	238	+ wrt_reg_word(optr, 0);
230	239	}
231	240
232	241	mboxes >>= 1;
..	..	@@ -251,27 +260,15 @@
251	260	if ((!abort_active && io_lock_on) \|\| IS_NOPOLLING_TYPE(ha)) {
252	261	set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
253	262
254		- if (IS_P3P_TYPE(ha)) {
255		- if (RD_REG_DWORD(&reg->isp82.hint) &
256		- HINT_MBX_INT_PENDING) {
257		- spin_unlock_irqrestore(&ha->hardware_lock,
258		- flags);
259		- ha->flags.mbox_busy = 0;
260		- atomic_dec(&ha->num_pend_mbx_stage2);
261		- ql_dbg(ql_dbg_mbx, vha, 0x1010,
262		- "Pending mailbox timeout, exiting.\n");
263		- rval = QLA_FUNCTION_TIMEOUT;
264		- goto premature_exit;
265		- }
266		- WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
267		- } else if (IS_FWI2_CAPABLE(ha))
268		- WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
	263	+ if (IS_P3P_TYPE(ha))
	264	+ wrt_reg_dword(&reg->isp82.hint, HINT_MBX_INT_PENDING);
	265	+ else if (IS_FWI2_CAPABLE(ha))
	266	+ wrt_reg_dword(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
269	267	else
270		- WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
	268	+ wrt_reg_word(&reg->isp.hccr, HCCR_SET_HOST_INT);
271	269	spin_unlock_irqrestore(&ha->hardware_lock, flags);
272	270
273	271	wait_time = jiffies;
274		- atomic_inc(&ha->num_pend_mbx_stage3);
275	272	if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
276	273	mcp->tov * HZ)) {
277	274	ql_dbg(ql_dbg_mbx, vha, 0x117a,
..	..	@@ -280,15 +277,24 @@
280	277	clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
281	278	spin_unlock_irqrestore(&ha->hardware_lock, flags);
282	279
	280	+ if (chip_reset != ha->chip_reset) {
	281	+ spin_lock_irqsave(&ha->hardware_lock, flags);
	282	+ ha->flags.mbox_busy = 0;
	283	+ spin_unlock_irqrestore(&ha->hardware_lock,
	284	+ flags);
	285	+ atomic_dec(&ha->num_pend_mbx_stage2);
	286	+ rval = QLA_ABORTED;
	287	+ goto premature_exit;
	288	+ }
283	289	} else if (ha->flags.purge_mbox \|\|
284	290	chip_reset != ha->chip_reset) {
	291	+ spin_lock_irqsave(&ha->hardware_lock, flags);
285	292	ha->flags.mbox_busy = 0;
	293	+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
286	294	atomic_dec(&ha->num_pend_mbx_stage2);
287		- atomic_dec(&ha->num_pend_mbx_stage3);
288	295	rval = QLA_ABORTED;
289	296	goto premature_exit;
290	297	}
291		- atomic_dec(&ha->num_pend_mbx_stage3);
292	298
293	299	if (time_after(jiffies, wait_time + 5 * HZ))
294	300	ql_log(ql_log_warn, vha, 0x1015, "cmd=0x%x, waited %d msecs\n",
..	..	@@ -298,29 +304,32 @@
298	304	"Cmd=%x Polling Mode.\n", command);
299	305
300	306	if (IS_P3P_TYPE(ha)) {
301		- if (RD_REG_DWORD(&reg->isp82.hint) &
	307	+ if (rd_reg_dword(&reg->isp82.hint) &
302	308	HINT_MBX_INT_PENDING) {
	309	+ ha->flags.mbox_busy = 0;
303	310	spin_unlock_irqrestore(&ha->hardware_lock,
304	311	flags);
305		- ha->flags.mbox_busy = 0;
306	312	atomic_dec(&ha->num_pend_mbx_stage2);
307	313	ql_dbg(ql_dbg_mbx, vha, 0x1012,
308	314	"Pending mailbox timeout, exiting.\n");
309	315	rval = QLA_FUNCTION_TIMEOUT;
310	316	goto premature_exit;
311	317	}
312		- WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
	318	+ wrt_reg_dword(&reg->isp82.hint, HINT_MBX_INT_PENDING);
313	319	} else if (IS_FWI2_CAPABLE(ha))
314		- WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
	320	+ wrt_reg_dword(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
315	321	else
316		- WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
	322	+ wrt_reg_word(&reg->isp.hccr, HCCR_SET_HOST_INT);
317	323	spin_unlock_irqrestore(&ha->hardware_lock, flags);
318	324
319	325	wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
320	326	while (!ha->flags.mbox_int) {
321	327	if (ha->flags.purge_mbox \|\|
322	328	chip_reset != ha->chip_reset) {
	329	+ spin_lock_irqsave(&ha->hardware_lock, flags);
323	330	ha->flags.mbox_busy = 0;
	331	+ spin_unlock_irqrestore(&ha->hardware_lock,
	332	+ flags);
324	333	atomic_dec(&ha->num_pend_mbx_stage2);
325	334	rval = QLA_ABORTED;
326	335	goto premature_exit;
..	..	@@ -355,7 +364,10 @@
355	364	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
356	365
357	366	if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
	367	+ spin_lock_irqsave(&ha->hardware_lock, flags);
358	368	ha->flags.mbox_busy = 0;
	369	+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
	370	+
359	371	/* Setting Link-Down error */
360	372	mcp->mb[0] = MBS_LINK_DOWN_ERROR;
361	373	ha->mcp = NULL;
..	..	@@ -365,8 +377,12 @@
365	377	goto premature_exit;
366	378	}
367	379
368		- if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
	380	+ if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE) {
	381	+ ql_dbg(ql_dbg_mbx, vha, 0x11ff,
	382	+ "mb_out[0] = %#x <> %#x\n", ha->mailbox_out[0],
	383	+ MBS_COMMAND_COMPLETE);
369	384	rval = QLA_FUNCTION_FAILED;
	385	+ }
370	386
371	387	/* Load return mailbox registers. */
372	388	iptr2 = mcp->mb;
..	..	@@ -393,14 +409,14 @@
393	409	uint16_t w;
394	410
395	411	if (IS_FWI2_CAPABLE(ha)) {
396		- mb[0] = RD_REG_WORD(&reg->isp24.mailbox0);
397		- mb[1] = RD_REG_WORD(&reg->isp24.mailbox1);
398		- mb[2] = RD_REG_WORD(&reg->isp24.mailbox2);
399		- mb[3] = RD_REG_WORD(&reg->isp24.mailbox3);
400		- mb[7] = RD_REG_WORD(&reg->isp24.mailbox7);
401		- ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
402		- host_status = RD_REG_DWORD(&reg->isp24.host_status);
403		- hccr = RD_REG_DWORD(&reg->isp24.hccr);
	412	+ mb[0] = rd_reg_word(&reg->isp24.mailbox0);
	413	+ mb[1] = rd_reg_word(&reg->isp24.mailbox1);
	414	+ mb[2] = rd_reg_word(&reg->isp24.mailbox2);
	415	+ mb[3] = rd_reg_word(&reg->isp24.mailbox3);
	416	+ mb[7] = rd_reg_word(&reg->isp24.mailbox7);
	417	+ ictrl = rd_reg_dword(&reg->isp24.ictrl);
	418	+ host_status = rd_reg_dword(&reg->isp24.host_status);
	419	+ hccr = rd_reg_dword(&reg->isp24.hccr);
404	420
405	421	ql_log(ql_log_warn, vha, 0xd04c,
406	422	"MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
..	..	@@ -410,7 +426,7 @@
410	426
411	427	} else {
412	428	mb[0] = RD_MAILBOX_REG(ha, &reg->isp, 0);
413		- ictrl = RD_REG_WORD(&reg->isp.ictrl);
	429	+ ictrl = rd_reg_word(&reg->isp.ictrl);
414	430	ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
415	431	"MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
416	432	"mb[0]=0x%x\n", command, ictrl, jiffies, mb[0]);
..	..	@@ -428,7 +444,10 @@
428	444	* then only PCI ERR flag would be set.
429	445	* we will do premature exit for above case.
430	446	*/
	447	+ spin_lock_irqsave(&ha->hardware_lock, flags);
431	448	ha->flags.mbox_busy = 0;
	449	+ spin_unlock_irqrestore(&ha->hardware_lock,
	450	+ flags);
432	451	rval = QLA_FUNCTION_TIMEOUT;
433	452	goto premature_exit;
434	453	}
..	..	@@ -439,12 +458,13 @@
439	458	* a dump
440	459	*/
441	460	if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
442		- ha->isp_ops->fw_dump(vha, 0);
	461	+ qla2xxx_dump_fw(vha);
443	462	rval = QLA_FUNCTION_TIMEOUT;
444	463	}
445	464	}
446		-
	465	+ spin_lock_irqsave(&ha->hardware_lock, flags);
447	466	ha->flags.mbox_busy = 0;
	467	+ spin_unlock_irqrestore(&ha->hardware_lock, flags);
448	468
449	469	/* Clean up */
450	470	ha->mcp = NULL;
..	..	@@ -534,9 +554,9 @@
534	554	mcp->mb[0]);
535	555	} else if (rval) {
536	556	if (ql2xextended_error_logging & (ql_dbg_disc\|ql_dbg_mbx)) {
537		- pr_warn("%s [%s]-%04x:%ld: **** Failed", QL_MSGHDR,
	557	+ pr_warn("%s [%s]-%04x:%ld: **** Failed=%x", QL_MSGHDR,
538	558	dev_name(&ha->pdev->dev), 0x1020+0x800,
539		- vha->host_no);
	559	+ vha->host_no, rval);
540	560	mboxes = mcp->in_mb;
541	561	cnt = 4;
542	562	for (i = 0; i < ha->mbx_count && cnt; i++, mboxes >>= 1)
..	..	@@ -549,15 +569,15 @@
549	569	if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha))) {
550	570	ql_dbg(ql_dbg_mbx, vha, 0x1198,
551	571	"host_status=%#x intr_ctrl=%#x intr_status=%#x\n",
552		- RD_REG_DWORD(&reg->isp24.host_status),
553		- RD_REG_DWORD(&reg->isp24.ictrl),
554		- RD_REG_DWORD(&reg->isp24.istatus));
	572	+ rd_reg_dword(&reg->isp24.host_status),
	573	+ rd_reg_dword(&reg->isp24.ictrl),
	574	+ rd_reg_dword(&reg->isp24.istatus));
555	575	} else {
556	576	ql_dbg(ql_dbg_mbx, vha, 0x1206,
557	577	"ctrl_status=%#x ictrl=%#x istatus=%#x\n",
558		- RD_REG_WORD(&reg->isp.ctrl_status),
559		- RD_REG_WORD(&reg->isp.ictrl),
560		- RD_REG_WORD(&reg->isp.istatus));
	578	+ rd_reg_word(&reg->isp.ctrl_status),
	579	+ rd_reg_word(&reg->isp.ictrl),
	580	+ rd_reg_word(&reg->isp.istatus));
561	581	}
562	582	} else {
563	583	ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
..	..	@@ -601,14 +621,15 @@
601	621	mcp->out_mb \|= MBX_4;
602	622	}
603	623
604		- mcp->in_mb = MBX_0;
	624	+ mcp->in_mb = MBX_1\|MBX_0;
605	625	mcp->tov = MBX_TOV_SECONDS;
606	626	mcp->flags = 0;
607	627	rval = qla2x00_mailbox_command(vha, mcp);
608	628
609	629	if (rval != QLA_SUCCESS) {
610	630	ql_dbg(ql_dbg_mbx, vha, 0x1023,
611		- "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	631	+ "Failed=%x mb[0]=%x mb[1]=%x.\n",
	632	+ rval, mcp->mb[0], mcp->mb[1]);
612	633	} else {
613	634	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
614	635	"Done %s.\n", __func__);
..	..	@@ -617,30 +638,7 @@
617	638	return rval;
618	639	}
619	640
620		-#define EXTENDED_BB_CREDITS BIT_0
621	641	#define NVME_ENABLE_FLAG BIT_3
622		-static inline uint16_t qla25xx_set_sfp_lr_dist(struct qla_hw_data *ha)
623		-{
624		- uint16_t mb4 = BIT_0;
625		-
626		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
627		- mb4 \|= ha->long_range_distance << LR_DIST_FW_POS;
628		-
629		- return mb4;
630		-}
631		-
632		-static inline uint16_t qla25xx_set_nvr_lr_dist(struct qla_hw_data *ha)
633		-{
634		- uint16_t mb4 = BIT_0;
635		-
636		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
637		- struct nvram_81xx *nv = ha->nvram;
638		-
639		- mb4 \|= LR_DIST_FW_FIELD(nv->enhanced_features);
640		- }
641		-
642		- return mb4;
643		-}
644	642
645	643	/*
646	644	* qla2x00_execute_fw
..	..	@@ -664,10 +662,14 @@
664	662	struct qla_hw_data *ha = vha->hw;
665	663	mbx_cmd_t mc;
666	664	mbx_cmd_t *mcp = &mc;
	665	+ u8 semaphore = 0;
	666	+#define EXE_FW_FORCE_SEMAPHORE BIT_7
	667	+ u8 retry = 3;
667	668
668	669	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
669	670	"Entered %s.\n", __func__);
670	671
	672	+again:
671	673	mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
672	674	mcp->out_mb = MBX_0;
673	675	mcp->in_mb = MBX_0;
..	..	@@ -677,41 +679,33 @@
677	679	mcp->mb[3] = 0;
678	680	mcp->mb[4] = 0;
679	681	mcp->mb[11] = 0;
680		- ha->flags.using_lr_setting = 0;
681		- if (IS_QLA25XX(ha) \|\| IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\|
682		- IS_QLA27XX(ha)) {
683		- if (ql2xautodetectsfp) {
684		- if (ha->flags.detected_lr_sfp) {
685		- mcp->mb[4] \|=
686		- qla25xx_set_sfp_lr_dist(ha);
687		- ha->flags.using_lr_setting = 1;
688		- }
689		- } else {
690		- struct nvram_81xx *nv = ha->nvram;
691		- /* set LR distance if specified in nvram */
692		- if (nv->enhanced_features &
693		- NEF_LR_DIST_ENABLE) {
694		- mcp->mb[4] \|=
695		- qla25xx_set_nvr_lr_dist(ha);
696		- ha->flags.using_lr_setting = 1;
697		- }
698		- }
	682	+
	683	+ /* Enable BPM? */
	684	+ if (ha->flags.lr_detected) {
	685	+ mcp->mb[4] = BIT_0;
	686	+ if (IS_BPM_RANGE_CAPABLE(ha))
	687	+ mcp->mb[4] \|=
	688	+ ha->lr_distance << LR_DIST_FW_POS;
699	689	}
700	690
701		- if (ql2xnvmeenable && IS_QLA27XX(ha))
	691	+ if (ql2xnvmeenable && (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)))
702	692	mcp->mb[4] \|= NVME_ENABLE_FLAG;
703	693
704		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
	694	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
705	695	struct nvram_81xx *nv = ha->nvram;
706	696	/* set minimum speed if specified in nvram */
707		- if (nv->min_link_speed >= 2 &&
708		- nv->min_link_speed <= 5) {
	697	+ if (nv->min_supported_speed >= 2 &&
	698	+ nv->min_supported_speed <= 5) {
709	699	mcp->mb[4] \|= BIT_4;
710		- mcp->mb[11] = nv->min_link_speed;
	700	+ mcp->mb[11] \|= nv->min_supported_speed & 0xF;
711	701	mcp->out_mb \|= MBX_11;
712	702	mcp->in_mb \|= BIT_5;
713		- vha->min_link_speed_feat = nv->min_link_speed;
	703	+ vha->min_supported_speed =
	704	+ nv->min_supported_speed;
714	705	}
	706	+
	707	+ if (IS_PPCARCH)
	708	+ mcp->mb[11] \|= BIT_4;
715	709	}
716	710
717	711	if (ha->flags.exlogins_enabled)
..	..	@@ -719,6 +713,9 @@
719	713
720	714	if (ha->flags.exchoffld_enabled)
721	715	mcp->mb[4] \|= ENABLE_EXCHANGE_OFFLD;
	716	+
	717	+ if (semaphore)
	718	+ mcp->mb[11] \|= EXE_FW_FORCE_SEMAPHORE;
722	719
723	720	mcp->out_mb \|= MBX_4 \| MBX_3 \| MBX_2 \| MBX_1 \| MBX_11;
724	721	mcp->in_mb \|= MBX_3 \| MBX_2 \| MBX_1;
..	..	@@ -736,35 +733,49 @@
736	733	rval = qla2x00_mailbox_command(vha, mcp);
737	734
738	735	if (rval != QLA_SUCCESS) {
	736	+ if (IS_QLA28XX(ha) && rval == QLA_COMMAND_ERROR &&
	737	+ mcp->mb[1] == 0x27 && retry) {
	738	+ semaphore = 1;
	739	+ retry--;
	740	+ ql_dbg(ql_dbg_async, vha, 0x1026,
	741	+ "Exe FW: force semaphore.\n");
	742	+ goto again;
	743	+ }
	744	+
739	745	ql_dbg(ql_dbg_mbx, vha, 0x1026,
740	746	"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
741		- } else {
742		- if (IS_FWI2_CAPABLE(ha)) {
743		- ha->fw_ability_mask = mcp->mb[3] << 16 \| mcp->mb[2];
744		- ql_dbg(ql_dbg_mbx, vha, 0x119a,
745		- "fw_ability_mask=%x.\n", ha->fw_ability_mask);
746		- ql_dbg(ql_dbg_mbx, vha, 0x1027,
747		- "exchanges=%x.\n", mcp->mb[1]);
748		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
749		- ha->max_speed_sup = mcp->mb[2] & BIT_0;
750		- ql_dbg(ql_dbg_mbx, vha, 0x119b,
751		- "Maximum speed supported=%s.\n",
752		- ha->max_speed_sup ? "32Gps" : "16Gps");
753		- if (vha->min_link_speed_feat) {
754		- ha->min_link_speed = mcp->mb[5];
755		- ql_dbg(ql_dbg_mbx, vha, 0x119c,
756		- "Minimum speed set=%s.\n",
757		- mcp->mb[5] == 5 ? "32Gps" :
758		- mcp->mb[5] == 4 ? "16Gps" :
759		- mcp->mb[5] == 3 ? "8Gps" :
760		- mcp->mb[5] == 2 ? "4Gps" :
761		- "unknown");
762		- }
763		- }
764		- }
765		- ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
766		- "Done.\n");
	747	+ return rval;
767	748	}
	749	+
	750	+ if (!IS_FWI2_CAPABLE(ha))
	751	+ goto done;
	752	+
	753	+ ha->fw_ability_mask = mcp->mb[3] << 16 \| mcp->mb[2];
	754	+ ql_dbg(ql_dbg_mbx, vha, 0x119a,
	755	+ "fw_ability_mask=%x.\n", ha->fw_ability_mask);
	756	+ ql_dbg(ql_dbg_mbx, vha, 0x1027, "exchanges=%x.\n", mcp->mb[1]);
	757	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	758	+ ha->max_supported_speed = mcp->mb[2] & (BIT_0\|BIT_1);
	759	+ ql_dbg(ql_dbg_mbx, vha, 0x119b, "max_supported_speed=%s.\n",
	760	+ ha->max_supported_speed == 0 ? "16Gps" :
	761	+ ha->max_supported_speed == 1 ? "32Gps" :
	762	+ ha->max_supported_speed == 2 ? "64Gps" : "unknown");
	763	+ if (vha->min_supported_speed) {
	764	+ ha->min_supported_speed = mcp->mb[5] &
	765	+ (BIT_0 \| BIT_1 \| BIT_2);
	766	+ ql_dbg(ql_dbg_mbx, vha, 0x119c,
	767	+ "min_supported_speed=%s.\n",
	768	+ ha->min_supported_speed == 6 ? "64Gps" :
	769	+ ha->min_supported_speed == 5 ? "32Gps" :
	770	+ ha->min_supported_speed == 4 ? "16Gps" :
	771	+ ha->min_supported_speed == 3 ? "8Gps" :
	772	+ ha->min_supported_speed == 2 ? "4Gps" : "unknown");
	773	+ }
	774	+ }
	775	+
	776	+done:
	777	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
	778	+ "Done %s.\n", __func__);
768	779
769	780	return rval;
770	781	}
..	..	@@ -841,7 +852,7 @@
841	852	* Context:
842	853	* Kernel context.
843	854	*/
844		-#define CONFIG_XLOGINS_MEM 0x3
	855	+#define CONFIG_XLOGINS_MEM 0x9
845	856	int
846	857	qla_set_exlogin_mem_cfg(scsi_qla_host_t *vha, dma_addr_t phys_addr)
847	858	{
..	..	@@ -868,8 +879,9 @@
868	879	mcp->flags = 0;
869	880	rval = qla2x00_mailbox_command(vha, mcp);
870	881	if (rval != QLA_SUCCESS) {
871		- /EMPTY/
872		- ql_dbg(ql_dbg_mbx, vha, 0x111b, "Failed=%x.\n", rval);
	882	+ ql_dbg(ql_dbg_mbx, vha, 0x111b,
	883	+ "EXlogin Failed=%x. MB0=%x MB11=%x\n",
	884	+ rval, mcp->mb[0], mcp->mb[11]);
873	885	} else {
874	886	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
875	887	"Done %s.\n", __func__);
..	..	@@ -1021,10 +1033,10 @@
1021	1033	mcp->in_mb \|= MBX_13\|MBX_12\|MBX_11\|MBX_10\|MBX_9\|MBX_8;
1022	1034	if (IS_FWI2_CAPABLE(ha))
1023	1035	mcp->in_mb \|= MBX_17\|MBX_16\|MBX_15;
1024		- if (IS_QLA27XX(ha))
	1036	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
1025	1037	mcp->in_mb \|=
1026	1038	MBX_25\|MBX_24\|MBX_23\|MBX_22\|MBX_21\|MBX_20\|MBX_19\|MBX_18\|
1027		- MBX_14\|MBX_13\|MBX_11\|MBX_10\|MBX_9\|MBX_8;
	1039	+ MBX_14\|MBX_13\|MBX_11\|MBX_10\|MBX_9\|MBX_8\|MBX_7;
1028	1040
1029	1041	mcp->flags = 0;
1030	1042	mcp->tov = MBX_TOV_SECONDS;
..	..	@@ -1077,15 +1089,31 @@
1077	1089	* FW supports nvme and driver load parameter requested nvme.
1078	1090	* BIT 26 of fw_attributes indicates NVMe support.
1079	1091	*/
1080		- if ((ha->fw_attributes_h & 0x400) && ql2xnvmeenable) {
	1092	+ if ((ha->fw_attributes_h &
	1093	+ (FW_ATTR_H_NVME \| FW_ATTR_H_NVME_UPDATED)) &&
	1094	+ ql2xnvmeenable) {
	1095	+ if (ha->fw_attributes_h & FW_ATTR_H_NVME_FBURST)
	1096	+ vha->flags.nvme_first_burst = 1;
	1097	+
1081	1098	vha->flags.nvme_enabled = 1;
1082	1099	ql_log(ql_log_info, vha, 0xd302,
1083	1100	"%s: FC-NVMe is Enabled (0x%x)\n",
1084	1101	__func__, ha->fw_attributes_h);
1085	1102	}
	1103	+
	1104	+ /* BIT_13 of Extended FW Attributes informs about NVMe2 support */
	1105	+ if (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_NVME2) {
	1106	+ ql_log(ql_log_info, vha, 0xd302,
	1107	+ "Firmware supports NVMe2 0x%x\n",
	1108	+ ha->fw_attributes_ext[0]);
	1109	+ vha->flags.nvme2_enabled = 1;
	1110	+ }
1086	1111	}
1087	1112
1088		- if (IS_QLA27XX(ha)) {
	1113	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	1114	+ ha->serdes_version[0] = mcp->mb[7] & 0xff;
	1115	+ ha->serdes_version[1] = mcp->mb[8] >> 8;
	1116	+ ha->serdes_version[2] = mcp->mb[8] & 0xff;
1089	1117	ha->mpi_version[0] = mcp->mb[10] & 0xff;
1090	1118	ha->mpi_version[1] = mcp->mb[11] >> 8;
1091	1119	ha->mpi_version[2] = mcp->mb[11] & 0xff;
..	..	@@ -1096,6 +1124,31 @@
1096	1124	ha->fw_shared_ram_end = (mcp->mb[21] << 16) \| mcp->mb[20];
1097	1125	ha->fw_ddr_ram_start = (mcp->mb[23] << 16) \| mcp->mb[22];
1098	1126	ha->fw_ddr_ram_end = (mcp->mb[25] << 16) \| mcp->mb[24];
	1127	+ if (IS_QLA28XX(ha)) {
	1128	+ if (mcp->mb[16] & BIT_10)
	1129	+ ha->flags.secure_fw = 1;
	1130	+
	1131	+ ql_log(ql_log_info, vha, 0xffff,
	1132	+ "Secure Flash Update in FW: %s\n",
	1133	+ (ha->flags.secure_fw) ? "Supported" :
	1134	+ "Not Supported");
	1135	+ }
	1136	+
	1137	+ if (ha->flags.scm_supported_a &&
	1138	+ (ha->fw_attributes_ext[0] & FW_ATTR_EXT0_SCM_SUPPORTED)) {
	1139	+ ha->flags.scm_supported_f = 1;
	1140	+ ha->sf_init_cb->flags \|= cpu_to_le16(BIT_13);
	1141	+ }
	1142	+ ql_log(ql_log_info, vha, 0x11a3, "SCM in FW: %s\n",
	1143	+ (ha->flags.scm_supported_f) ? "Supported" :
	1144	+ "Not Supported");
	1145	+
	1146	+ if (vha->flags.nvme2_enabled) {
	1147	+ /* set BIT_15 of special feature control block for SLER */
	1148	+ ha->sf_init_cb->flags \|= cpu_to_le16(BIT_15);
	1149	+ /* set BIT_14 of special feature control block for PI CTRL*/
	1150	+ ha->sf_init_cb->flags \|= cpu_to_le16(BIT_14);
	1151	+ }
1099	1152	}
1100	1153
1101	1154	failed:
..	..	@@ -1358,17 +1411,20 @@
1358	1411	mbx_cmd_t mc;
1359	1412	mbx_cmd_t *mcp = &mc;
1360	1413
	1414	+ if (!vha->hw->flags.fw_started)
	1415	+ return QLA_INVALID_COMMAND;
	1416	+
1361	1417	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
1362	1418	"Entered %s.\n", __func__);
1363	1419
1364	1420	mcp->mb[0] = MBC_IOCB_COMMAND_A64;
1365	1421	mcp->mb[1] = 0;
1366		- mcp->mb[2] = MSW(phys_addr);
1367		- mcp->mb[3] = LSW(phys_addr);
	1422	+ mcp->mb[2] = MSW(LSD(phys_addr));
	1423	+ mcp->mb[3] = LSW(LSD(phys_addr));
1368	1424	mcp->mb[6] = MSW(MSD(phys_addr));
1369	1425	mcp->mb[7] = LSW(MSD(phys_addr));
1370	1426	mcp->out_mb = MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
1371		- mcp->in_mb = MBX_2\|MBX_0;
	1427	+ mcp->in_mb = MBX_1\|MBX_0;
1372	1428	mcp->tov = tov;
1373	1429	mcp->flags = 0;
1374	1430	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -1377,13 +1433,14 @@
1377	1433	/EMPTY/
1378	1434	ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
1379	1435	} else {
1380		- sts_entry_t sts_entry = (sts_entry_t ) buffer;
	1436	+ sts_entry_t *sts_entry = buffer;
1381	1437
1382	1438	/* Mask reserved bits. */
1383	1439	sts_entry->entry_status &=
1384	1440	IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
1385	1441	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
1386		- "Done %s.\n", __func__);
	1442	+ "Done %s (status=%x).\n", __func__,
	1443	+ sts_entry->entry_status);
1387	1444	}
1388	1445
1389	1446	return rval;
..	..	@@ -1428,7 +1485,7 @@
1428	1485	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
1429	1486	"Entered %s.\n", __func__);
1430	1487
1431		- if (vha->flags.qpairs_available && sp->qpair)
	1488	+ if (sp->qpair)
1432	1489	req = sp->qpair->req;
1433	1490	else
1434	1491	req = vha->req;
..	..	@@ -1476,17 +1533,12 @@
1476	1533	mbx_cmd_t mc;
1477	1534	mbx_cmd_t *mcp = &mc;
1478	1535	scsi_qla_host_t *vha;
1479		- struct req_que *req;
1480		- struct rsp_que *rsp;
1481	1536
1482		- l = l;
1483	1537	vha = fcport->vha;
1484	1538
1485	1539	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
1486	1540	"Entered %s.\n", __func__);
1487	1541
1488		- req = vha->hw->req_q_map[0];
1489		- rsp = req->rsp;
1490	1542	mcp->mb[0] = MBC_ABORT_TARGET;
1491	1543	mcp->out_mb = MBX_9\|MBX_2\|MBX_1\|MBX_0;
1492	1544	if (HAS_EXTENDED_IDS(vha->hw)) {
..	..	@@ -1509,7 +1561,7 @@
1509	1561	}
1510	1562
1511	1563	/* Issue marker IOCB. */
1512		- rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
	1564	+ rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, 0,
1513	1565	MK_SYNC_ID);
1514	1566	if (rval2 != QLA_SUCCESS) {
1515	1567	ql_dbg(ql_dbg_mbx, vha, 0x1040,
..	..	@@ -1529,16 +1581,12 @@
1529	1581	mbx_cmd_t mc;
1530	1582	mbx_cmd_t *mcp = &mc;
1531	1583	scsi_qla_host_t *vha;
1532		- struct req_que *req;
1533		- struct rsp_que *rsp;
1534	1584
1535	1585	vha = fcport->vha;
1536	1586
1537	1587	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
1538	1588	"Entered %s.\n", __func__);
1539	1589
1540		- req = vha->hw->req_q_map[0];
1541		- rsp = req->rsp;
1542	1590	mcp->mb[0] = MBC_LUN_RESET;
1543	1591	mcp->out_mb = MBX_9\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
1544	1592	if (HAS_EXTENDED_IDS(vha->hw))
..	..	@@ -1558,7 +1606,7 @@
1558	1606	}
1559	1607
1560	1608	/* Issue marker IOCB. */
1561		- rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
	1609	+ rval2 = qla2x00_marker(vha, vha->hw->base_qpair, fcport->loop_id, l,
1562	1610	MK_SYNC_ID_LUN);
1563	1611	if (rval2 != QLA_SUCCESS) {
1564	1612	ql_dbg(ql_dbg_mbx, vha, 0x1044,
..	..	@@ -1610,8 +1658,9 @@
1610	1658	mcp->in_mb \|= MBX_13\|MBX_12\|MBX_11\|MBX_10;
1611	1659	if (IS_FWI2_CAPABLE(vha->hw))
1612	1660	mcp->in_mb \|= MBX_19\|MBX_18\|MBX_17\|MBX_16;
1613		- if (IS_QLA27XX(vha->hw))
1614		- mcp->in_mb \|= MBX_15;
	1661	+ if (IS_QLA27XX(vha->hw) \|\| IS_QLA28XX(vha->hw))
	1662	+ mcp->in_mb \|= MBX_15\|MBX_21\|MBX_22\|MBX_23;
	1663	+
1615	1664	mcp->tov = MBX_TOV_SECONDS;
1616	1665	mcp->flags = 0;
1617	1666	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -1664,8 +1713,22 @@
1664	1713	}
1665	1714	}
1666	1715
1667		- if (IS_QLA27XX(vha->hw))
	1716	+ if (IS_QLA27XX(vha->hw) \|\| IS_QLA28XX(vha->hw)) {
1668	1717	vha->bbcr = mcp->mb[15];
	1718	+ if (mcp->mb[7] & SCM_EDC_ACC_RECEIVED) {
	1719	+ ql_log(ql_log_info, vha, 0x11a4,
	1720	+ "SCM: EDC ELS completed, flags 0x%x\n",
	1721	+ mcp->mb[21]);
	1722	+ }
	1723	+ if (mcp->mb[7] & SCM_RDF_ACC_RECEIVED) {
	1724	+ vha->hw->flags.scm_enabled = 1;
	1725	+ vha->scm_fabric_connection_flags \|=
	1726	+ SCM_FLAG_RDF_COMPLETED;
	1727	+ ql_log(ql_log_info, vha, 0x11a5,
	1728	+ "SCM: RDF ELS completed, flags 0x%x\n",
	1729	+ mcp->mb[23]);
	1730	+ }
	1731	+ }
1669	1732	}
1670	1733
1671	1734	return rval;
..	..	@@ -1778,9 +1841,20 @@
1778	1841	mcp->mb[14] = sizeof(*ha->ex_init_cb);
1779	1842	mcp->out_mb \|= MBX_14\|MBX_13\|MBX_12\|MBX_11\|MBX_10;
1780	1843	}
	1844	+
	1845	+ if (ha->flags.scm_supported_f \|\| vha->flags.nvme2_enabled) {
	1846	+ mcp->mb[1] \|= BIT_1;
	1847	+ mcp->mb[16] = MSW(ha->sf_init_cb_dma);
	1848	+ mcp->mb[17] = LSW(ha->sf_init_cb_dma);
	1849	+ mcp->mb[18] = MSW(MSD(ha->sf_init_cb_dma));
	1850	+ mcp->mb[19] = LSW(MSD(ha->sf_init_cb_dma));
	1851	+ mcp->mb[15] = sizeof(*ha->sf_init_cb);
	1852	+ mcp->out_mb \|= MBX_19\|MBX_18\|MBX_17\|MBX_16\|MBX_15;
	1853	+ }
	1854	+
1781	1855	/* 1 and 2 should normally be captured. */
1782	1856	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
1783		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	1857	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
1784	1858	/* mb3 is additional info about the installed SFP. */
1785	1859	mcp->in_mb \|= MBX_3;
1786	1860	mcp->buf_size = size;
..	..	@@ -1791,10 +1865,20 @@
1791	1865	if (rval != QLA_SUCCESS) {
1792	1866	/EMPTY/
1793	1867	ql_dbg(ql_dbg_mbx, vha, 0x104d,
1794		- "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
	1868	+ "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x.\n",
1795	1869	rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
	1870	+ if (ha->init_cb) {
	1871	+ ql_dbg(ql_dbg_mbx, vha, 0x104d, "init_cb:\n");
	1872	+ ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
	1873	+ 0x0104d, ha->init_cb, sizeof(*ha->init_cb));
	1874	+ }
	1875	+ if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
	1876	+ ql_dbg(ql_dbg_mbx, vha, 0x104d, "ex_init_cb:\n");
	1877	+ ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha,
	1878	+ 0x0104d, ha->ex_init_cb, sizeof(*ha->ex_init_cb));
	1879	+ }
1796	1880	} else {
1797		- if (IS_QLA27XX(ha)) {
	1881	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
1798	1882	if (mcp->mb[2] == 6 \|\| mcp->mb[3] == 2)
1799	1883	ql_dbg(ql_dbg_mbx, vha, 0x119d,
1800	1884	"Invalid SFP/Validation Failed\n");
..	..	@@ -1884,7 +1968,7 @@
1884	1968	pd24 = (struct port_database_24xx *) pd;
1885	1969
1886	1970	/* Check for logged in state. */
1887		- if (fcport->fc4f_nvme) {
	1971	+ if (NVME_TARGET(ha, fcport)) {
1888	1972	current_login_state = pd24->current_login_state >> 4;
1889	1973	last_login_state = pd24->last_login_state >> 4;
1890	1974	} else {
..	..	@@ -1978,7 +2062,7 @@
1978	2062
1979	2063	/* Passback COS information. */
1980	2064	fcport->supported_classes = (pd->options & BIT_4) ?
1981		- FC_COS_CLASS2: FC_COS_CLASS3;
	2065	+ FC_COS_CLASS2 : FC_COS_CLASS3;
1982	2066	}
1983	2067
1984	2068	gpd_error_out:
..	..	@@ -1993,6 +2077,57 @@
1993	2077	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
1994	2078	"Done %s.\n", __func__);
1995	2079	}
	2080	+
	2081	+ return rval;
	2082	+}
	2083	+
	2084	+int
	2085	+qla24xx_get_port_database(scsi_qla_host_t *vha, u16 nport_handle,
	2086	+ struct port_database_24xx *pdb)
	2087	+{
	2088	+ mbx_cmd_t mc;
	2089	+ mbx_cmd_t *mcp = &mc;
	2090	+ dma_addr_t pdb_dma;
	2091	+ int rval;
	2092	+
	2093	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1115,
	2094	+ "Entered %s.\n", __func__);
	2095	+
	2096	+ memset(pdb, 0, sizeof(*pdb));
	2097	+
	2098	+ pdb_dma = dma_map_single(&vha->hw->pdev->dev, pdb,
	2099	+ sizeof(*pdb), DMA_FROM_DEVICE);
	2100	+ if (!pdb_dma) {
	2101	+ ql_log(ql_log_warn, vha, 0x1116, "Failed to map dma buffer.\n");
	2102	+ return QLA_MEMORY_ALLOC_FAILED;
	2103	+ }
	2104	+
	2105	+ mcp->mb[0] = MBC_GET_PORT_DATABASE;
	2106	+ mcp->mb[1] = nport_handle;
	2107	+ mcp->mb[2] = MSW(LSD(pdb_dma));
	2108	+ mcp->mb[3] = LSW(LSD(pdb_dma));
	2109	+ mcp->mb[6] = MSW(MSD(pdb_dma));
	2110	+ mcp->mb[7] = LSW(MSD(pdb_dma));
	2111	+ mcp->mb[9] = 0;
	2112	+ mcp->mb[10] = 0;
	2113	+ mcp->out_mb = MBX_10\|MBX_9\|MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	2114	+ mcp->in_mb = MBX_1\|MBX_0;
	2115	+ mcp->buf_size = sizeof(*pdb);
	2116	+ mcp->flags = MBX_DMA_IN;
	2117	+ mcp->tov = vha->hw->login_timeout * 2;
	2118	+ rval = qla2x00_mailbox_command(vha, mcp);
	2119	+
	2120	+ if (rval != QLA_SUCCESS) {
	2121	+ ql_dbg(ql_dbg_mbx, vha, 0x111a,
	2122	+ "Failed=%x mb[0]=%x mb[1]=%x.\n",
	2123	+ rval, mcp->mb[0], mcp->mb[1]);
	2124	+ } else {
	2125	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111b,
	2126	+ "Done %s.\n", __func__);
	2127	+ }
	2128	+
	2129	+ dma_unmap_single(&vha->hw->pdev->dev, pdb_dma,
	2130	+ sizeof(*pdb), DMA_FROM_DEVICE);
1996	2131
1997	2132	return rval;
1998	2133	}
..	..	@@ -2048,7 +2183,7 @@
2048	2183	/EMPTY/
2049	2184	ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
2050	2185	} else {
2051		- if (IS_QLA27XX(ha)) {
	2186	+ if (IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
2052	2187	if (mcp->mb[2] == 6 \|\| mcp->mb[3] == 2)
2053	2188	ql_dbg(ql_dbg_mbx, vha, 0x119e,
2054	2189	"Invalid SFP/Validation Failed\n");
..	..	@@ -2202,7 +2337,7 @@
2202	2337	mbx_cmd_t mc;
2203	2338	mbx_cmd_t *mcp = &mc;
2204	2339
2205		- ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
	2340	+ ql_dbg(ql_dbg_disc, vha, 0x105a,
2206	2341	"Entered %s.\n", __func__);
2207	2342
2208	2343	if (IS_CNA_CAPABLE(vha->hw)) {
..	..	@@ -2213,10 +2348,7 @@
2213	2348	mcp->out_mb = MBX_2\|MBX_1\|MBX_0;
2214	2349	} else if (IS_FWI2_CAPABLE(vha->hw)) {
2215	2350	mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2216		- if (N2N_TOPO(vha->hw))
2217		- mcp->mb[1] = BIT_4; /* re-init */
2218		- else
2219		- mcp->mb[1] = BIT_6; /* LIP */
	2351	+ mcp->mb[1] = BIT_4;
2220	2352	mcp->mb[2] = 0;
2221	2353	mcp->mb[3] = vha->hw->loop_reset_delay;
2222	2354	mcp->out_mb = MBX_3\|MBX_2\|MBX_1\|MBX_0;
..	..	@@ -2339,7 +2471,7 @@
2339	2471
2340	2472	lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2341	2473	lg->entry_count = 1;
2342		- lg->handle = MAKE_HANDLE(req->id, lg->handle);
	2474	+ lg->handle = make_handle(req->id, lg->handle);
2343	2475	lg->nport_handle = cpu_to_le16(loop_id);
2344	2476	lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
2345	2477	if (opt & BIT_0)
..	..	@@ -2609,7 +2741,7 @@
2609	2741	req = vha->req;
2610	2742	lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
2611	2743	lg->entry_count = 1;
2612		- lg->handle = MAKE_HANDLE(req->id, lg->handle);
	2744	+ lg->handle = make_handle(req->id, lg->handle);
2613	2745	lg->nport_handle = cpu_to_le16(loop_id);
2614	2746	lg->control_flags =
2615	2747	cpu_to_le16(LCF_COMMAND_LOGO\|LCF_IMPL_LOGO\|
..	..	@@ -2726,7 +2858,7 @@
2726	2858	"Entered %s.\n", __func__);
2727	2859
2728	2860	mcp->mb[0] = MBC_LIP_FULL_LOGIN;
2729		- mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
	2861	+ mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_4 : 0;
2730	2862	mcp->mb[2] = 0;
2731	2863	mcp->mb[3] = 0;
2732	2864	mcp->out_mb = MBX_3\|MBX_2\|MBX_1\|MBX_0;
..	..	@@ -2834,7 +2966,8 @@
2834	2966	mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2835	2967	mcp->out_mb = MBX_0;
2836	2968	mcp->in_mb = MBX_11\|MBX_10\|MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
2837		- if (IS_QLA81XX(vha->hw) \|\| IS_QLA83XX(vha->hw) \|\| IS_QLA27XX(vha->hw))
	2969	+ if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\|
	2970	+ IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
2838	2971	mcp->in_mb \|= MBX_12;
2839	2972	mcp->tov = MBX_TOV_SECONDS;
2840	2973	mcp->flags = 0;
..	..	@@ -2859,7 +2992,7 @@
2859	2992	ha->orig_fw_iocb_count = mcp->mb[10];
2860	2993	if (ha->flags.npiv_supported)
2861	2994	ha->max_npiv_vports = mcp->mb[11];
2862		- if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	2995	+ if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha))
2863	2996	ha->fw_max_fcf_count = mcp->mb[12];
2864	2997	}
2865	2998
..	..	@@ -2881,7 +3014,8 @@
2881	3014	* Kernel context.
2882	3015	*/
2883	3016	int
2884		-qla2x00_get_fcal_position_map(scsi_qla_host_t vha, char pos_map)
	3017	+qla2x00_get_fcal_position_map(scsi_qla_host_t vha, char pos_map,
	3018	+ u8 *num_entries)
2885	3019	{
2886	3020	int rval;
2887	3021	mbx_cmd_t mc;
..	..	@@ -2921,6 +3055,8 @@
2921	3055
2922	3056	if (pos_map)
2923	3057	memcpy(pos_map, pmap, FCAL_MAP_SIZE);
	3058	+ if (num_entries)
	3059	+ *num_entries = pmap[0];
2924	3060	}
2925	3061	dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2926	3062
..	..	@@ -2954,7 +3090,7 @@
2954	3090	int rval;
2955	3091	mbx_cmd_t mc;
2956	3092	mbx_cmd_t *mcp = &mc;
2957		- uint32_t iter = (void )stats;
	3093	+ uint32_t iter = (uint32_t )stats;
2958	3094	ushort dwords = offsetof(typeof(stats), link_up_cnt)/sizeof(iter);
2959	3095	struct qla_hw_data *ha = vha->hw;
2960	3096
..	..	@@ -3013,20 +3149,21 @@
3013	3149	int rval;
3014	3150	mbx_cmd_t mc;
3015	3151	mbx_cmd_t *mcp = &mc;
3016		- uint32_t *iter, dwords;
	3152	+ uint32_t iter = (uint32_t )stats;
	3153	+ ushort dwords = sizeof(stats)/sizeof(iter);
3017	3154
3018	3155	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
3019	3156	"Entered %s.\n", __func__);
3020	3157
3021	3158	memset(&mc, 0, sizeof(mc));
3022	3159	mc.mb[0] = MBC_GET_LINK_PRIV_STATS;
3023		- mc.mb[2] = MSW(stats_dma);
3024		- mc.mb[3] = LSW(stats_dma);
	3160	+ mc.mb[2] = MSW(LSD(stats_dma));
	3161	+ mc.mb[3] = LSW(LSD(stats_dma));
3025	3162	mc.mb[6] = MSW(MSD(stats_dma));
3026	3163	mc.mb[7] = LSW(MSD(stats_dma));
3027		- mc.mb[8] = sizeof(struct link_statistics) / 4;
3028		- mc.mb[9] = cpu_to_le16(vha->vp_idx);
3029		- mc.mb[10] = cpu_to_le16(options);
	3164	+ mc.mb[8] = dwords;
	3165	+ mc.mb[9] = vha->vp_idx;
	3166	+ mc.mb[10] = options;
3030	3167
3031	3168	rval = qla24xx_send_mb_cmd(vha, &mc);
3032	3169
..	..	@@ -3039,8 +3176,6 @@
3039	3176	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
3040	3177	"Done %s.\n", __func__);
3041	3178	/* Re-endianize - firmware data is le32. */
3042		- dwords = sizeof(struct link_statistics) / 4;
3043		- iter = &stats->link_fail_cnt;
3044	3179	for ( ; dwords--; iter++)
3045	3180	le32_to_cpus(iter);
3046	3181	}
..	..	@@ -3065,22 +3200,25 @@
3065	3200	struct scsi_qla_host *vha = fcport->vha;
3066	3201	struct qla_hw_data *ha = vha->hw;
3067	3202	struct req_que *req = vha->req;
	3203	+ struct qla_qpair *qpair = sp->qpair;
3068	3204
3069	3205	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
3070	3206	"Entered %s.\n", __func__);
3071	3207
3072	3208	if (sp->qpair)
3073	3209	req = sp->qpair->req;
	3210	+ else
	3211	+ return QLA_FUNCTION_FAILED;
3074	3212
3075	3213	if (ql2xasynctmfenable)
3076	3214	return qla24xx_async_abort_command(sp);
3077	3215
3078		- spin_lock_irqsave(&ha->hardware_lock, flags);
	3216	+ spin_lock_irqsave(qpair->qp_lock_ptr, flags);
3079	3217	for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
3080	3218	if (req->outstanding_cmds[handle] == sp)
3081	3219	break;
3082	3220	}
3083		- spin_unlock_irqrestore(&ha->hardware_lock, flags);
	3221	+ spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
3084	3222	if (handle == req->num_outstanding_cmds) {
3085	3223	/* Command not found. */
3086	3224	return QLA_FUNCTION_FAILED;
..	..	@@ -3095,9 +3233,9 @@
3095	3233
3096	3234	abt->entry_type = ABORT_IOCB_TYPE;
3097	3235	abt->entry_count = 1;
3098		- abt->handle = MAKE_HANDLE(req->id, abt->handle);
	3236	+ abt->handle = make_handle(req->id, abt->handle);
3099	3237	abt->nport_handle = cpu_to_le16(fcport->loop_id);
3100		- abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
	3238	+ abt->handle_to_abort = make_handle(req->id, handle);
3101	3239	abt->port_id[0] = fcport->d_id.b.al_pa;
3102	3240	abt->port_id[1] = fcport->d_id.b.area;
3103	3241	abt->port_id[2] = fcport->d_id.b.domain;
..	..	@@ -3118,7 +3256,7 @@
3118	3256	ql_dbg(ql_dbg_mbx, vha, 0x1090,
3119	3257	"Failed to complete IOCB -- completion status (%x).\n",
3120	3258	le16_to_cpu(abt->nport_handle));
3121		- if (abt->nport_handle == CS_IOCB_ERROR)
	3259	+ if (abt->nport_handle == cpu_to_le16(CS_IOCB_ERROR))
3122	3260	rval = QLA_FUNCTION_PARAMETER_ERROR;
3123	3261	else
3124	3262	rval = QLA_FUNCTION_FAILED;
..	..	@@ -3150,7 +3288,6 @@
3150	3288	scsi_qla_host_t *vha;
3151	3289	struct qla_hw_data *ha;
3152	3290	struct req_que *req;
3153		- struct rsp_que *rsp;
3154	3291	struct qla_qpair *qpair;
3155	3292
3156	3293	vha = fcport->vha;
..	..	@@ -3163,10 +3300,7 @@
3163	3300	if (vha->vp_idx && vha->qpair) {
3164	3301	/* NPIV port */
3165	3302	qpair = vha->qpair;
3166		- rsp = qpair->rsp;
3167	3303	req = qpair->req;
3168		- } else {
3169		- rsp = req->rsp;
3170	3304	}
3171	3305
3172	3306	tsk = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
..	..	@@ -3178,7 +3312,7 @@
3178	3312
3179	3313	tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
3180	3314	tsk->p.tsk.entry_count = 1;
3181		- tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
	3315	+ tsk->p.tsk.handle = make_handle(req->id, tsk->p.tsk.handle);
3182	3316	tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
3183	3317	tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
3184	3318	tsk->p.tsk.control_flags = cpu_to_le32(type);
..	..	@@ -3223,8 +3357,8 @@
3223	3357	}
3224	3358
3225	3359	/* Issue marker IOCB. */
3226		- rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
3227		- type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
	3360	+ rval2 = qla2x00_marker(vha, ha->base_qpair, fcport->loop_id, l,
	3361	+ type == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
3228	3362	if (rval2 != QLA_SUCCESS) {
3229	3363	ql_dbg(ql_dbg_mbx, vha, 0x1099,
3230	3364	"Failed to issue marker IOCB (%x).\n", rval2);
..	..	@@ -3299,7 +3433,7 @@
3299	3433	mbx_cmd_t *mcp = &mc;
3300	3434
3301	3435	if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3302		- !IS_QLA27XX(vha->hw))
	3436	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
3303	3437	return QLA_FUNCTION_FAILED;
3304	3438
3305	3439	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
..	..	@@ -3338,7 +3472,7 @@
3338	3472	mbx_cmd_t *mcp = &mc;
3339	3473
3340	3474	if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
3341		- !IS_QLA27XX(vha->hw))
	3475	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
3342	3476	return QLA_FUNCTION_FAILED;
3343	3477
3344	3478	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
..	..	@@ -3444,9 +3578,9 @@
3444	3578	/**
3445	3579	* qla2x00_set_serdes_params() -
3446	3580	* @vha: HA context
3447		- * @sw_em_1g:
3448		- * @sw_em_2g:
3449		- * @sw_em_4g:
	3581	+ * @sw_em_1g: serial link options
	3582	+ * @sw_em_2g: serial link options
	3583	+ * @sw_em_4g: serial link options
3450	3584	*
3451	3585	* Returns
3452	3586	*/
..	..	@@ -3607,7 +3741,8 @@
3607	3741	"Entered %s.\n", __func__);
3608	3742
3609	3743	if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
3610		- !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
	3744	+ !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
	3745	+ !IS_QLA28XX(vha->hw))
3611	3746	return QLA_FUNCTION_FAILED;
3612	3747
3613	3748	if (unlikely(pci_channel_offline(vha->hw->pdev)))
..	..	@@ -3720,7 +3855,7 @@
3720	3855	rval = qla2x00_mailbox_command(vha, mcp);
3721	3856
3722	3857	/* Return mailbox statuses. */
3723		- if (mb != NULL) {
	3858	+ if (mb) {
3724	3859	mb[0] = mcp->mb[0];
3725	3860	mb[1] = mcp->mb[1];
3726	3861	mb[3] = mcp->mb[3];
..	..	@@ -3755,7 +3890,7 @@
3755	3890	mcp->mb[0] = MBC_PORT_PARAMS;
3756	3891	mcp->mb[1] = loop_id;
3757	3892	mcp->mb[2] = BIT_0;
3758		- mcp->mb[3] = port_speed & (BIT_5\|BIT_4\|BIT_3\|BIT_2\|BIT_1\|BIT_0);
	3893	+ mcp->mb[3] = port_speed & 0x3F;
3759	3894	mcp->mb[9] = vha->vp_idx;
3760	3895	mcp->out_mb = MBX_9\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
3761	3896	mcp->in_mb = MBX_3\|MBX_1\|MBX_0;
..	..	@@ -3764,7 +3899,7 @@
3764	3899	rval = qla2x00_mailbox_command(vha, mcp);
3765	3900
3766	3901	/* Return mailbox statuses. */
3767		- if (mb != NULL) {
	3902	+ if (mb) {
3768	3903	mb[0] = mcp->mb[0];
3769	3904	mb[1] = mcp->mb[1];
3770	3905	mb[3] = mcp->mb[3];
..	..	@@ -3837,14 +3972,46 @@
3837	3972	case TOPO_N2N:
3838	3973	ha->current_topology = ISP_CFG_N;
3839	3974	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
	3975	+ list_for_each_entry(fcport, &vha->vp_fcports, list) {
	3976	+ fcport->scan_state = QLA_FCPORT_SCAN;
	3977	+ fcport->n2n_flag = 0;
	3978	+ }
	3979	+ id.b24 = 0;
	3980	+ if (wwn_to_u64(vha->port_name) >
	3981	+ wwn_to_u64(rptid_entry->u.f1.port_name)) {
	3982	+ vha->d_id.b24 = 0;
	3983	+ vha->d_id.b.al_pa = 1;
	3984	+ ha->flags.n2n_bigger = 1;
	3985	+
	3986	+ id.b.al_pa = 2;
	3987	+ ql_dbg(ql_dbg_async, vha, 0x5075,
	3988	+ "Format 1: assign local id %x remote id %x\n",
	3989	+ vha->d_id.b24, id.b24);
	3990	+ } else {
	3991	+ ql_dbg(ql_dbg_async, vha, 0x5075,
	3992	+ "Format 1: Remote login - Waiting for WWPN %8phC.\n",
	3993	+ rptid_entry->u.f1.port_name);
	3994	+ ha->flags.n2n_bigger = 0;
	3995	+ }
	3996	+
3840	3997	fcport = qla2x00_find_fcport_by_wwpn(vha,
3841	3998	rptid_entry->u.f1.port_name, 1);
3842	3999	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
3843	4000
	4001	+
3844	4002	if (fcport) {
3845	4003	fcport->plogi_nack_done_deadline = jiffies + HZ;
3846		- fcport->dm_login_expire = jiffies + 3*HZ;
	4004	+ fcport->dm_login_expire = jiffies +
	4005	+ QLA_N2N_WAIT_TIME * HZ;
3847	4006	fcport->scan_state = QLA_FCPORT_FOUND;
	4007	+ fcport->n2n_flag = 1;
	4008	+ fcport->keep_nport_handle = 1;
	4009	+
	4010	+ if (wwn_to_u64(vha->port_name) >
	4011	+ wwn_to_u64(fcport->port_name)) {
	4012	+ fcport->d_id = id;
	4013	+ }
	4014	+
3848	4015	switch (fcport->disc_state) {
3849	4016	case DSC_DELETED:
3850	4017	set_bit(RELOGIN_NEEDED,
..	..	@@ -3857,30 +4024,11 @@
3857	4024	break;
3858	4025	}
3859	4026	} else {
3860		- id.b24 = 0;
3861		- if (wwn_to_u64(vha->port_name) >
3862		- wwn_to_u64(rptid_entry->u.f1.port_name)) {
3863		- vha->d_id.b24 = 0;
3864		- vha->d_id.b.al_pa = 1;
3865		- ha->flags.n2n_bigger = 1;
3866		- ha->flags.n2n_ae = 0;
3867		-
3868		- id.b.al_pa = 2;
3869		- ql_dbg(ql_dbg_async, vha, 0x5075,
3870		- "Format 1: assign local id %x remote id %x\n",
3871		- vha->d_id.b24, id.b24);
3872		- } else {
3873		- ql_dbg(ql_dbg_async, vha, 0x5075,
3874		- "Format 1: Remote login - Waiting for WWPN %8phC.\n",
3875		- rptid_entry->u.f1.port_name);
3876		- ha->flags.n2n_bigger = 0;
3877		- ha->flags.n2n_ae = 1;
3878		- }
3879	4027	qla24xx_post_newsess_work(vha, &id,
3880	4028	rptid_entry->u.f1.port_name,
3881	4029	rptid_entry->u.f1.node_name,
3882	4030	NULL,
3883		- FC4_TYPE_UNKNOWN);
	4031	+ FS_FCP_IS_N2N);
3884	4032	}
3885	4033
3886	4034	/* if our portname is higher then initiate N2N login */
..	..	@@ -3978,6 +4126,7 @@
3978	4126
3979	4127	list_for_each_entry(fcport, &vha->vp_fcports, list) {
3980	4128	fcport->scan_state = QLA_FCPORT_SCAN;
	4129	+ fcport->n2n_flag = 0;
3981	4130	}
3982	4131
3983	4132	fcport = qla2x00_find_fcport_by_wwpn(vha,
..	..	@@ -3987,6 +4136,14 @@
3987	4136	fcport->login_retry = vha->hw->login_retry_count;
3988	4137	fcport->plogi_nack_done_deadline = jiffies + HZ;
3989	4138	fcport->scan_state = QLA_FCPORT_FOUND;
	4139	+ fcport->keep_nport_handle = 1;
	4140	+ fcport->n2n_flag = 1;
	4141	+ fcport->d_id.b.domain =
	4142	+ rptid_entry->u.f2.remote_nport_id[2];
	4143	+ fcport->d_id.b.area =
	4144	+ rptid_entry->u.f2.remote_nport_id[1];
	4145	+ fcport->d_id.b.al_pa =
	4146	+ rptid_entry->u.f2.remote_nport_id[0];
3990	4147	}
3991	4148	}
3992	4149	}
..	..	@@ -4128,7 +4285,8 @@
4128	4285	if (MSW(addr) \|\| IS_FWI2_CAPABLE(vha->hw)) {
4129	4286	mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
4130	4287	mcp->mb[8] = MSW(addr);
4131		- mcp->out_mb = MBX_8\|MBX_0;
	4288	+ mcp->mb[10] = 0;
	4289	+ mcp->out_mb = MBX_10\|MBX_8\|MBX_0;
4132	4290	} else {
4133	4291	mcp->mb[0] = MBC_DUMP_RISC_RAM;
4134	4292	mcp->out_mb = MBX_0;
..	..	@@ -4207,7 +4365,7 @@
4207	4365	ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
4208	4366	"Dump of Verify Request.\n");
4209	4367	ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
4210		- (uint8_t )mn, sizeof(mn));
	4368	+ mn, sizeof(*mn));
4211	4369
4212	4370	rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
4213	4371	if (rval != QLA_SUCCESS) {
..	..	@@ -4219,7 +4377,7 @@
4219	4377	ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
4220	4378	"Dump of Verify Response.\n");
4221	4379	ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
4222		- (uint8_t )mn, sizeof(mn));
	4380	+ mn, sizeof(*mn));
4223	4381
4224	4382	status[0] = le16_to_cpu(mn->p.rsp.comp_status);
4225	4383	status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
..	..	@@ -4295,7 +4453,7 @@
4295	4453	mcp->mb[12] = req->qos;
4296	4454	mcp->mb[11] = req->vp_idx;
4297	4455	mcp->mb[13] = req->rid;
4298		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4456	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
4299	4457	mcp->mb[15] = 0;
4300	4458
4301	4459	mcp->mb[4] = req->id;
..	..	@@ -4309,9 +4467,10 @@
4309	4467	mcp->flags = MBX_DMA_OUT;
4310	4468	mcp->tov = MBX_TOV_SECONDS * 2;
4311	4469
4312		- if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4470	+ if (IS_QLA81XX(ha) \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\|
	4471	+ IS_QLA28XX(ha))
4313	4472	mcp->in_mb \|= MBX_1;
4314		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
	4473	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
4315	4474	mcp->out_mb \|= MBX_15;
4316	4475	/* debug q create issue in SR-IOV */
4317	4476	mcp->in_mb \|= MBX_9 \| MBX_8 \| MBX_7;
..	..	@@ -4319,9 +4478,9 @@
4319	4478
4320	4479	spin_lock_irqsave(&ha->hardware_lock, flags);
4321	4480	if (!(req->options & BIT_0)) {
4322		- WRT_REG_DWORD(req->req_q_in, 0);
4323		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
4324		- WRT_REG_DWORD(req->req_q_out, 0);
	4481	+ wrt_reg_dword(req->req_q_in, 0);
	4482	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	4483	+ wrt_reg_dword(req->req_q_out, 0);
4325	4484	}
4326	4485	spin_unlock_irqrestore(&ha->hardware_lock, flags);
4327	4486
..	..	@@ -4364,7 +4523,7 @@
4364	4523	mcp->mb[5] = rsp->length;
4365	4524	mcp->mb[14] = rsp->msix->entry;
4366	4525	mcp->mb[13] = rsp->rid;
4367		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
	4526	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
4368	4527	mcp->mb[15] = 0;
4369	4528
4370	4529	mcp->mb[4] = rsp->id;
..	..	@@ -4381,7 +4540,7 @@
4381	4540	if (IS_QLA81XX(ha)) {
4382	4541	mcp->out_mb \|= MBX_12\|MBX_11\|MBX_10;
4383	4542	mcp->in_mb \|= MBX_1;
4384		- } else if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha)) {
	4543	+ } else if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
4385	4544	mcp->out_mb \|= MBX_15\|MBX_12\|MBX_11\|MBX_10;
4386	4545	mcp->in_mb \|= MBX_1;
4387	4546	/* debug q create issue in SR-IOV */
..	..	@@ -4390,9 +4549,9 @@
4390	4549
4391	4550	spin_lock_irqsave(&ha->hardware_lock, flags);
4392	4551	if (!(rsp->options & BIT_0)) {
4393		- WRT_REG_DWORD(rsp->rsp_q_out, 0);
4394		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
4395		- WRT_REG_DWORD(rsp->rsp_q_in, 0);
	4552	+ wrt_reg_dword(rsp->rsp_q_out, 0);
	4553	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	4554	+ wrt_reg_dword(rsp->rsp_q_in, 0);
4396	4555	}
4397	4556
4398	4557	spin_unlock_irqrestore(&ha->hardware_lock, flags);
..	..	@@ -4449,7 +4608,7 @@
4449	4608	"Entered %s.\n", __func__);
4450	4609
4451	4610	if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4452		- !IS_QLA27XX(vha->hw))
	4611	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4453	4612	return QLA_FUNCTION_FAILED;
4454	4613
4455	4614	mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
..	..	@@ -4481,7 +4640,7 @@
4481	4640	mbx_cmd_t *mcp = &mc;
4482	4641
4483	4642	if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4484		- !IS_QLA27XX(vha->hw))
	4643	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4485	4644	return QLA_FUNCTION_FAILED;
4486	4645
4487	4646	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
..	..	@@ -4516,7 +4675,7 @@
4516	4675	mbx_cmd_t *mcp = &mc;
4517	4676
4518	4677	if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
4519		- !IS_QLA27XX(vha->hw))
	4678	+ !IS_QLA27XX(vha->hw) && !IS_QLA28XX(vha->hw))
4520	4679	return QLA_FUNCTION_FAILED;
4521	4680
4522	4681	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
..	..	@@ -4530,6 +4689,42 @@
4530	4689	mcp->mb[5] = MSW(finish);
4531	4690	mcp->out_mb = MBX_5\|MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
4532	4691	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
	4692	+ mcp->tov = MBX_TOV_SECONDS;
	4693	+ mcp->flags = 0;
	4694	+ rval = qla2x00_mailbox_command(vha, mcp);
	4695	+
	4696	+ if (rval != QLA_SUCCESS) {
	4697	+ ql_dbg(ql_dbg_mbx, vha, 0x10e3,
	4698	+ "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
	4699	+ rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
	4700	+ } else {
	4701	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
	4702	+ "Done %s.\n", __func__);
	4703	+ }
	4704	+
	4705	+ return rval;
	4706	+}
	4707	+
	4708	+int
	4709	+qla81xx_fac_semaphore_access(scsi_qla_host_t *vha, int lock)
	4710	+{
	4711	+ int rval = QLA_SUCCESS;
	4712	+ mbx_cmd_t mc;
	4713	+ mbx_cmd_t *mcp = &mc;
	4714	+ struct qla_hw_data *ha = vha->hw;
	4715	+
	4716	+ if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
	4717	+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	4718	+ return rval;
	4719	+
	4720	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
	4721	+ "Entered %s.\n", __func__);
	4722	+
	4723	+ mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
	4724	+ mcp->mb[1] = (lock ? FAC_OPT_CMD_LOCK_SEMAPHORE :
	4725	+ FAC_OPT_CMD_UNLOCK_SEMAPHORE);
	4726	+ mcp->out_mb = MBX_1\|MBX_0;
	4727	+ mcp->in_mb = MBX_1\|MBX_0;
4533	4728	mcp->tov = MBX_TOV_SECONDS;
4534	4729	mcp->flags = 0;
4535	4730	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -4583,7 +4778,7 @@
4583	4778	mbx_cmd_t *mcp = &mc;
4584	4779	int i;
4585	4780	int len;
4586		- uint16_t *str;
	4781	+ __le16 *str;
4587	4782	struct qla_hw_data *ha = vha->hw;
4588	4783
4589	4784	if (!IS_P3P_TYPE(ha))
..	..	@@ -4592,14 +4787,14 @@
4592	4787	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
4593	4788	"Entered %s.\n", __func__);
4594	4789
4595		- str = (void *)version;
	4790	+ str = (__force __le16 *)version;
4596	4791	len = strlen(version);
4597	4792
4598	4793	mcp->mb[0] = MBC_SET_RNID_PARAMS;
4599	4794	mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
4600	4795	mcp->out_mb = MBX_1\|MBX_0;
4601	4796	for (i = 4; i < 16 && len; i++, str++, len -= 2) {
4602		- mcp->mb[i] = cpu_to_le16p(str);
	4797	+ mcp->mb[i] = le16_to_cpup(str);
4603	4798	mcp->out_mb \|= 1<<i;
4604	4799	}
4605	4800	for (; i < 16; i++) {
..	..	@@ -4717,8 +4912,73 @@
4717	4912	"Done %s.\n", __func__);
4718	4913	bp = (uint32_t *) buf;
4719	4914	for (i = 0; i < (bufsiz-4)/4; i++, bp++)
4720		- bp = le32_to_cpu(bp);
	4915	+ bp = le32_to_cpu((__force __le32)bp);
4721	4916	}
	4917	+
	4918	+ return rval;
	4919	+}
	4920	+
	4921	+#define PUREX_CMD_COUNT 2
	4922	+int
	4923	+qla25xx_set_els_cmds_supported(scsi_qla_host_t *vha)
	4924	+{
	4925	+ int rval;
	4926	+ mbx_cmd_t mc;
	4927	+ mbx_cmd_t *mcp = &mc;
	4928	+ uint8_t *els_cmd_map;
	4929	+ dma_addr_t els_cmd_map_dma;
	4930	+ uint8_t cmd_opcode[PUREX_CMD_COUNT];
	4931	+ uint8_t i, index, purex_bit;
	4932	+ struct qla_hw_data *ha = vha->hw;
	4933	+
	4934	+ if (!IS_QLA25XX(ha) && !IS_QLA2031(ha) &&
	4935	+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	4936	+ return QLA_SUCCESS;
	4937	+
	4938	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1197,
	4939	+ "Entered %s.\n", __func__);
	4940	+
	4941	+ els_cmd_map = dma_alloc_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
	4942	+ &els_cmd_map_dma, GFP_KERNEL);
	4943	+ if (!els_cmd_map) {
	4944	+ ql_log(ql_log_warn, vha, 0x7101,
	4945	+ "Failed to allocate RDP els command param.\n");
	4946	+ return QLA_MEMORY_ALLOC_FAILED;
	4947	+ }
	4948	+
	4949	+ /* List of Purex ELS */
	4950	+ cmd_opcode[0] = ELS_FPIN;
	4951	+ cmd_opcode[1] = ELS_RDP;
	4952	+
	4953	+ for (i = 0; i < PUREX_CMD_COUNT; i++) {
	4954	+ index = cmd_opcode[i] / 8;
	4955	+ purex_bit = cmd_opcode[i] % 8;
	4956	+ els_cmd_map[index] \|= 1 << purex_bit;
	4957	+ }
	4958	+
	4959	+ mcp->mb[0] = MBC_SET_RNID_PARAMS;
	4960	+ mcp->mb[1] = RNID_TYPE_ELS_CMD << 8;
	4961	+ mcp->mb[2] = MSW(LSD(els_cmd_map_dma));
	4962	+ mcp->mb[3] = LSW(LSD(els_cmd_map_dma));
	4963	+ mcp->mb[6] = MSW(MSD(els_cmd_map_dma));
	4964	+ mcp->mb[7] = LSW(MSD(els_cmd_map_dma));
	4965	+ mcp->out_mb = MBX_7\|MBX_6\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	4966	+ mcp->in_mb = MBX_1\|MBX_0;
	4967	+ mcp->tov = MBX_TOV_SECONDS;
	4968	+ mcp->flags = MBX_DMA_OUT;
	4969	+ mcp->buf_size = ELS_CMD_MAP_SIZE;
	4970	+ rval = qla2x00_mailbox_command(vha, mcp);
	4971	+
	4972	+ if (rval != QLA_SUCCESS) {
	4973	+ ql_dbg(ql_dbg_mbx, vha, 0x118d,
	4974	+ "Failed=%x (%x,%x).\n", rval, mcp->mb[0], mcp->mb[1]);
	4975	+ } else {
	4976	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118c,
	4977	+ "Done %s.\n", __func__);
	4978	+ }
	4979	+
	4980	+ dma_free_coherent(&ha->pdev->dev, ELS_CMD_MAP_SIZE,
	4981	+ els_cmd_map, els_cmd_map_dma);
4722	4982
4723	4983	return rval;
4724	4984	}
..	..	@@ -4776,8 +5036,8 @@
4776	5036
4777	5037	mcp->mb[0] = MBC_READ_SFP;
4778	5038	mcp->mb[1] = dev;
4779		- mcp->mb[2] = MSW(sfp_dma);
4780		- mcp->mb[3] = LSW(sfp_dma);
	5039	+ mcp->mb[2] = MSW(LSD(sfp_dma));
	5040	+ mcp->mb[3] = LSW(LSD(sfp_dma));
4781	5041	mcp->mb[6] = MSW(MSD(sfp_dma));
4782	5042	mcp->mb[7] = LSW(MSD(sfp_dma));
4783	5043	mcp->mb[8] = len;
..	..	@@ -4795,10 +5055,10 @@
4795	5055	if (rval != QLA_SUCCESS) {
4796	5056	ql_dbg(ql_dbg_mbx, vha, 0x10e9,
4797	5057	"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4798		- if (mcp->mb[0] == MBS_COMMAND_ERROR &&
4799		- mcp->mb[1] == 0x22)
	5058	+ if (mcp->mb[0] == MBS_COMMAND_ERROR && mcp->mb[1] == 0x22) {
4800	5059	/* sfp is not there */
4801	5060	rval = QLA_INTERFACE_ERROR;
	5061	+ }
4802	5062	} else {
4803	5063	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
4804	5064	"Done %s.\n", __func__);
..	..	@@ -4830,8 +5090,8 @@
4830	5090
4831	5091	mcp->mb[0] = MBC_WRITE_SFP;
4832	5092	mcp->mb[1] = dev;
4833		- mcp->mb[2] = MSW(sfp_dma);
4834		- mcp->mb[3] = LSW(sfp_dma);
	5093	+ mcp->mb[2] = MSW(LSD(sfp_dma));
	5094	+ mcp->mb[3] = LSW(LSD(sfp_dma));
4835	5095	mcp->mb[6] = MSW(MSD(sfp_dma));
4836	5096	mcp->mb[7] = LSW(MSD(sfp_dma));
4837	5097	mcp->mb[8] = len;
..	..	@@ -4952,7 +5212,7 @@
4952	5212	mcp->mb[8] = MSW(risc_addr);
4953	5213	mcp->out_mb = MBX_8\|MBX_1\|MBX_0;
4954	5214	mcp->in_mb = MBX_3\|MBX_2\|MBX_0;
4955		- mcp->tov = 30;
	5215	+ mcp->tov = MBX_TOV_SECONDS;
4956	5216	mcp->flags = 0;
4957	5217	rval = qla2x00_mailbox_command(vha, mcp);
4958	5218	if (rval != QLA_SUCCESS) {
..	..	@@ -5066,10 +5326,11 @@
5066	5326	mcp->out_mb \|= MBX_2;
5067	5327
5068	5328	mcp->in_mb = MBX_0;
5069		- if (IS_QLA24XX_TYPE(ha) \|\| IS_QLA25XX(ha) \|\|
5070		- IS_CNA_CAPABLE(ha) \|\| IS_QLA2031(ha))
	5329	+ if (IS_CNA_CAPABLE(ha) \|\| IS_QLA24XX_TYPE(ha) \|\| IS_QLA25XX(ha) \|\|
	5330	+ IS_QLA2031(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
5071	5331	mcp->in_mb \|= MBX_1;
5072		- if (IS_CNA_CAPABLE(ha) \|\| IS_QLA2031(ha))
	5332	+ if (IS_CNA_CAPABLE(ha) \|\| IS_QLA2031(ha) \|\| IS_QLA27XX(ha) \|\|
	5333	+ IS_QLA28XX(ha))
5073	5334	mcp->in_mb \|= MBX_3;
5074	5335
5075	5336	mcp->tov = MBX_TOV_SECONDS;
..	..	@@ -5138,13 +5399,14 @@
5138	5399	mcp->mb[3] = MSW(data);
5139	5400	mcp->mb[8] = MSW(risc_addr);
5140	5401	mcp->out_mb = MBX_8\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
5141		- mcp->in_mb = MBX_0;
5142		- mcp->tov = 30;
	5402	+ mcp->in_mb = MBX_1\|MBX_0;
	5403	+ mcp->tov = MBX_TOV_SECONDS;
5143	5404	mcp->flags = 0;
5144	5405	rval = qla2x00_mailbox_command(vha, mcp);
5145	5406	if (rval != QLA_SUCCESS) {
5146	5407	ql_dbg(ql_dbg_mbx, vha, 0x1101,
5147		- "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	5408	+ "Failed=%x mb[0]=%x mb[1]=%x.\n",
	5409	+ rval, mcp->mb[0], mcp->mb[1]);
5148	5410	} else {
5149	5411	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
5150	5412	"Done %s.\n", __func__);
..	..	@@ -5170,18 +5432,18 @@
5170	5432	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
5171	5433
5172	5434	/* Write the MBC data to the registers */
5173		- WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
5174		- WRT_REG_WORD(&reg->mailbox1, mb[0]);
5175		- WRT_REG_WORD(&reg->mailbox2, mb[1]);
5176		- WRT_REG_WORD(&reg->mailbox3, mb[2]);
5177		- WRT_REG_WORD(&reg->mailbox4, mb[3]);
	5435	+ wrt_reg_word(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
	5436	+ wrt_reg_word(&reg->mailbox1, mb[0]);
	5437	+ wrt_reg_word(&reg->mailbox2, mb[1]);
	5438	+ wrt_reg_word(&reg->mailbox3, mb[2]);
	5439	+ wrt_reg_word(&reg->mailbox4, mb[3]);
5178	5440
5179		- WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
	5441	+ wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);
5180	5442
5181	5443	/* Poll for MBC interrupt */
5182	5444	for (timer = 6000000; timer; timer--) {
5183	5445	/* Check for pending interrupts. */
5184		- stat = RD_REG_DWORD(&reg->host_status);
	5446	+ stat = rd_reg_dword(&reg->host_status);
5185	5447	if (stat & HSRX_RISC_INT) {
5186	5448	stat &= 0xff;
5187	5449
..	..	@@ -5189,10 +5451,10 @@
5189	5451	stat == 0x10 \|\| stat == 0x11) {
5190	5452	set_bit(MBX_INTERRUPT,
5191	5453	&ha->mbx_cmd_flags);
5192		- mb0 = RD_REG_WORD(&reg->mailbox0);
5193		- WRT_REG_DWORD(&reg->hccr,
	5454	+ mb0 = rd_reg_word(&reg->mailbox0);
	5455	+ wrt_reg_dword(&reg->hccr,
5194	5456	HCCRX_CLR_RISC_INT);
5195		- RD_REG_DWORD(&reg->hccr);
	5457	+ rd_reg_dword(&reg->hccr);
5196	5458	break;
5197	5459	}
5198	5460	}
..	..	@@ -5215,6 +5477,66 @@
5215	5477	return rval;
5216	5478	}
5217	5479
	5480	+/* Set the specified data rate */
	5481	+int
	5482	+qla2x00_set_data_rate(scsi_qla_host_t *vha, uint16_t mode)
	5483	+{
	5484	+ int rval;
	5485	+ mbx_cmd_t mc;
	5486	+ mbx_cmd_t *mcp = &mc;
	5487	+ struct qla_hw_data *ha = vha->hw;
	5488	+ uint16_t val;
	5489	+
	5490	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
	5491	+ "Entered %s speed:0x%x mode:0x%x.\n", __func__, ha->set_data_rate,
	5492	+ mode);
	5493	+
	5494	+ if (!IS_FWI2_CAPABLE(ha))
	5495	+ return QLA_FUNCTION_FAILED;
	5496	+
	5497	+ memset(mcp, 0, sizeof(*mcp));
	5498	+ switch (ha->set_data_rate) {
	5499	+ case PORT_SPEED_AUTO:
	5500	+ case PORT_SPEED_4GB:
	5501	+ case PORT_SPEED_8GB:
	5502	+ case PORT_SPEED_16GB:
	5503	+ case PORT_SPEED_32GB:
	5504	+ val = ha->set_data_rate;
	5505	+ break;
	5506	+ default:
	5507	+ ql_log(ql_log_warn, vha, 0x1199,
	5508	+ "Unrecognized speed setting:%d. Setting Autoneg\n",
	5509	+ ha->set_data_rate);
	5510	+ val = ha->set_data_rate = PORT_SPEED_AUTO;
	5511	+ break;
	5512	+ }
	5513	+
	5514	+ mcp->mb[0] = MBC_DATA_RATE;
	5515	+ mcp->mb[1] = mode;
	5516	+ mcp->mb[2] = val;
	5517	+
	5518	+ mcp->out_mb = MBX_2\|MBX_1\|MBX_0;
	5519	+ mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
	5520	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	5521	+ mcp->in_mb \|= MBX_4\|MBX_3;
	5522	+ mcp->tov = MBX_TOV_SECONDS;
	5523	+ mcp->flags = 0;
	5524	+ rval = qla2x00_mailbox_command(vha, mcp);
	5525	+ if (rval != QLA_SUCCESS) {
	5526	+ ql_dbg(ql_dbg_mbx, vha, 0x1107,
	5527	+ "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	5528	+ } else {
	5529	+ if (mcp->mb[1] != 0x7)
	5530	+ ql_dbg(ql_dbg_mbx, vha, 0x1179,
	5531	+ "Speed set:0x%x\n", mcp->mb[1]);
	5532	+
	5533	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
	5534	+ "Done %s.\n", __func__);
	5535	+ }
	5536	+
	5537	+ return rval;
	5538	+}
	5539	+
5218	5540	int
5219	5541	qla2x00_get_data_rate(scsi_qla_host_t *vha)
5220	5542	{
..	..	@@ -5230,11 +5552,11 @@
5230	5552	return QLA_FUNCTION_FAILED;
5231	5553
5232	5554	mcp->mb[0] = MBC_DATA_RATE;
5233		- mcp->mb[1] = 0;
	5555	+ mcp->mb[1] = QLA_GET_DATA_RATE;
5234	5556	mcp->out_mb = MBX_1\|MBX_0;
5235	5557	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
5236		- if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
5237		- mcp->in_mb \|= MBX_3;
	5558	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha))
	5559	+ mcp->in_mb \|= MBX_4\|MBX_3;
5238	5560	mcp->tov = MBX_TOV_SECONDS;
5239	5561	mcp->flags = 0;
5240	5562	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5242,6 +5564,15 @@
5242	5564	ql_dbg(ql_dbg_mbx, vha, 0x1107,
5243	5565	"Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
5244	5566	} else {
	5567	+ if (mcp->mb[1] != 0x7)
	5568	+ ha->link_data_rate = mcp->mb[1];
	5569	+
	5570	+ if (IS_QLA83XX(ha) \|\| IS_QLA27XX(ha) \|\| IS_QLA28XX(ha)) {
	5571	+ if (mcp->mb[4] & BIT_0)
	5572	+ ql_log(ql_log_info, vha, 0x11a2,
	5573	+ "FEC=enabled (data rate).\n");
	5574	+ }
	5575	+
5245	5576	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
5246	5577	"Done %s.\n", __func__);
5247	5578	if (mcp->mb[1] != 0x7)
..	..	@@ -5263,7 +5594,7 @@
5263	5594	"Entered %s.\n", __func__);
5264	5595
5265	5596	if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
5266		- !IS_QLA27XX(ha))
	5597	+ !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
5267	5598	return QLA_FUNCTION_FAILED;
5268	5599	mcp->mb[0] = MBC_GET_PORT_CONFIG;
5269	5600	mcp->out_mb = MBX_0;
..	..	@@ -5341,7 +5672,7 @@
5341	5672	mcp->mb[9] = vha->vp_idx;
5342	5673	mcp->out_mb = MBX_9\|MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
5343	5674	mcp->in_mb = MBX_4\|MBX_3\|MBX_1\|MBX_0;
5344		- mcp->tov = 30;
	5675	+ mcp->tov = MBX_TOV_SECONDS;
5345	5676	mcp->flags = 0;
5346	5677	rval = qla2x00_mailbox_command(vha, mcp);
5347	5678	if (mb != NULL) {
..	..	@@ -5428,7 +5759,7 @@
5428	5759
5429	5760	mcp->out_mb = MBX_1\|MBX_0;
5430	5761	mcp->in_mb = MBX_0;
5431		- mcp->tov = 30;
	5762	+ mcp->tov = MBX_TOV_SECONDS;
5432	5763	mcp->flags = 0;
5433	5764
5434	5765	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5463,7 +5794,7 @@
5463	5794
5464	5795	mcp->out_mb = MBX_1\|MBX_0;
5465	5796	mcp->in_mb = MBX_0;
5466		- mcp->tov = 30;
	5797	+ mcp->tov = MBX_TOV_SECONDS;
5467	5798	mcp->flags = 0;
5468	5799
5469	5800	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5579,6 +5910,7 @@
5579	5910	mbx_cmd_t *mcp = &mc;
5580	5911	int rval = QLA_FUNCTION_FAILED;
5581	5912	int offset = 0, size = MINIDUMP_SIZE_36K;
	5913	+
5582	5914	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
5583	5915	"Entered %s.\n", __func__);
5584	5916
..	..	@@ -5654,7 +5986,7 @@
5654	5986	if (IS_QLA8031(ha))
5655	5987	mcp->out_mb \|= MBX_6\|MBX_5\|MBX_4\|MBX_3;
5656	5988	mcp->in_mb = MBX_0;
5657		- mcp->tov = 30;
	5989	+ mcp->tov = MBX_TOV_SECONDS;
5658	5990	mcp->flags = 0;
5659	5991
5660	5992	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5690,7 +6022,7 @@
5690	6022	mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
5691	6023	if (IS_QLA8031(ha))
5692	6024	mcp->in_mb \|= MBX_6\|MBX_5\|MBX_4\|MBX_3;
5693		- mcp->tov = 30;
	6025	+ mcp->tov = MBX_TOV_SECONDS;
5694	6026	mcp->flags = 0;
5695	6027
5696	6028	rval = qla2x00_mailbox_command(vha, mcp);
..	..	@@ -5759,7 +6091,7 @@
5759	6091	mbx_cmd_t mc;
5760	6092	mbx_cmd_t *mcp = &mc;
5761	6093
5762		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
	6094	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
5763	6095	return QLA_FUNCTION_FAILED;
5764	6096
5765	6097	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
..	..	@@ -5834,7 +6166,7 @@
5834	6166	struct qla_hw_data *ha = vha->hw;
5835	6167	unsigned long retry_max_time = jiffies + (2 * HZ);
5836	6168
5837		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
	6169	+ if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
5838	6170	return QLA_FUNCTION_FAILED;
5839	6171
5840	6172	ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
..	..	@@ -5884,7 +6216,7 @@
5884	6216	mbx_cmd_t *mcp = &mc;
5885	6217	struct qla_hw_data *ha = vha->hw;
5886	6218
5887		- if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
	6219	+ if (!IS_QLA83XX(ha))
5888	6220	return QLA_FUNCTION_FAILED;
5889	6221
5890	6222	ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
..	..	@@ -5900,7 +6232,7 @@
5900	6232	ql_dbg(ql_dbg_mbx, vha, 0x1144,
5901	6233	"Failed=%x mb[0]=%x mb[1]=%x.\n",
5902	6234	rval, mcp->mb[0], mcp->mb[1]);
5903		- ha->isp_ops->fw_dump(vha, 0);
	6235	+ qla2xxx_dump_fw(vha);
5904	6236	} else {
5905	6237	ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
5906	6238	}
..	..	@@ -5945,7 +6277,7 @@
5945	6277	"Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
5946	6278	rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
5947	6279	mcp->mb[4]);
5948		- ha->isp_ops->fw_dump(vha, 0);
	6280	+ qla2xxx_dump_fw(vha);
5949	6281	} else {
5950	6282	if (subcode & BIT_5)
5951	6283	*sector_size = mcp->mb[1];
..	..	@@ -6017,7 +6349,8 @@
6017	6349	mbx_cmd_t *mcp = &mc;
6018	6350	dma_addr_t dd_dma;
6019	6351
6020		- if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
	6352	+ if (!IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw) &&
	6353	+ !IS_QLA28XX(vha->hw))
6021	6354	return QLA_FUNCTION_FAILED;
6022	6355
6023	6356	ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x119f,
..	..	@@ -6059,10 +6392,8 @@
6059	6392	return rval;
6060	6393	}
6061	6394
6062		-static void qla2x00_async_mb_sp_done(void *s, int res)
	6395	+static void qla2x00_async_mb_sp_done(srb_t *sp, int res)
6063	6396	{
6064		- struct srb *sp = s;
6065		-
6066	6397	sp->u.iocb_cmd.u.mbx.rc = res;
6067	6398
6068	6399	complete(&sp->u.iocb_cmd.u.mbx.comp);
..	..	@@ -6160,13 +6491,13 @@
6160	6491
6161	6492	memset(&mc, 0, sizeof(mc));
6162	6493	mc.mb[0] = MBC_GET_PORT_DATABASE;
6163		- mc.mb[1] = cpu_to_le16(fcport->loop_id);
	6494	+ mc.mb[1] = fcport->loop_id;
6164	6495	mc.mb[2] = MSW(pd_dma);
6165	6496	mc.mb[3] = LSW(pd_dma);
6166	6497	mc.mb[6] = MSW(MSD(pd_dma));
6167	6498	mc.mb[7] = LSW(MSD(pd_dma));
6168		- mc.mb[9] = cpu_to_le16(vha->vp_idx);
6169		- mc.mb[10] = cpu_to_le16((uint16_t)opt);
	6499	+ mc.mb[9] = vha->vp_idx;
	6500	+ mc.mb[10] = opt;
6170	6501
6171	6502	rval = qla24xx_send_mb_cmd(vha, &mc);
6172	6503	if (rval != QLA_SUCCESS) {
..	..	@@ -6194,7 +6525,7 @@
6194	6525	uint64_t zero = 0;
6195	6526	u8 current_login_state, last_login_state;
6196	6527
6197		- if (fcport->fc4f_nvme) {
	6528	+ if (NVME_TARGET(vha->hw, fcport)) {
6198	6529	current_login_state = pd->current_login_state >> 4;
6199	6530	last_login_state = pd->last_login_state >> 4;
6200	6531	} else {
..	..	@@ -6229,10 +6560,14 @@
6229	6560	fcport->d_id.b.al_pa = pd->port_id[2];
6230	6561	fcport->d_id.b.rsvd_1 = 0;
6231	6562
6232		- if (fcport->fc4f_nvme) {
6233		- fcport->nvme_prli_service_param =
6234		- pd->prli_nvme_svc_param_word_3;
	6563	+ if (NVME_TARGET(vha->hw, fcport)) {
6235	6564	fcport->port_type = FCT_NVME;
	6565	+ if ((pd->prli_svc_param_word_3[0] & BIT_5) == 0)
	6566	+ fcport->port_type \|= FCT_NVME_INITIATOR;
	6567	+ if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
	6568	+ fcport->port_type \|= FCT_NVME_TARGET;
	6569	+ if ((pd->prli_svc_param_word_3[0] & BIT_3) == 0)
	6570	+ fcport->port_type \|= FCT_NVME_DISCOVERY;
6236	6571	} else {
6237	6572	/* If not target must be initiator or unknown type. */
6238	6573	if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
..	..	@@ -6273,7 +6608,7 @@
6273	6608	mc.mb[6] = MSW(MSD(id_list_dma));
6274	6609	mc.mb[7] = LSW(MSD(id_list_dma));
6275	6610	mc.mb[8] = 0;
6276		- mc.mb[9] = cpu_to_le16(vha->vp_idx);
	6611	+ mc.mb[9] = vha->vp_idx;
6277	6612
6278	6613	rval = qla24xx_send_mb_cmd(vha, &mc);
6279	6614	if (rval != QLA_SUCCESS) {
..	..	@@ -6299,8 +6634,8 @@
6299	6634
6300	6635	memset(mcp->mb, 0 , sizeof(mcp->mb));
6301	6636	mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6302		- mcp->mb[1] = cpu_to_le16(1);
6303		- mcp->mb[2] = cpu_to_le16(value);
	6637	+ mcp->mb[1] = 1;
	6638	+ mcp->mb[2] = value;
6304	6639	mcp->out_mb = MBX_2 \| MBX_1 \| MBX_0;
6305	6640	mcp->in_mb = MBX_2 \| MBX_0;
6306	6641	mcp->tov = MBX_TOV_SECONDS;
..	..	@@ -6325,7 +6660,7 @@
6325	6660
6326	6661	memset(mcp->mb, 0, sizeof(mcp->mb));
6327	6662	mcp->mb[0] = MBC_GET_SET_ZIO_THRESHOLD;
6328		- mcp->mb[1] = cpu_to_le16(0);
	6663	+ mcp->mb[1] = 0;
6329	6664	mcp->out_mb = MBX_1 \| MBX_0;
6330	6665	mcp->in_mb = MBX_2 \| MBX_0;
6331	6666	mcp->tov = MBX_TOV_SECONDS;
..	..	@@ -6421,3 +6756,158 @@
6421	6756	done:
6422	6757	return rval;
6423	6758	}
	6759	+
	6760	+int qla28xx_secure_flash_update(scsi_qla_host_t *vha, uint16_t opts,
	6761	+ uint16_t region, uint32_t len, dma_addr_t sfub_dma_addr,
	6762	+ uint32_t sfub_len)
	6763	+{
	6764	+ int rval;
	6765	+ mbx_cmd_t mc;
	6766	+ mbx_cmd_t *mcp = &mc;
	6767	+
	6768	+ mcp->mb[0] = MBC_SECURE_FLASH_UPDATE;
	6769	+ mcp->mb[1] = opts;
	6770	+ mcp->mb[2] = region;
	6771	+ mcp->mb[3] = MSW(len);
	6772	+ mcp->mb[4] = LSW(len);
	6773	+ mcp->mb[5] = MSW(sfub_dma_addr);
	6774	+ mcp->mb[6] = LSW(sfub_dma_addr);
	6775	+ mcp->mb[7] = MSW(MSD(sfub_dma_addr));
	6776	+ mcp->mb[8] = LSW(MSD(sfub_dma_addr));
	6777	+ mcp->mb[9] = sfub_len;
	6778	+ mcp->out_mb =
	6779	+ MBX_9\|MBX_8\|MBX_7\|MBX_6\|MBX_5\|MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	6780	+ mcp->in_mb = MBX_2\|MBX_1\|MBX_0;
	6781	+ mcp->tov = MBX_TOV_SECONDS;
	6782	+ mcp->flags = 0;
	6783	+ rval = qla2x00_mailbox_command(vha, mcp);
	6784	+
	6785	+ if (rval != QLA_SUCCESS) {
	6786	+ ql_dbg(ql_dbg_mbx, vha, 0xffff, "%s(%ld): failed rval 0x%x, %x %x %x",
	6787	+ __func__, vha->host_no, rval, mcp->mb[0], mcp->mb[1],
	6788	+ mcp->mb[2]);
	6789	+ }
	6790	+
	6791	+ return rval;
	6792	+}
	6793	+
	6794	+int qla2xxx_write_remote_register(scsi_qla_host_t *vha, uint32_t addr,
	6795	+ uint32_t data)
	6796	+{
	6797	+ int rval;
	6798	+ mbx_cmd_t mc;
	6799	+ mbx_cmd_t *mcp = &mc;
	6800	+
	6801	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
	6802	+ "Entered %s.\n", __func__);
	6803	+
	6804	+ mcp->mb[0] = MBC_WRITE_REMOTE_REG;
	6805	+ mcp->mb[1] = LSW(addr);
	6806	+ mcp->mb[2] = MSW(addr);
	6807	+ mcp->mb[3] = LSW(data);
	6808	+ mcp->mb[4] = MSW(data);
	6809	+ mcp->out_mb = MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	6810	+ mcp->in_mb = MBX_1\|MBX_0;
	6811	+ mcp->tov = MBX_TOV_SECONDS;
	6812	+ mcp->flags = 0;
	6813	+ rval = qla2x00_mailbox_command(vha, mcp);
	6814	+
	6815	+ if (rval != QLA_SUCCESS) {
	6816	+ ql_dbg(ql_dbg_mbx, vha, 0x10e9,
	6817	+ "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	6818	+ } else {
	6819	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
	6820	+ "Done %s.\n", __func__);
	6821	+ }
	6822	+
	6823	+ return rval;
	6824	+}
	6825	+
	6826	+int qla2xxx_read_remote_register(scsi_qla_host_t *vha, uint32_t addr,
	6827	+ uint32_t *data)
	6828	+{
	6829	+ int rval;
	6830	+ mbx_cmd_t mc;
	6831	+ mbx_cmd_t *mcp = &mc;
	6832	+
	6833	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
	6834	+ "Entered %s.\n", __func__);
	6835	+
	6836	+ mcp->mb[0] = MBC_READ_REMOTE_REG;
	6837	+ mcp->mb[1] = LSW(addr);
	6838	+ mcp->mb[2] = MSW(addr);
	6839	+ mcp->out_mb = MBX_2\|MBX_1\|MBX_0;
	6840	+ mcp->in_mb = MBX_4\|MBX_3\|MBX_2\|MBX_1\|MBX_0;
	6841	+ mcp->tov = MBX_TOV_SECONDS;
	6842	+ mcp->flags = 0;
	6843	+ rval = qla2x00_mailbox_command(vha, mcp);
	6844	+
	6845	+ *data = (uint32_t)((((uint32_t)mcp->mb[4]) << 16) \| mcp->mb[3]);
	6846	+
	6847	+ if (rval != QLA_SUCCESS) {
	6848	+ ql_dbg(ql_dbg_mbx, vha, 0x10e9,
	6849	+ "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
	6850	+ } else {
	6851	+ ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
	6852	+ "Done %s.\n", __func__);
	6853	+ }
	6854	+
	6855	+ return rval;
	6856	+}
	6857	+
	6858	+int
	6859	+ql26xx_led_config(scsi_qla_host_t vha, uint16_t options, uint16_t led)
	6860	+{
	6861	+ struct qla_hw_data *ha = vha->hw;
	6862	+ mbx_cmd_t mc;
	6863	+ mbx_cmd_t *mcp = &mc;
	6864	+ int rval;
	6865	+
	6866	+ if (!IS_QLA2031(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
	6867	+ return QLA_FUNCTION_FAILED;
	6868	+
	6869	+ ql_dbg(ql_dbg_mbx, vha, 0x7070, "Entered %s (options=%x).\n",
	6870	+ __func__, options);
	6871	+
	6872	+ mcp->mb[0] = MBC_SET_GET_FC_LED_CONFIG;
	6873	+ mcp->mb[1] = options;
	6874	+ mcp->out_mb = MBX_1\|MBX_0;
	6875	+ mcp->in_mb = MBX_1\|MBX_0;
	6876	+ if (options & BIT_0) {
	6877	+ if (options & BIT_1) {
	6878	+ mcp->mb[2] = led[2];
	6879	+ mcp->out_mb \|= MBX_2;
	6880	+ }
	6881	+ if (options & BIT_2) {
	6882	+ mcp->mb[3] = led[0];
	6883	+ mcp->out_mb \|= MBX_3;
	6884	+ }
	6885	+ if (options & BIT_3) {
	6886	+ mcp->mb[4] = led[1];
	6887	+ mcp->out_mb \|= MBX_4;
	6888	+ }
	6889	+ } else {
	6890	+ mcp->in_mb \|= MBX_4\|MBX_3\|MBX_2;
	6891	+ }
	6892	+ mcp->tov = MBX_TOV_SECONDS;
	6893	+ mcp->flags = 0;
	6894	+ rval = qla2x00_mailbox_command(vha, mcp);
	6895	+ if (rval) {
	6896	+ ql_dbg(ql_dbg_mbx, vha, 0x7071, "Failed %s %x (mb=%x,%x)\n",
	6897	+ __func__, rval, mcp->mb[0], mcp->mb[1]);
	6898	+ return rval;
	6899	+ }
	6900	+
	6901	+ if (options & BIT_0) {
	6902	+ ha->beacon_blink_led = 0;
	6903	+ ql_dbg(ql_dbg_mbx, vha, 0x7072, "Done %s\n", __func__);
	6904	+ } else {
	6905	+ led[2] = mcp->mb[2];
	6906	+ led[0] = mcp->mb[3];
	6907	+ led[1] = mcp->mb[4];
	6908	+ ql_dbg(ql_dbg_mbx, vha, 0x7073, "Done %s (led=%x,%x,%x)\n",
	6909	+ __func__, led[0], led[1], led[2]);
	6910	+ }
	6911	+
	6912	+ return rval;
	6913	+}