~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,14 +1,15 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* QLogic Fibre Channel HBA Driver
3	4	* Copyright (c) 2003-2014 QLogic Corporation
4		- *
5		- * See LICENSE.qla2xxx for copyright and licensing details.
6	5	*/
7	6	#ifndef __QLA_FW_H
8	7	#define __QLA_FW_H
9	8
10	9	#include <linux/nvme.h>
11	10	#include <linux/nvme-fc.h>
	11	+
	12	+#include "qla_dsd.h"
12	13
13	14	#define MBS_CHECKSUM_ERROR 0x4010
14	15	#define MBS_INVALID_PRODUCT_KEY 0x4020
..	..	@@ -29,6 +30,9 @@
29	30	#define PDO_FORCE_ADISC BIT_1
30	31	#define PDO_FORCE_PLOGI BIT_0
31	32
	33	+struct buffer_credit_24xx {
	34	+ u32 parameter[28];
	35	+};
32	36
33	37	#define PORT_DATABASE_24XX_SIZE 64
34	38	struct port_database_24xx {
..	..	@@ -129,28 +133,28 @@
129	133	struct nvram_24xx {
130	134	/* NVRAM header. */
131	135	uint8_t id[4];
132		- uint16_t nvram_version;
	136	+ __le16 nvram_version;
133	137	uint16_t reserved_0;
134	138
135	139	/* Firmware Initialization Control Block. */
136		- uint16_t version;
	140	+ __le16 version;
137	141	uint16_t reserved_1;
138		- __le16 frame_payload_size;
139		- uint16_t execution_throttle;
140		- uint16_t exchange_count;
141		- uint16_t hard_address;
	142	+ __le16 frame_payload_size;
	143	+ __le16 execution_throttle;
	144	+ __le16 exchange_count;
	145	+ __le16 hard_address;
142	146
143	147	uint8_t port_name[WWN_SIZE];
144	148	uint8_t node_name[WWN_SIZE];
145	149
146		- uint16_t login_retry_count;
147		- uint16_t link_down_on_nos;
148		- uint16_t interrupt_delay_timer;
149		- uint16_t login_timeout;
	150	+ __le16 login_retry_count;
	151	+ __le16 link_down_on_nos;
	152	+ __le16 interrupt_delay_timer;
	153	+ __le16 login_timeout;
150	154
151		- uint32_t firmware_options_1;
152		- uint32_t firmware_options_2;
153		- uint32_t firmware_options_3;
	155	+ __le32 firmware_options_1;
	156	+ __le32 firmware_options_2;
	157	+ __le32 firmware_options_3;
154	158
155	159	/* Offset 56. */
156	160
..	..	@@ -173,7 +177,7 @@
173	177	* BIT 11-13 = Output Emphasis 4G
174	178	* BIT 14-15 = Reserved
175	179	*/
176		- uint16_t seriallink_options[4];
	180	+ __le16 seriallink_options[4];
177	181
178	182	uint16_t reserved_2[16];
179	183
..	..	@@ -213,25 +217,25 @@
213	217	*
214	218	* BIT 16-31 =
215	219	*/
216		- uint32_t host_p;
	220	+ __le32 host_p;
217	221
218	222	uint8_t alternate_port_name[WWN_SIZE];
219	223	uint8_t alternate_node_name[WWN_SIZE];
220	224
221	225	uint8_t boot_port_name[WWN_SIZE];
222		- uint16_t boot_lun_number;
	226	+ __le16 boot_lun_number;
223	227	uint16_t reserved_8;
224	228
225	229	uint8_t alt1_boot_port_name[WWN_SIZE];
226		- uint16_t alt1_boot_lun_number;
	230	+ __le16 alt1_boot_lun_number;
227	231	uint16_t reserved_9;
228	232
229	233	uint8_t alt2_boot_port_name[WWN_SIZE];
230		- uint16_t alt2_boot_lun_number;
	234	+ __le16 alt2_boot_lun_number;
231	235	uint16_t reserved_10;
232	236
233	237	uint8_t alt3_boot_port_name[WWN_SIZE];
234		- uint16_t alt3_boot_lun_number;
	238	+ __le16 alt3_boot_lun_number;
235	239	uint16_t reserved_11;
236	240
237	241	/*
..	..	@@ -244,23 +248,23 @@
244	248	* BIT 6 = Reserved
245	249	* BIT 7-31 =
246	250	*/
247		- uint32_t efi_parameters;
	251	+ __le32 efi_parameters;
248	252
249	253	uint8_t reset_delay;
250	254	uint8_t reserved_12;
251	255	uint16_t reserved_13;
252	256
253		- uint16_t boot_id_number;
	257	+ __le16 boot_id_number;
254	258	uint16_t reserved_14;
255	259
256		- uint16_t max_luns_per_target;
	260	+ __le16 max_luns_per_target;
257	261	uint16_t reserved_15;
258	262
259		- uint16_t port_down_retry_count;
260		- uint16_t link_down_timeout;
	263	+ __le16 port_down_retry_count;
	264	+ __le16 link_down_timeout;
261	265
262	266	/* FCode parameters. */
263		- uint16_t fcode_parameter;
	267	+ __le16 fcode_parameter;
264	268
265	269	uint16_t reserved_16[3];
266	270
..	..	@@ -270,13 +274,13 @@
270	274	uint8_t prev_drv_ver_minor;
271	275	uint8_t prev_drv_ver_subminor;
272	276
273		- uint16_t prev_bios_ver_major;
274		- uint16_t prev_bios_ver_minor;
	277	+ __le16 prev_bios_ver_major;
	278	+ __le16 prev_bios_ver_minor;
275	279
276		- uint16_t prev_efi_ver_major;
277		- uint16_t prev_efi_ver_minor;
	280	+ __le16 prev_efi_ver_major;
	281	+ __le16 prev_efi_ver_minor;
278	282
279		- uint16_t prev_fw_ver_major;
	283	+ __le16 prev_fw_ver_major;
280	284	uint8_t prev_fw_ver_minor;
281	285	uint8_t prev_fw_ver_subminor;
282	286
..	..	@@ -304,7 +308,7 @@
304	308	uint16_t subsystem_vendor_id;
305	309	uint16_t subsystem_device_id;
306	310
307		- uint32_t checksum;
	311	+ __le32 checksum;
308	312	};
309	313
310	314	/*
..	..	@@ -313,46 +317,46 @@
313	317	*/
314	318	#define ICB_VERSION 1
315	319	struct init_cb_24xx {
316		- uint16_t version;
	320	+ __le16 version;
317	321	uint16_t reserved_1;
318	322
319		- uint16_t frame_payload_size;
320		- uint16_t execution_throttle;
321		- uint16_t exchange_count;
	323	+ __le16 frame_payload_size;
	324	+ __le16 execution_throttle;
	325	+ __le16 exchange_count;
322	326
323		- uint16_t hard_address;
	327	+ __le16 hard_address;
324	328
325	329	uint8_t port_name[WWN_SIZE]; /* Big endian. */
326	330	uint8_t node_name[WWN_SIZE]; /* Big endian. */
327	331
328		- uint16_t response_q_inpointer;
329		- uint16_t request_q_outpointer;
	332	+ __le16 response_q_inpointer;
	333	+ __le16 request_q_outpointer;
330	334
331		- uint16_t login_retry_count;
	335	+ __le16 login_retry_count;
332	336
333		- uint16_t prio_request_q_outpointer;
	337	+ __le16 prio_request_q_outpointer;
334	338
335		- uint16_t response_q_length;
336		- uint16_t request_q_length;
	339	+ __le16 response_q_length;
	340	+ __le16 request_q_length;
337	341
338		- uint16_t link_down_on_nos; /* Milliseconds. */
	342	+ __le16 link_down_on_nos; /* Milliseconds. */
339	343
340		- uint16_t prio_request_q_length;
	344	+ __le16 prio_request_q_length;
341	345
342		- uint32_t request_q_address[2];
343		- uint32_t response_q_address[2];
344		- uint32_t prio_request_q_address[2];
	346	+ __le64 request_q_address __packed;
	347	+ __le64 response_q_address __packed;
	348	+ __le64 prio_request_q_address __packed;
345	349
346		- uint16_t msix;
347		- uint16_t msix_atio;
	350	+ __le16 msix;
	351	+ __le16 msix_atio;
348	352	uint8_t reserved_2[4];
349	353
350		- uint16_t atio_q_inpointer;
351		- uint16_t atio_q_length;
352		- uint32_t atio_q_address[2];
	354	+ __le16 atio_q_inpointer;
	355	+ __le16 atio_q_length;
	356	+ __le64 atio_q_address __packed;
353	357
354		- uint16_t interrupt_delay_timer; /* 100us increments. */
355		- uint16_t login_timeout;
	358	+ __le16 interrupt_delay_timer; /* 100us increments. */
	359	+ __le16 login_timeout;
356	360
357	361	/*
358	362	* BIT 0 = Enable Hard Loop Id
..	..	@@ -373,7 +377,7 @@
373	377	* BIT 14 = Node Name Option
374	378	* BIT 15-31 = Reserved
375	379	*/
376		- uint32_t firmware_options_1;
	380	+ __le32 firmware_options_1;
377	381
378	382	/*
379	383	* BIT 0 = Operation Mode bit 0
..	..	@@ -394,7 +398,7 @@
394	398	* BIT 14 = Enable Target PRLI Control
395	399	* BIT 15-31 = Reserved
396	400	*/
397		- uint32_t firmware_options_2;
	401	+ __le32 firmware_options_2;
398	402
399	403	/*
400	404	* BIT 0 = Reserved
..	..	@@ -420,9 +424,9 @@
420	424	* BIT 30 = Enable request queue 0 out index shadowing
421	425	* BIT 31 = Reserved
422	426	*/
423		- uint32_t firmware_options_3;
424		- uint16_t qos;
425		- uint16_t rid;
	427	+ __le32 firmware_options_3;
	428	+ __le16 qos;
	429	+ __le16 rid;
426	430	uint8_t reserved_3[20];
427	431	};
428	432
..	..	@@ -438,33 +442,32 @@
438	442
439	443	uint32_t handle; /* System handle. */
440	444
441		- uint16_t nport_handle; /* N_PORT hanlde. */
	445	+ __le16 nport_handle; /* N_PORT handle. */
442	446
443		- uint16_t timeout; /* Commnad timeout. */
	447	+ __le16 timeout; /* Command timeout. */
444	448
445		- uint16_t wr_dseg_count; /* Write Data segment count. */
446		- uint16_t rd_dseg_count; /* Read Data segment count. */
	449	+ __le16 wr_dseg_count; /* Write Data segment count. */
	450	+ __le16 rd_dseg_count; /* Read Data segment count. */
447	451
448	452	struct scsi_lun lun; /* FCP LUN (BE). */
449	453
450		- uint16_t control_flags; /* Control flags. */
	454	+ __le16 control_flags; /* Control flags. */
451	455	#define BD_WRAP_BACK BIT_3
452	456	#define BD_READ_DATA BIT_1
453	457	#define BD_WRITE_DATA BIT_0
454	458
455		- uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
456		- uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
	459	+ __le16 fcp_cmnd_dseg_len; /* Data segment length. */
	460	+ __le64 fcp_cmnd_dseg_address __packed;/* Data segment address. */
457	461
458	462	uint16_t reserved[2]; /* Reserved */
459	463
460		- uint32_t rd_byte_count; /* Total Byte count Read. */
461		- uint32_t wr_byte_count; /* Total Byte count write. */
	464	+ __le32 rd_byte_count; /* Total Byte count Read. */
	465	+ __le32 wr_byte_count; /* Total Byte count write. */
462	466
463	467	uint8_t port_id[3]; /* PortID of destination port.*/
464	468	uint8_t vp_index;
465	469
466		- uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
467		- uint16_t fcp_data_dseg_len; /* Data segment length. */
	470	+ struct dsd64 fcp_dsd;
468	471	};
469	472
470	473	#define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
..	..	@@ -476,33 +479,33 @@
476	479
477	480	uint32_t handle; /* System handle. */
478	481
479		- uint16_t nport_handle; /* N_PORT handle. */
480		- uint16_t timeout; /* Command timeout. */
	482	+ __le16 nport_handle; /* N_PORT handle. */
	483	+ __le16 timeout; /* Command timeout. */
481	484
482		- uint16_t dseg_count; /* Data segment count. */
	485	+ __le16 dseg_count; /* Data segment count. */
483	486
484		- uint16_t fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
	487	+ __le16 fcp_rsp_dsd_len; /* FCP_RSP DSD length. */
485	488
486	489	struct scsi_lun lun; /* FCP LUN (BE). */
487	490
488		- uint16_t control_flags; /* Control flags. */
	491	+ __le16 control_flags; /* Control flags. */
489	492	#define CF_DIF_SEG_DESCR_ENABLE BIT_3
490	493	#define CF_DATA_SEG_DESCR_ENABLE BIT_2
491	494	#define CF_READ_DATA BIT_1
492	495	#define CF_WRITE_DATA BIT_0
493	496
494		- uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
495		- uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
	497	+ __le16 fcp_cmnd_dseg_len; /* Data segment length. */
	498	+ /* Data segment address. */
	499	+ __le64 fcp_cmnd_dseg_address __packed;
	500	+ /* Data segment address. */
	501	+ __le64 fcp_rsp_dseg_address __packed;
496	502
497		- uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
498		-
499		- uint32_t byte_count; /* Total byte count. */
	503	+ __le32 byte_count; /* Total byte count. */
500	504
501	505	uint8_t port_id[3]; /* PortID of destination port. */
502	506	uint8_t vp_index;
503	507
504		- uint32_t fcp_data_dseg_address[2]; /* Data segment address. */
505		- uint32_t fcp_data_dseg_len; /* Data segment length. */
	508	+ struct dsd64 fcp_dsd;
506	509	};
507	510
508	511	#define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
..	..	@@ -514,16 +517,16 @@
514	517
515	518	uint32_t handle; /* System handle. */
516	519
517		- uint16_t nport_handle; /* N_PORT handle. */
518		- uint16_t timeout; /* Command timeout. */
	520	+ __le16 nport_handle; /* N_PORT handle. */
	521	+ __le16 timeout; /* Command timeout. */
519	522	#define FW_MAX_TIMEOUT 0x1999
520	523
521		- uint16_t dseg_count; /* Data segment count. */
	524	+ __le16 dseg_count; /* Data segment count. */
522	525	uint16_t reserved_1;
523	526
524	527	struct scsi_lun lun; /* FCP LUN (BE). */
525	528
526		- uint16_t task_mgmt_flags; /* Task management flags. */
	529	+ __le16 task_mgmt_flags; /* Task management flags. */
527	530	#define TMF_CLEAR_ACA BIT_14
528	531	#define TMF_TARGET_RESET BIT_13
529	532	#define TMF_LUN_RESET BIT_12
..	..	@@ -543,13 +546,12 @@
543	546	uint8_t crn;
544	547
545	548	uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
546		- uint32_t byte_count; /* Total byte count. */
	549	+ __le32 byte_count; /* Total byte count. */
547	550
548	551	uint8_t port_id[3]; /* PortID of destination port. */
549	552	uint8_t vp_index;
550	553
551		- uint32_t dseg_0_address[2]; /* Data segment 0 address. */
552		- uint32_t dseg_0_len; /* Data segment 0 length. */
	554	+ struct dsd64 dsd;
553	555	};
554	556
555	557	#define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
..	..	@@ -562,29 +564,29 @@
562	564
563	565	uint32_t handle; /* System handle. */
564	566
565		- uint16_t nport_handle; /* N_PORT handle. */
566		- uint16_t timeout; /* Command timeout. */
	567	+ __le16 nport_handle; /* N_PORT handle. */
	568	+ __le16 timeout; /* Command timeout. */
567	569
568		- uint16_t dseg_count; /* Data segment count. */
	570	+ __le16 dseg_count; /* Data segment count. */
569	571
570		- uint16_t fcp_rsp_dseg_len; /* FCP_RSP DSD length. */
	572	+ __le16 fcp_rsp_dseg_len; /* FCP_RSP DSD length. */
571	573
572	574	struct scsi_lun lun; /* FCP LUN (BE). */
573	575
574		- uint16_t control_flags; /* Control flags. */
	576	+ __le16 control_flags; /* Control flags. */
575	577
576		- uint16_t fcp_cmnd_dseg_len; /* Data segment length. */
577		- uint32_t fcp_cmnd_dseg_address[2]; /* Data segment address. */
	578	+ __le16 fcp_cmnd_dseg_len; /* Data segment length. */
	579	+ __le64 fcp_cmnd_dseg_address __packed;
	580	+ /* Data segment address. */
	581	+ __le64 fcp_rsp_dseg_address __packed;
578	582
579		- uint32_t fcp_rsp_dseg_address[2]; /* Data segment address. */
580		-
581		- uint32_t byte_count; /* Total byte count. */
	583	+ __le32 byte_count; /* Total byte count. */
582	584
583	585	uint8_t port_id[3]; /* PortID of destination port. */
584	586	uint8_t vp_index;
585	587
586		- uint32_t crc_context_address[2]; /* Data segment address. */
587		- uint16_t crc_context_len; /* Data segment length. */
	588	+ __le64 crc_context_address __packed; /* Data segment address. */
	589	+ __le16 crc_context_len; /* Data segment length. */
588	590	uint16_t reserved_1; /* MUST be set to 0. */
589	591	};
590	592
..	..	@@ -601,32 +603,32 @@
601	603
602	604	uint32_t handle; /* System handle. */
603	605
604		- uint16_t comp_status; /* Completion status. */
605		- uint16_t ox_id; /* OX_ID used by the firmware. */
	606	+ __le16 comp_status; /* Completion status. */
	607	+ __le16 ox_id; /* OX_ID used by the firmware. */
606	608
607		- uint32_t residual_len; /* FW calc residual transfer length. */
	609	+ __le32 residual_len; /* FW calc residual transfer length. */
608	610
609	611	union {
610		- uint16_t reserved_1;
611		- uint16_t nvme_rsp_pyld_len;
	612	+ __le16 reserved_1;
	613	+ __le16 nvme_rsp_pyld_len;
612	614	};
613	615
614		- uint16_t state_flags; /* State flags. */
	616	+ __le16 state_flags; /* State flags. */
615	617	#define SF_TRANSFERRED_DATA BIT_11
616	618	#define SF_NVME_ERSP BIT_6
617	619	#define SF_FCP_RSP_DMA BIT_0
618	620
619		- uint16_t retry_delay;
620		- uint16_t scsi_status; /* SCSI status. */
	621	+ __le16 status_qualifier;
	622	+ __le16 scsi_status; /* SCSI status. */
621	623	#define SS_CONFIRMATION_REQ BIT_12
622	624
623		- uint32_t rsp_residual_count; /* FCP RSP residual count. */
	625	+ __le32 rsp_residual_count; /* FCP RSP residual count. */
624	626
625		- uint32_t sense_len; /* FCP SENSE length. */
	627	+ __le32 sense_len; /* FCP SENSE length. */
626	628
627	629	union {
628	630	struct {
629		- uint32_t rsp_data_len; /* FCP response data length */
	631	+ __le32 rsp_data_len; /* FCP response data length */
630	632	uint8_t data[28]; /* FCP rsp/sense information */
631	633	};
632	634	struct nvme_fc_ersp_iu nvme_ersp;
..	..	@@ -669,7 +671,7 @@
669	671
670	672	uint32_t handle; /* System handle. */
671	673
672		- uint16_t nport_handle; /* N_PORT handle. */
	674	+ __le16 nport_handle; /* N_PORT handle. */
673	675
674	676	uint8_t modifier; /* Modifier (7-0). */
675	677	#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
..	..	@@ -698,29 +700,70 @@
698	700
699	701	uint32_t handle; /* System handle. */
700	702
701		- uint16_t comp_status; /* Completion status. */
	703	+ __le16 comp_status; /* Completion status. */
702	704
703		- uint16_t nport_handle; /* N_PORT handle. */
	705	+ __le16 nport_handle; /* N_PORT handle. */
704	706
705		- uint16_t cmd_dsd_count;
	707	+ __le16 cmd_dsd_count;
706	708
707	709	uint8_t vp_index;
708	710	uint8_t reserved_1;
709	711
710		- uint16_t timeout; /* Command timeout. */
	712	+ __le16 timeout; /* Command timeout. */
711	713	uint16_t reserved_2;
712	714
713		- uint16_t rsp_dsd_count;
	715	+ __le16 rsp_dsd_count;
714	716
715	717	uint8_t reserved_3[10];
716	718
717		- uint32_t rsp_byte_count;
718		- uint32_t cmd_byte_count;
	719	+ __le32 rsp_byte_count;
	720	+ __le32 cmd_byte_count;
719	721
720		- uint32_t dseg_0_address[2]; /* Data segment 0 address. */
721		- uint32_t dseg_0_len; /* Data segment 0 length. */
722		- uint32_t dseg_1_address[2]; /* Data segment 1 address. */
723		- uint32_t dseg_1_len; /* Data segment 1 length. */
	722	+ struct dsd64 dsd[2];
	723	+};
	724	+
	725	+#define PURX_ELS_HEADER_SIZE 0x18
	726	+
	727	+/*
	728	+ * ISP queue - PUREX IOCB entry structure definition
	729	+ */
	730	+#define PUREX_IOCB_TYPE 0x51 /* CT Pass Through IOCB entry */
	731	+struct purex_entry_24xx {
	732	+ uint8_t entry_type; /* Entry type. */
	733	+ uint8_t entry_count; /* Entry count. */
	734	+ uint8_t sys_define; /* System defined. */
	735	+ uint8_t entry_status; /* Entry Status. */
	736	+
	737	+ __le16 reserved1;
	738	+ uint8_t vp_idx;
	739	+ uint8_t reserved2;
	740	+
	741	+ __le16 status_flags;
	742	+ __le16 nport_handle;
	743	+
	744	+ __le16 frame_size;
	745	+ __le16 trunc_frame_size;
	746	+
	747	+ __le32 rx_xchg_addr;
	748	+
	749	+ uint8_t d_id[3];
	750	+ uint8_t r_ctl;
	751	+
	752	+ uint8_t s_id[3];
	753	+ uint8_t cs_ctl;
	754	+
	755	+ uint8_t f_ctl[3];
	756	+ uint8_t type;
	757	+
	758	+ __le16 seq_cnt;
	759	+ uint8_t df_ctl;
	760	+ uint8_t seq_id;
	761	+
	762	+ __le16 rx_id;
	763	+ __le16 ox_id;
	764	+ __le32 param;
	765	+
	766	+ uint8_t els_frame_payload[20];
724	767	};
725	768
726	769	/*
..	..	@@ -735,27 +778,26 @@
735	778
736	779	uint32_t handle; /* System handle. */
737	780
738		- uint16_t reserved_1;
	781	+ __le16 comp_status; /* response only */
	782	+ __le16 nport_handle;
739	783
740		- uint16_t nport_handle; /* N_PORT handle. */
741		-
742		- uint16_t tx_dsd_count;
	784	+ __le16 tx_dsd_count;
743	785
744	786	uint8_t vp_index;
745	787	uint8_t sof_type;
746	788	#define EST_SOFI3 (1 << 4)
747	789	#define EST_SOFI2 (3 << 4)
748	790
749		- uint32_t rx_xchg_address; /* Receive exchange address. */
750		- uint16_t rx_dsd_count;
	791	+ __le32 rx_xchg_address; /* Receive exchange address. */
	792	+ __le16 rx_dsd_count;
751	793
752	794	uint8_t opcode;
753	795	uint8_t reserved_2;
754	796
755		- uint8_t port_id[3];
	797	+ uint8_t d_id[3];
756	798	uint8_t s_id[3];
757	799
758		- uint16_t control_flags; /* Control flags. */
	800	+ __le16 control_flags; /* Control flags. */
759	801	#define ECF_PAYLOAD_DESCR_MASK (BIT_15\|BIT_14\|BIT_13)
760	802	#define EPD_ELS_COMMAND (0 << 13)
761	803	#define EPD_ELS_ACC (1 << 13)
..	..	@@ -764,13 +806,24 @@
764	806	#define ECF_CLR_PASSTHRU_PEND BIT_12
765	807	#define ECF_INCL_FRAME_HDR BIT_11
766	808
767		- uint32_t rx_byte_count;
768		- uint32_t tx_byte_count;
	809	+ union {
	810	+ struct {
	811	+ __le32 rx_byte_count;
	812	+ __le32 tx_byte_count;
769	813
770		- uint32_t tx_address[2]; /* Data segment 0 address. */
771		- uint32_t tx_len; /* Data segment 0 length. */
772		- uint32_t rx_address[2]; /* Data segment 1 address. */
773		- uint32_t rx_len; /* Data segment 1 length. */
	814	+ __le64 tx_address __packed; /* DSD 0 address. */
	815	+ __le32 tx_len; /* DSD 0 length. */
	816	+
	817	+ __le64 rx_address __packed; /* DSD 1 address. */
	818	+ __le32 rx_len; /* DSD 1 length. */
	819	+ };
	820	+ struct {
	821	+ __le32 total_byte_count;
	822	+ __le32 error_subcode_1;
	823	+ __le32 error_subcode_2;
	824	+ __le32 error_subcode_3;
	825	+ };
	826	+ };
774	827	};
775	828
776	829	struct els_sts_entry_24xx {
..	..	@@ -779,32 +832,33 @@
779	832	uint8_t sys_define; /* System Defined. */
780	833	uint8_t entry_status; /* Entry Status. */
781	834
782		- uint32_t handle; /* System handle. */
	835	+ __le32 handle; /* System handle. */
783	836
784		- uint16_t comp_status;
	837	+ __le16 comp_status;
785	838
786		- uint16_t nport_handle; /* N_PORT handle. */
	839	+ __le16 nport_handle; /* N_PORT handle. */
787	840
788		- uint16_t reserved_1;
	841	+ __le16 reserved_1;
789	842
790	843	uint8_t vp_index;
791	844	uint8_t sof_type;
792	845
793		- uint32_t rx_xchg_address; /* Receive exchange address. */
794		- uint16_t reserved_2;
	846	+ __le32 rx_xchg_address; /* Receive exchange address. */
	847	+ __le16 reserved_2;
795	848
796	849	uint8_t opcode;
797	850	uint8_t reserved_3;
798	851
799		- uint8_t port_id[3];
800		- uint8_t reserved_4;
	852	+ uint8_t d_id[3];
	853	+ uint8_t s_id[3];
801	854
802		- uint16_t reserved_5;
	855	+ __le16 control_flags; /* Control flags. */
	856	+ __le32 total_byte_count;
	857	+ __le32 error_subcode_1;
	858	+ __le32 error_subcode_2;
	859	+ __le32 error_subcode_3;
803	860
804		- uint16_t control_flags; /* Control flags. */
805		- uint32_t total_byte_count;
806		- uint32_t error_subcode_1;
807		- uint32_t error_subcode_2;
	861	+ __le32 reserved_4[4];
808	862	};
809	863	/*
810	864	* ISP queue - Mailbox Command entry structure definition.
..	..	@@ -831,12 +885,12 @@
831	885
832	886	uint32_t handle; /* System handle. */
833	887
834		- uint16_t comp_status; /* Completion status. */
	888	+ __le16 comp_status; /* Completion status. */
835	889	#define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
836	890
837		- uint16_t nport_handle; /* N_PORT handle. */
	891	+ __le16 nport_handle; /* N_PORT handle. */
838	892
839		- uint16_t control_flags; /* Control flags. */
	893	+ __le16 control_flags; /* Control flags. */
840	894	/* Modifiers. */
841	895	#define LCF_INCLUDE_SNS BIT_10 /* Include SNS (FFFFFC) during LOGO. */
842	896	#define LCF_FCP2_OVERRIDE BIT_9 /* Set/Reset word 3 of PRLI. */
..	..	@@ -865,7 +919,7 @@
865	919
866	920	uint8_t rsp_size; /* Response size in 32bit words. */
867	921
868		- uint32_t io_parameter[11]; /* General I/O parameters. */
	922	+ __le32 io_parameter[11]; /* General I/O parameters. */
869	923	#define LSC_SCODE_NOLINK 0x01
870	924	#define LSC_SCODE_NOIOCB 0x02
871	925	#define LSC_SCODE_NOXCB 0x03
..	..	@@ -893,17 +947,17 @@
893	947
894	948	uint32_t handle; /* System handle. */
895	949
896		- uint16_t nport_handle; /* N_PORT handle. */
	950	+ __le16 nport_handle; /* N_PORT handle. */
897	951
898	952	uint16_t reserved_1;
899	953
900		- uint16_t delay; /* Activity delay in seconds. */
	954	+ __le16 delay; /* Activity delay in seconds. */
901	955
902		- uint16_t timeout; /* Command timeout. */
	956	+ __le16 timeout; /* Command timeout. */
903	957
904	958	struct scsi_lun lun; /* FCP LUN (BE). */
905	959
906		- uint32_t control_flags; /* Control Flags. */
	960	+ __le32 control_flags; /* Control Flags. */
907	961	#define TCF_NOTMCMD_TO_TARGET BIT_31
908	962	#define TCF_LUN_RESET BIT_4
909	963	#define TCF_ABORT_TASK_SET BIT_3
..	..	@@ -928,15 +982,15 @@
928	982
929	983	uint32_t handle; /* System handle. */
930	984
931		- uint16_t nport_handle; /* N_PORT handle. */
	985	+ __le16 nport_handle; /* N_PORT handle. */
932	986	/* or Completion status. */
933	987
934		- uint16_t options; /* Options. */
	988	+ __le16 options; /* Options. */
935	989	#define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */
936	990
937	991	uint32_t handle_to_abort; /* System handle to abort. */
938	992
939		- uint16_t req_que_no;
	993	+ __le16 req_que_no;
940	994	uint8_t reserved_1[30];
941	995
942	996	uint8_t port_id[3]; /* PortID of destination port. */
..	..	@@ -945,11 +999,96 @@
945	999	uint8_t reserved_2[12];
946	1000	};
947	1001
	1002	+#define ABTS_RCV_TYPE 0x54
	1003	+#define ABTS_RSP_TYPE 0x55
	1004	+struct abts_entry_24xx {
	1005	+ uint8_t entry_type;
	1006	+ uint8_t entry_count;
	1007	+ uint8_t handle_count;
	1008	+ uint8_t entry_status;
	1009	+
	1010	+ __le32 handle; /* type 0x55 only */
	1011	+
	1012	+ __le16 comp_status; /* type 0x55 only */
	1013	+ __le16 nport_handle; /* type 0x54 only */
	1014	+
	1015	+ __le16 control_flags; /* type 0x55 only */
	1016	+ uint8_t vp_idx;
	1017	+ uint8_t sof_type; /* sof_type is upper nibble */
	1018	+
	1019	+ __le32 rx_xch_addr;
	1020	+
	1021	+ uint8_t d_id[3];
	1022	+ uint8_t r_ctl;
	1023	+
	1024	+ uint8_t s_id[3];
	1025	+ uint8_t cs_ctl;
	1026	+
	1027	+ uint8_t f_ctl[3];
	1028	+ uint8_t type;
	1029	+
	1030	+ __le16 seq_cnt;
	1031	+ uint8_t df_ctl;
	1032	+ uint8_t seq_id;
	1033	+
	1034	+ __le16 rx_id;
	1035	+ __le16 ox_id;
	1036	+
	1037	+ __le32 param;
	1038	+
	1039	+ union {
	1040	+ struct {
	1041	+ __le32 subcode3;
	1042	+ __le32 rsvd;
	1043	+ __le32 subcode1;
	1044	+ __le32 subcode2;
	1045	+ } error;
	1046	+ struct {
	1047	+ __le16 rsrvd1;
	1048	+ uint8_t last_seq_id;
	1049	+ uint8_t seq_id_valid;
	1050	+ __le16 aborted_rx_id;
	1051	+ __le16 aborted_ox_id;
	1052	+ __le16 high_seq_cnt;
	1053	+ __le16 low_seq_cnt;
	1054	+ } ba_acc;
	1055	+ struct {
	1056	+ uint8_t vendor_unique;
	1057	+ uint8_t explanation;
	1058	+ uint8_t reason;
	1059	+ } ba_rjt;
	1060	+ } payload;
	1061	+
	1062	+ __le32 rx_xch_addr_to_abort;
	1063	+} __packed;
	1064	+
	1065	+/* ABTS payload explanation values */
	1066	+#define BA_RJT_EXP_NO_ADDITIONAL 0
	1067	+#define BA_RJT_EXP_INV_OX_RX_ID 3
	1068	+#define BA_RJT_EXP_SEQ_ABORTED 5
	1069	+
	1070	+/* ABTS payload reason values */
	1071	+#define BA_RJT_RSN_INV_CMD_CODE 1
	1072	+#define BA_RJT_RSN_LOGICAL_ERROR 3
	1073	+#define BA_RJT_RSN_LOGICAL_BUSY 5
	1074	+#define BA_RJT_RSN_PROTOCOL_ERROR 7
	1075	+#define BA_RJT_RSN_UNABLE_TO_PERFORM 9
	1076	+#define BA_RJT_RSN_VENDOR_SPECIFIC 0xff
	1077	+
	1078	+/* FC_F values */
	1079	+#define FC_TYPE_BLD 0x000 /* Basic link data */
	1080	+#define FC_F_CTL_RSP_CNTXT 0x800000 /* Responder of exchange */
	1081	+#define FC_F_CTL_LAST_SEQ 0x100000 /* Last sequence */
	1082	+#define FC_F_CTL_END_SEQ 0x80000 /* Last sequence */
	1083	+#define FC_F_CTL_SEQ_INIT 0x010000 /* Sequence initiative */
	1084	+#define FC_ROUTING_BLD 0x80 /* Basic link data frame */
	1085	+#define FC_R_CTL_BLD_BA_ACC 0x04 /* BA_ACC (basic accept) */
	1086	+
948	1087	/*
949	1088	* ISP I/O Register Set structure definitions.
950	1089	*/
951	1090	struct device_reg_24xx {
952		- uint32_t flash_addr; /* Flash/NVRAM BIOS address. */
	1091	+ __le32 flash_addr; /* Flash/NVRAM BIOS address. */
953	1092	#define FARX_DATA_FLAG BIT_31
954	1093	#define FARX_ACCESS_FLASH_CONF 0x7FFD0000
955	1094	#define FARX_ACCESS_FLASH_DATA 0x7FF00000
..	..	@@ -1000,9 +1139,9 @@
1000	1139	#define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
1001	1140	#define HW_EVENT_FLASH_FW_ERR 0xF024
1002	1141
1003		- uint32_t flash_data; /* Flash/NVRAM BIOS data. */
	1142	+ __le32 flash_data; /* Flash/NVRAM BIOS data. */
1004	1143
1005		- uint32_t ctrl_status; /* Control/Status. */
	1144	+ __le32 ctrl_status; /* Control/Status. */
1006	1145	#define CSRX_FLASH_ACCESS_ERROR BIT_18 /* Flash/NVRAM Access Error. */
1007	1146	#define CSRX_DMA_ACTIVE BIT_17 /* DMA Active status. */
1008	1147	#define CSRX_DMA_SHUTDOWN BIT_16 /* DMA Shutdown control status. */
..	..	@@ -1028,35 +1167,35 @@
1028	1167	#define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1029	1168	#define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */
1030	1169
1031		- uint32_t ictrl; /* Interrupt control. */
	1170	+ __le32 ictrl; /* Interrupt control. */
1032	1171	#define ICRX_EN_RISC_INT BIT_3 /* Enable RISC interrupts on PCI. */
1033	1172
1034		- uint32_t istatus; /* Interrupt status. */
	1173	+ __le32 istatus; /* Interrupt status. */
1035	1174	#define ISRX_RISC_INT BIT_3 /* RISC interrupt. */
1036	1175
1037		- uint32_t unused_1[2]; /* Gap. */
	1176	+ __le32 unused_1[2]; /* Gap. */
1038	1177
1039	1178	/* Request Queue. */
1040		- uint32_t req_q_in; /* In-Pointer. */
1041		- uint32_t req_q_out; /* Out-Pointer. */
	1179	+ __le32 req_q_in; /* In-Pointer. */
	1180	+ __le32 req_q_out; /* Out-Pointer. */
1042	1181	/* Response Queue. */
1043		- uint32_t rsp_q_in; /* In-Pointer. */
1044		- uint32_t rsp_q_out; /* Out-Pointer. */
	1182	+ __le32 rsp_q_in; /* In-Pointer. */
	1183	+ __le32 rsp_q_out; /* Out-Pointer. */
1045	1184	/* Priority Request Queue. */
1046		- uint32_t preq_q_in; /* In-Pointer. */
1047		- uint32_t preq_q_out; /* Out-Pointer. */
	1185	+ __le32 preq_q_in; /* In-Pointer. */
	1186	+ __le32 preq_q_out; /* Out-Pointer. */
1048	1187
1049		- uint32_t unused_2[2]; /* Gap. */
	1188	+ __le32 unused_2[2]; /* Gap. */
1050	1189
1051	1190	/* ATIO Queue. */
1052		- uint32_t atio_q_in; /* In-Pointer. */
1053		- uint32_t atio_q_out; /* Out-Pointer. */
	1191	+ __le32 atio_q_in; /* In-Pointer. */
	1192	+ __le32 atio_q_out; /* Out-Pointer. */
1054	1193
1055		- uint32_t host_status;
	1194	+ __le32 host_status;
1056	1195	#define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
1057	1196	#define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
1058	1197
1059		- uint32_t hccr; /* Host command & control register. */
	1198	+ __le32 hccr; /* Host command & control register. */
1060	1199	/* HCCR statuses. */
1061	1200	#define HCCRX_HOST_INT BIT_6 /* Host to RISC interrupt bit. */
1062	1201	#define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
..	..	@@ -1078,7 +1217,7 @@
1078	1217	/* Clear RISC to PCI interrupt. */
1079	1218	#define HCCRX_CLR_RISC_INT 0xA0000000
1080	1219
1081		- uint32_t gpiod; /* GPIO Data register. */
	1220	+ __le32 gpiod; /* GPIO Data register. */
1082	1221
1083	1222	/* LED update mask. */
1084	1223	#define GPDX_LED_UPDATE_MASK (BIT_20\|BIT_19\|BIT_18)
..	..	@@ -1097,7 +1236,7 @@
1097	1236	/* Data in/out. */
1098	1237	#define GPDX_DATA_INOUT (BIT_1\|BIT_0)
1099	1238
1100		- uint32_t gpioe; /* GPIO Enable register. */
	1239	+ __le32 gpioe; /* GPIO Enable register. */
1101	1240	/* Enable update mask. */
1102	1241	#define GPEX_ENABLE_UPDATE_MASK (BIT_17\|BIT_16)
1103	1242	/* Enable update mask. */
..	..	@@ -1105,56 +1244,56 @@
1105	1244	/* Enable. */
1106	1245	#define GPEX_ENABLE (BIT_1\|BIT_0)
1107	1246
1108		- uint32_t iobase_addr; /* I/O Bus Base Address register. */
	1247	+ __le32 iobase_addr; /* I/O Bus Base Address register. */
1109	1248
1110		- uint32_t unused_3[10]; /* Gap. */
	1249	+ __le32 unused_3[10]; /* Gap. */
1111	1250
1112		- uint16_t mailbox0;
1113		- uint16_t mailbox1;
1114		- uint16_t mailbox2;
1115		- uint16_t mailbox3;
1116		- uint16_t mailbox4;
1117		- uint16_t mailbox5;
1118		- uint16_t mailbox6;
1119		- uint16_t mailbox7;
1120		- uint16_t mailbox8;
1121		- uint16_t mailbox9;
1122		- uint16_t mailbox10;
1123		- uint16_t mailbox11;
1124		- uint16_t mailbox12;
1125		- uint16_t mailbox13;
1126		- uint16_t mailbox14;
1127		- uint16_t mailbox15;
1128		- uint16_t mailbox16;
1129		- uint16_t mailbox17;
1130		- uint16_t mailbox18;
1131		- uint16_t mailbox19;
1132		- uint16_t mailbox20;
1133		- uint16_t mailbox21;
1134		- uint16_t mailbox22;
1135		- uint16_t mailbox23;
1136		- uint16_t mailbox24;
1137		- uint16_t mailbox25;
1138		- uint16_t mailbox26;
1139		- uint16_t mailbox27;
1140		- uint16_t mailbox28;
1141		- uint16_t mailbox29;
1142		- uint16_t mailbox30;
1143		- uint16_t mailbox31;
	1251	+ __le16 mailbox0;
	1252	+ __le16 mailbox1;
	1253	+ __le16 mailbox2;
	1254	+ __le16 mailbox3;
	1255	+ __le16 mailbox4;
	1256	+ __le16 mailbox5;
	1257	+ __le16 mailbox6;
	1258	+ __le16 mailbox7;
	1259	+ __le16 mailbox8;
	1260	+ __le16 mailbox9;
	1261	+ __le16 mailbox10;
	1262	+ __le16 mailbox11;
	1263	+ __le16 mailbox12;
	1264	+ __le16 mailbox13;
	1265	+ __le16 mailbox14;
	1266	+ __le16 mailbox15;
	1267	+ __le16 mailbox16;
	1268	+ __le16 mailbox17;
	1269	+ __le16 mailbox18;
	1270	+ __le16 mailbox19;
	1271	+ __le16 mailbox20;
	1272	+ __le16 mailbox21;
	1273	+ __le16 mailbox22;
	1274	+ __le16 mailbox23;
	1275	+ __le16 mailbox24;
	1276	+ __le16 mailbox25;
	1277	+ __le16 mailbox26;
	1278	+ __le16 mailbox27;
	1279	+ __le16 mailbox28;
	1280	+ __le16 mailbox29;
	1281	+ __le16 mailbox30;
	1282	+ __le16 mailbox31;
1144	1283
1145		- uint32_t iobase_window;
1146		- uint32_t iobase_c4;
1147		- uint32_t iobase_c8;
1148		- uint32_t unused_4_1[6]; /* Gap. */
1149		- uint32_t iobase_q;
1150		- uint32_t unused_5[2]; /* Gap. */
1151		- uint32_t iobase_select;
1152		- uint32_t unused_6[2]; /* Gap. */
1153		- uint32_t iobase_sdata;
	1284	+ __le32 iobase_window;
	1285	+ __le32 iobase_c4;
	1286	+ __le32 iobase_c8;
	1287	+ __le32 unused_4_1[6]; /* Gap. */
	1288	+ __le32 iobase_q;
	1289	+ __le32 unused_5[2]; /* Gap. */
	1290	+ __le32 iobase_select;
	1291	+ __le32 unused_6[2]; /* Gap. */
	1292	+ __le32 iobase_sdata;
1154	1293	};
1155	1294	/* RISC-RISC semaphore register PCI offet */
1156	1295	#define RISC_REGISTER_BASE_OFFSET 0x7010
1157		-#define RISC_REGISTER_WINDOW_OFFET 0x6
	1296	+#define RISC_REGISTER_WINDOW_OFFSET 0x6
1158	1297
1159	1298	/* RISC-RISC semaphore/flag register (risc address 0x7016) */
1160	1299
..	..	@@ -1216,8 +1355,8 @@
1216	1355	struct mid_init_cb_24xx {
1217	1356	struct init_cb_24xx init_cb;
1218	1357
1219		- uint16_t count;
1220		- uint16_t options;
	1358	+ __le16 count;
	1359	+ __le16 options;
1221	1360
1222	1361	struct mid_conf_entry_24xx entries[MAX_MULTI_ID_FABRIC];
1223	1362	};
..	..	@@ -1251,27 +1390,27 @@
1251	1390
1252	1391	uint32_t handle; /* System handle. */
1253	1392
1254		- uint16_t vp_idx_failed;
	1393	+ __le16 vp_idx_failed;
1255	1394
1256		- uint16_t comp_status; /* Completion status. */
	1395	+ __le16 comp_status; /* Completion status. */
1257	1396	#define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1258	1397	#define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1259	1398	#define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1260	1399
1261		- uint16_t command;
	1400	+ __le16 command;
1262	1401	#define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1263	1402	#define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1264	1403	#define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1265	1404	#define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1266	1405	#define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1267	1406
1268		- uint16_t vp_count;
	1407	+ __le16 vp_count;
1269	1408
1270	1409	uint8_t vp_idx_map[16];
1271		- uint16_t flags;
1272		- uint16_t id;
	1410	+ __le16 flags;
	1411	+ __le16 id;
1273	1412	uint16_t reserved_4;
1274		- uint16_t hopct;
	1413	+ __le16 hopct;
1275	1414	uint8_t reserved_5[24];
1276	1415	};
1277	1416
..	..	@@ -1287,12 +1426,12 @@
1287	1426
1288	1427	uint32_t handle; /* System handle. */
1289	1428
1290		- uint16_t flags;
	1429	+ __le16 flags;
1291	1430	#define CS_VF_BIND_VPORTS_TO_VF BIT_0
1292	1431	#define CS_VF_SET_QOS_OF_VPORTS BIT_1
1293	1432	#define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1294	1433
1295		- uint16_t comp_status; /* Completion status. */
	1434	+ __le16 comp_status; /* Completion status. */
1296	1435	#define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1297	1436	#define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1298	1437	#define CS_VCT_ERROR 0x03 /* Unknown error. */
..	..	@@ -1319,9 +1458,9 @@
1319	1458	uint16_t reserved_vp2;
1320	1459	uint8_t port_name_idx2[WWN_SIZE];
1321	1460	uint8_t node_name_idx2[WWN_SIZE];
1322		- uint16_t id;
	1461	+ __le16 id;
1323	1462	uint16_t reserved_4;
1324		- uint16_t hopct;
	1463	+ __le16 hopct;
1325	1464	uint8_t reserved_5[2];
1326	1465	};
1327	1466
..	..	@@ -1348,7 +1487,7 @@
1348	1487	uint8_t entry_count; /* Entry count. */
1349	1488	uint8_t sys_define; /* System defined. */
1350	1489	uint8_t entry_status; /* Entry Status. */
1351		- uint32_t resv1;
	1490	+ __le32 resv1;
1352	1491	uint8_t vp_acquired;
1353	1492	uint8_t vp_setup;
1354	1493	uint8_t vp_idx; /* Format 0=reserved */
..	..	@@ -1357,12 +1496,12 @@
1357	1496	uint8_t port_id[3];
1358	1497	uint8_t format;
1359	1498	union {
1360		- struct {
	1499	+ struct _f0 {
1361	1500	/* format 0 loop */
1362	1501	uint8_t vp_idx_map[16];
1363	1502	uint8_t reserved_4[32];
1364	1503	} f0;
1365		- struct {
	1504	+ struct _f1 {
1366	1505	/* format 1 fabric */
1367	1506	uint8_t vpstat1_subcode; /* vp_status=1 subcode */
1368	1507	uint8_t flags;
..	..	@@ -1384,21 +1523,22 @@
1384	1523	uint16_t bbcr;
1385	1524	uint8_t reserved_5[6];
1386	1525	} f1;
1387		- struct { /* format 2: N2N direct connect */
1388		- uint8_t vpstat1_subcode;
1389		- uint8_t flags;
1390		- uint16_t rsv6;
1391		- uint8_t rsv2[12];
	1526	+ struct _f2 { /* format 2: N2N direct connect */
	1527	+ uint8_t vpstat1_subcode;
	1528	+ uint8_t flags;
	1529	+ uint16_t fip_flags;
	1530	+ uint8_t rsv2[12];
1392	1531
1393		- uint8_t ls_rjt_vendor;
1394		- uint8_t ls_rjt_explanation;
1395		- uint8_t ls_rjt_reason;
1396		- uint8_t rsv3[5];
	1532	+ uint8_t ls_rjt_vendor;
	1533	+ uint8_t ls_rjt_explanation;
	1534	+ uint8_t ls_rjt_reason;
	1535	+ uint8_t rsv3[5];
1397	1536
1398		- uint8_t port_name[8];
1399		- uint8_t node_name[8];
1400		- uint8_t remote_nport_id[4];
1401		- uint32_t reserved_5;
	1537	+ uint8_t port_name[8];
	1538	+ uint8_t node_name[8];
	1539	+ uint16_t bbcr;
	1540	+ uint8_t reserved_5[2];
	1541	+ uint8_t remote_nport_id[4];
1402	1542	} f2;
1403	1543	} u;
1404	1544	};
..	..	@@ -1411,20 +1551,20 @@
1411	1551	uint8_t entry_status; /* Entry Status. */
1412	1552
1413	1553	uint32_t handle; /* System handle. */
1414		- uint16_t comp_status; /* Completion status. */
1415		- uint16_t timeout; /* timeout */
1416		- uint16_t adim_tagging_mode;
	1554	+ __le16 comp_status; /* Completion status. */
	1555	+ __le16 timeout; /* timeout */
	1556	+ __le16 adim_tagging_mode;
1417	1557
1418		- uint16_t vfport_id;
	1558	+ __le16 vfport_id;
1419	1559	uint32_t exch_addr;
1420	1560
1421		- uint16_t nport_handle; /* N_PORT handle. */
1422		- uint16_t control_flags;
	1561	+ __le16 nport_handle; /* N_PORT handle. */
	1562	+ __le16 control_flags;
1423	1563	uint32_t io_parameter_0;
1424	1564	uint32_t io_parameter_1;
1425		- uint32_t tx_address[2]; /* Data segment 0 address. */
	1565	+ __le64 tx_address __packed; /* Data segment 0 address. */
1426	1566	uint32_t tx_len; /* Data segment 0 length. */
1427		- uint32_t rx_address[2]; /* Data segment 1 address. */
	1567	+ __le64 rx_address __packed; /* Data segment 1 address. */
1428	1568	uint32_t rx_len; /* Data segment 1 length. */
1429	1569	};
1430	1570
..	..	@@ -1434,13 +1574,13 @@
1434	1574
1435	1575	struct qla_fdt_layout {
1436	1576	uint8_t sig[4];
1437		- uint16_t version;
1438		- uint16_t len;
1439		- uint16_t checksum;
	1577	+ __le16 version;
	1578	+ __le16 len;
	1579	+ __le16 checksum;
1440	1580	uint8_t unused1[2];
1441	1581	uint8_t model[16];
1442		- uint16_t man_id;
1443		- uint16_t id;
	1582	+ __le16 man_id;
	1583	+ __le16 id;
1444	1584	uint8_t flags;
1445	1585	uint8_t erase_cmd;
1446	1586	uint8_t alt_erase_cmd;
..	..	@@ -1449,15 +1589,15 @@
1449	1589	uint8_t wrt_sts_reg_cmd;
1450	1590	uint8_t unprotect_sec_cmd;
1451	1591	uint8_t read_man_id_cmd;
1452		- uint32_t block_size;
1453		- uint32_t alt_block_size;
1454		- uint32_t flash_size;
1455		- uint32_t wrt_enable_data;
	1592	+ __le32 block_size;
	1593	+ __le32 alt_block_size;
	1594	+ __le32 flash_size;
	1595	+ __le32 wrt_enable_data;
1456	1596	uint8_t read_id_addr_len;
1457	1597	uint8_t wrt_disable_bits;
1458	1598	uint8_t read_dev_id_len;
1459	1599	uint8_t chip_erase_cmd;
1460		- uint16_t read_timeout;
	1600	+ __le16 read_timeout;
1461	1601	uint8_t protect_sec_cmd;
1462	1602	uint8_t unused2[65];
1463	1603	};
..	..	@@ -1466,18 +1606,11 @@
1466	1606
1467	1607	struct qla_flt_location {
1468	1608	uint8_t sig[4];
1469		- uint16_t start_lo;
1470		- uint16_t start_hi;
	1609	+ __le16 start_lo;
	1610	+ __le16 start_hi;
1471	1611	uint8_t version;
1472	1612	uint8_t unused[5];
1473		- uint16_t checksum;
1474		-};
1475		-
1476		-struct qla_flt_header {
1477		- uint16_t version;
1478		- uint16_t length;
1479		- uint16_t checksum;
1480		- uint16_t unused;
	1613	+ __le16 checksum;
1481	1614	};
1482	1615
1483	1616	#define FLT_REG_FW 0x01
..	..	@@ -1515,29 +1648,59 @@
1515	1648	#define FLT_REG_VPD_SEC_27XX_2 0xD8
1516	1649	#define FLT_REG_VPD_SEC_27XX_3 0xDA
1517	1650
	1651	+/* 28xx */
	1652	+#define FLT_REG_AUX_IMG_PRI_28XX 0x125
	1653	+#define FLT_REG_AUX_IMG_SEC_28XX 0x126
	1654	+#define FLT_REG_VPD_SEC_28XX_0 0x10C
	1655	+#define FLT_REG_VPD_SEC_28XX_1 0x10E
	1656	+#define FLT_REG_VPD_SEC_28XX_2 0x110
	1657	+#define FLT_REG_VPD_SEC_28XX_3 0x112
	1658	+#define FLT_REG_NVRAM_SEC_28XX_0 0x10D
	1659	+#define FLT_REG_NVRAM_SEC_28XX_1 0x10F
	1660	+#define FLT_REG_NVRAM_SEC_28XX_2 0x111
	1661	+#define FLT_REG_NVRAM_SEC_28XX_3 0x113
	1662	+#define FLT_REG_MPI_PRI_28XX 0xD3
	1663	+#define FLT_REG_MPI_SEC_28XX 0xF0
	1664	+#define FLT_REG_PEP_PRI_28XX 0xD1
	1665	+#define FLT_REG_PEP_SEC_28XX 0xF1
	1666	+
1518	1667	struct qla_flt_region {
1519		- uint32_t code;
1520		- uint32_t size;
1521		- uint32_t start;
1522		- uint32_t end;
	1668	+ __le16 code;
	1669	+ uint8_t attribute;
	1670	+ uint8_t reserved;
	1671	+ __le32 size;
	1672	+ __le32 start;
	1673	+ __le32 end;
1523	1674	};
	1675	+
	1676	+struct qla_flt_header {
	1677	+ __le16 version;
	1678	+ __le16 length;
	1679	+ __le16 checksum;
	1680	+ __le16 unused;
	1681	+ struct qla_flt_region region[0];
	1682	+};
	1683	+
	1684	+#define FLT_REGION_SIZE 16
	1685	+#define FLT_MAX_REGIONS 0xFF
	1686	+#define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS)
1524	1687
1525	1688	/* Flash NPIV Configuration Table ********************************************/
1526	1689
1527	1690	struct qla_npiv_header {
1528	1691	uint8_t sig[2];
1529		- uint16_t version;
1530		- uint16_t entries;
1531		- uint16_t unused[4];
1532		- uint16_t checksum;
	1692	+ __le16 version;
	1693	+ __le16 entries;
	1694	+ __le16 unused[4];
	1695	+ __le16 checksum;
1533	1696	};
1534	1697
1535	1698	struct qla_npiv_entry {
1536		- uint16_t flags;
1537		- uint16_t vf_id;
	1699	+ __le16 flags;
	1700	+ __le16 vf_id;
1538	1701	uint8_t q_qos;
1539	1702	uint8_t f_qos;
1540		- uint16_t unused1;
	1703	+ __le16 unused1;
1541	1704	uint8_t port_name[WWN_SIZE];
1542	1705	uint8_t node_name[WWN_SIZE];
1543	1706	};
..	..	@@ -1567,7 +1730,7 @@
1567	1730
1568	1731	uint32_t handle;
1569	1732
1570		- uint16_t options;
	1733	+ __le16 options;
1571	1734	#define VCO_DONT_UPDATE_FW BIT_0
1572	1735	#define VCO_FORCE_UPDATE BIT_1
1573	1736	#define VCO_DONT_RESET_UPDATE BIT_2
..	..	@@ -1575,21 +1738,20 @@
1575	1738	#define VCO_END_OF_DATA BIT_14
1576	1739	#define VCO_ENABLE_DSD BIT_15
1577	1740
1578		- uint16_t reserved_1;
	1741	+ __le16 reserved_1;
1579	1742
1580		- uint16_t data_seg_cnt;
1581		- uint16_t reserved_2[3];
	1743	+ __le16 data_seg_cnt;
	1744	+ __le16 reserved_2[3];
1582	1745
1583		- uint32_t fw_ver;
1584		- uint32_t exchange_address;
	1746	+ __le32 fw_ver;
	1747	+ __le32 exchange_address;
1585	1748
1586		- uint32_t reserved_3[3];
1587		- uint32_t fw_size;
1588		- uint32_t fw_seq_size;
1589		- uint32_t relative_offset;
	1749	+ __le32 reserved_3[3];
	1750	+ __le32 fw_size;
	1751	+ __le32 fw_seq_size;
	1752	+ __le32 relative_offset;
1590	1753
1591		- uint32_t dseg_address[2];
1592		- uint32_t dseg_length;
	1754	+ struct dsd64 dsd;
1593	1755	};
1594	1756
1595	1757	struct verify_chip_rsp_84xx {
..	..	@@ -1600,22 +1762,22 @@
1600	1762
1601	1763	uint32_t handle;
1602	1764
1603		- uint16_t comp_status;
	1765	+ __le16 comp_status;
1604	1766	#define CS_VCS_CHIP_FAILURE 0x3
1605	1767	#define CS_VCS_BAD_EXCHANGE 0x8
1606	1768	#define CS_VCS_SEQ_COMPLETEi 0x40
1607	1769
1608		- uint16_t failure_code;
	1770	+ __le16 failure_code;
1609	1771	#define VFC_CHECKSUM_ERROR 0x1
1610	1772	#define VFC_INVALID_LEN 0x2
1611	1773	#define VFC_ALREADY_IN_PROGRESS 0x8
1612	1774
1613		- uint16_t reserved_1[4];
	1775	+ __le16 reserved_1[4];
1614	1776
1615		- uint32_t fw_ver;
1616		- uint32_t exchange_address;
	1777	+ __le32 fw_ver;
	1778	+ __le32 exchange_address;
1617	1779
1618		- uint32_t reserved_2[6];
	1780	+ __le32 reserved_2[6];
1619	1781	};
1620	1782
1621	1783	#define ACCESS_CHIP_IOCB_TYPE 0x2B
..	..	@@ -1627,27 +1789,26 @@
1627	1789
1628	1790	uint32_t handle;
1629	1791
1630		- uint16_t options;
	1792	+ __le16 options;
1631	1793	#define ACO_DUMP_MEMORY 0x0
1632	1794	#define ACO_LOAD_MEMORY 0x1
1633	1795	#define ACO_CHANGE_CONFIG_PARAM 0x2
1634	1796	#define ACO_REQUEST_INFO 0x3
1635	1797
1636		- uint16_t reserved1;
	1798	+ __le16 reserved1;
1637	1799
1638		- uint16_t dseg_count;
1639		- uint16_t reserved2[3];
	1800	+ __le16 dseg_count;
	1801	+ __le16 reserved2[3];
1640	1802
1641		- uint32_t parameter1;
1642		- uint32_t parameter2;
1643		- uint32_t parameter3;
	1803	+ __le32 parameter1;
	1804	+ __le32 parameter2;
	1805	+ __le32 parameter3;
1644	1806
1645		- uint32_t reserved3[3];
1646		- uint32_t total_byte_cnt;
1647		- uint32_t reserved4;
	1807	+ __le32 reserved3[3];
	1808	+ __le32 total_byte_cnt;
	1809	+ __le32 reserved4;
1648	1810
1649		- uint32_t dseg_address[2];
1650		- uint32_t dseg_length;
	1811	+ struct dsd64 dsd;
1651	1812	};
1652	1813
1653	1814	struct access_chip_rsp_84xx {
..	..	@@ -1658,11 +1819,11 @@
1658	1819
1659	1820	uint32_t handle;
1660	1821
1661		- uint16_t comp_status;
1662		- uint16_t failure_code;
1663		- uint32_t residual_count;
	1822	+ __le16 comp_status;
	1823	+ __le16 failure_code;
	1824	+ __le32 residual_count;
1664	1825
1665		- uint32_t reserved[12];
	1826	+ __le32 reserved[12];
1666	1827	};
1667	1828
1668	1829	/* 81XX Support **************************************************************/
..	..	@@ -1707,59 +1868,62 @@
1707	1868
1708	1869	/* LR Distance bit positions */
1709	1870	#define LR_DIST_NV_POS 2
	1871	+#define LR_DIST_NV_MASK 0xf
1710	1872	#define LR_DIST_FW_POS 12
1711		-#define LR_DIST_FW_SHIFT (LR_DIST_FW_POS - LR_DIST_NV_POS)
1712		-#define LR_DIST_FW_FIELD(x) ((x) << LR_DIST_FW_SHIFT & 0xf000)
	1873	+
	1874	+/* FAC semaphore defines */
	1875	+#define FAC_SEMAPHORE_UNLOCK 0
	1876	+#define FAC_SEMAPHORE_LOCK 1
1713	1877
1714	1878	struct nvram_81xx {
1715	1879	/* NVRAM header. */
1716	1880	uint8_t id[4];
1717		- uint16_t nvram_version;
1718		- uint16_t reserved_0;
	1881	+ __le16 nvram_version;
	1882	+ __le16 reserved_0;
1719	1883
1720	1884	/* Firmware Initialization Control Block. */
1721		- uint16_t version;
1722		- uint16_t reserved_1;
1723		- uint16_t frame_payload_size;
1724		- uint16_t execution_throttle;
1725		- uint16_t exchange_count;
1726		- uint16_t reserved_2;
	1885	+ __le16 version;
	1886	+ __le16 reserved_1;
	1887	+ __le16 frame_payload_size;
	1888	+ __le16 execution_throttle;
	1889	+ __le16 exchange_count;
	1890	+ __le16 reserved_2;
1727	1891
1728	1892	uint8_t port_name[WWN_SIZE];
1729	1893	uint8_t node_name[WWN_SIZE];
1730	1894
1731		- uint16_t login_retry_count;
1732		- uint16_t reserved_3;
1733		- uint16_t interrupt_delay_timer;
1734		- uint16_t login_timeout;
	1895	+ __le16 login_retry_count;
	1896	+ __le16 reserved_3;
	1897	+ __le16 interrupt_delay_timer;
	1898	+ __le16 login_timeout;
1735	1899
1736		- uint32_t firmware_options_1;
1737		- uint32_t firmware_options_2;
1738		- uint32_t firmware_options_3;
	1900	+ __le32 firmware_options_1;
	1901	+ __le32 firmware_options_2;
	1902	+ __le32 firmware_options_3;
1739	1903
1740		- uint16_t reserved_4[4];
	1904	+ __le16 reserved_4[4];
1741	1905
1742	1906	/* Offset 64. */
1743	1907	uint8_t enode_mac[6];
1744		- uint16_t reserved_5[5];
	1908	+ __le16 reserved_5[5];
1745	1909
1746	1910	/* Offset 80. */
1747		- uint16_t reserved_6[24];
	1911	+ __le16 reserved_6[24];
1748	1912
1749	1913	/* Offset 128. */
1750		- uint16_t ex_version;
	1914	+ __le16 ex_version;
1751	1915	uint8_t prio_fcf_matching_flags;
1752	1916	uint8_t reserved_6_1[3];
1753		- uint16_t pri_fcf_vlan_id;
	1917	+ __le16 pri_fcf_vlan_id;
1754	1918	uint8_t pri_fcf_fabric_name[8];
1755		- uint16_t reserved_6_2[7];
	1919	+ __le16 reserved_6_2[7];
1756	1920	uint8_t spma_mac_addr[6];
1757		- uint16_t reserved_6_3[14];
	1921	+ __le16 reserved_6_3[14];
1758	1922
1759	1923	/* Offset 192. */
1760		- uint8_t min_link_speed;
	1924	+ uint8_t min_supported_speed;
1761	1925	uint8_t reserved_7_0;
1762		- uint16_t reserved_7[31];
	1926	+ __le16 reserved_7[31];
1763	1927
1764	1928	/*
1765	1929	* BIT 0 = Enable spinup delay
..	..	@@ -1792,26 +1956,26 @@
1792	1956	* BIT 25 = Temp WWPN
1793	1957	* BIT 26-31 =
1794	1958	*/
1795		- uint32_t host_p;
	1959	+ __le32 host_p;
1796	1960
1797	1961	uint8_t alternate_port_name[WWN_SIZE];
1798	1962	uint8_t alternate_node_name[WWN_SIZE];
1799	1963
1800	1964	uint8_t boot_port_name[WWN_SIZE];
1801		- uint16_t boot_lun_number;
1802		- uint16_t reserved_8;
	1965	+ __le16 boot_lun_number;
	1966	+ __le16 reserved_8;
1803	1967
1804	1968	uint8_t alt1_boot_port_name[WWN_SIZE];
1805		- uint16_t alt1_boot_lun_number;
1806		- uint16_t reserved_9;
	1969	+ __le16 alt1_boot_lun_number;
	1970	+ __le16 reserved_9;
1807	1971
1808	1972	uint8_t alt2_boot_port_name[WWN_SIZE];
1809		- uint16_t alt2_boot_lun_number;
1810		- uint16_t reserved_10;
	1973	+ __le16 alt2_boot_lun_number;
	1974	+ __le16 reserved_10;
1811	1975
1812	1976	uint8_t alt3_boot_port_name[WWN_SIZE];
1813		- uint16_t alt3_boot_lun_number;
1814		- uint16_t reserved_11;
	1977	+ __le16 alt3_boot_lun_number;
	1978	+ __le16 reserved_11;
1815	1979
1816	1980	/*
1817	1981	* BIT 0 = Selective Login
..	..	@@ -1823,60 +1987,63 @@
1823	1987	* BIT 6 = Reserved
1824	1988	* BIT 7-31 =
1825	1989	*/
1826		- uint32_t efi_parameters;
	1990	+ __le32 efi_parameters;
1827	1991
1828	1992	uint8_t reset_delay;
1829	1993	uint8_t reserved_12;
1830		- uint16_t reserved_13;
	1994	+ __le16 reserved_13;
1831	1995
1832		- uint16_t boot_id_number;
1833		- uint16_t reserved_14;
	1996	+ __le16 boot_id_number;
	1997	+ __le16 reserved_14;
1834	1998
1835		- uint16_t max_luns_per_target;
1836		- uint16_t reserved_15;
	1999	+ __le16 max_luns_per_target;
	2000	+ __le16 reserved_15;
1837	2001
1838		- uint16_t port_down_retry_count;
1839		- uint16_t link_down_timeout;
	2002	+ __le16 port_down_retry_count;
	2003	+ __le16 link_down_timeout;
1840	2004
1841	2005	/* FCode parameters. */
1842		- uint16_t fcode_parameter;
	2006	+ __le16 fcode_parameter;
1843	2007
1844		- uint16_t reserved_16[3];
	2008	+ __le16 reserved_16[3];
1845	2009
1846	2010	/* Offset 352. */
1847	2011	uint8_t reserved_17[4];
1848		- uint16_t reserved_18[5];
	2012	+ __le16 reserved_18[5];
1849	2013	uint8_t reserved_19[2];
1850		- uint16_t reserved_20[8];
	2014	+ __le16 reserved_20[8];
1851	2015
1852	2016	/* Offset 384. */
1853	2017	uint8_t reserved_21[16];
1854		- uint16_t reserved_22[3];
	2018	+ __le16 reserved_22[3];
1855	2019
1856	2020	/* Offset 406 (0x196) Enhanced Features
1857	2021	* BIT 0 = Extended BB credits for LR
1858	2022	* BIT 1 = Virtual Fabric Enable
1859	2023	* BIT 2-5 = Distance Support if BIT 0 is on
1860		- * BIT 6-15 = Unused
	2024	+ * BIT 6 = Prefer FCP
	2025	+ * BIT 7 = SCM Disabled if BIT is set (1)
	2026	+ * BIT 8-15 = Unused
1861	2027	*/
1862	2028	uint16_t enhanced_features;
	2029	+
1863	2030	uint16_t reserved_24[4];
1864	2031
1865	2032	/* Offset 416. */
1866		- uint16_t reserved_25[32];
	2033	+ __le16 reserved_25[32];
1867	2034
1868	2035	/* Offset 480. */
1869	2036	uint8_t model_name[16];
1870	2037
1871	2038	/* Offset 496. */
1872		- uint16_t feature_mask_l;
1873		- uint16_t feature_mask_h;
1874		- uint16_t reserved_26[2];
	2039	+ __le16 feature_mask_l;
	2040	+ __le16 feature_mask_h;
	2041	+ __le16 reserved_26[2];
1875	2042
1876		- uint16_t subsystem_vendor_id;
1877		- uint16_t subsystem_device_id;
	2043	+ __le16 subsystem_vendor_id;
	2044	+ __le16 subsystem_device_id;
1878	2045
1879		- uint32_t checksum;
	2046	+ __le32 checksum;
1880	2047	};
1881	2048
1882	2049	/*
..	..	@@ -1885,44 +2052,44 @@
1885	2052	*/
1886	2053	#define ICB_VERSION 1
1887	2054	struct init_cb_81xx {
1888		- uint16_t version;
1889		- uint16_t reserved_1;
	2055	+ __le16 version;
	2056	+ __le16 reserved_1;
1890	2057
1891		- uint16_t frame_payload_size;
1892		- uint16_t execution_throttle;
1893		- uint16_t exchange_count;
	2058	+ __le16 frame_payload_size;
	2059	+ __le16 execution_throttle;
	2060	+ __le16 exchange_count;
1894	2061
1895		- uint16_t reserved_2;
	2062	+ __le16 reserved_2;
1896	2063
1897	2064	uint8_t port_name[WWN_SIZE]; /* Big endian. */
1898	2065	uint8_t node_name[WWN_SIZE]; /* Big endian. */
1899	2066
1900		- uint16_t response_q_inpointer;
1901		- uint16_t request_q_outpointer;
	2067	+ __le16 response_q_inpointer;
	2068	+ __le16 request_q_outpointer;
1902	2069
1903		- uint16_t login_retry_count;
	2070	+ __le16 login_retry_count;
1904	2071
1905		- uint16_t prio_request_q_outpointer;
	2072	+ __le16 prio_request_q_outpointer;
1906	2073
1907		- uint16_t response_q_length;
1908		- uint16_t request_q_length;
	2074	+ __le16 response_q_length;
	2075	+ __le16 request_q_length;
1909	2076
1910		- uint16_t reserved_3;
	2077	+ __le16 reserved_3;
1911	2078
1912		- uint16_t prio_request_q_length;
	2079	+ __le16 prio_request_q_length;
1913	2080
1914		- uint32_t request_q_address[2];
1915		- uint32_t response_q_address[2];
1916		- uint32_t prio_request_q_address[2];
	2081	+ __le64 request_q_address __packed;
	2082	+ __le64 response_q_address __packed;
	2083	+ __le64 prio_request_q_address __packed;
1917	2084
1918	2085	uint8_t reserved_4[8];
1919	2086
1920		- uint16_t atio_q_inpointer;
1921		- uint16_t atio_q_length;
1922		- uint32_t atio_q_address[2];
	2087	+ __le16 atio_q_inpointer;
	2088	+ __le16 atio_q_length;
	2089	+ __le64 atio_q_address __packed;
1923	2090
1924		- uint16_t interrupt_delay_timer; /* 100us increments. */
1925		- uint16_t login_timeout;
	2091	+ __le16 interrupt_delay_timer; /* 100us increments. */
	2092	+ __le16 login_timeout;
1926	2093
1927	2094	/*
1928	2095	* BIT 0-3 = Reserved
..	..	@@ -1935,7 +2102,7 @@
1935	2102	* BIT 14 = Node Name Option
1936	2103	* BIT 15-31 = Reserved
1937	2104	*/
1938		- uint32_t firmware_options_1;
	2105	+ __le32 firmware_options_1;
1939	2106
1940	2107	/*
1941	2108	* BIT 0 = Operation Mode bit 0
..	..	@@ -1953,7 +2120,7 @@
1953	2120	* BIT 14 = Enable Target PRLI Control
1954	2121	* BIT 15-31 = Reserved
1955	2122	*/
1956		- uint32_t firmware_options_2;
	2123	+ __le32 firmware_options_2;
1957	2124
1958	2125	/*
1959	2126	* BIT 0-3 = Reserved
..	..	@@ -1974,7 +2141,7 @@
1974	2141	* BIT 28 = SPMA selection bit 1
1975	2142	* BIT 30-31 = Reserved
1976	2143	*/
1977		- uint32_t firmware_options_3;
	2144	+ __le32 firmware_options_3;
1978	2145
1979	2146	uint8_t reserved_5[8];
1980	2147
..	..	@@ -2005,6 +2172,8 @@
2005	2172
2006	2173	#define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
2007	2174	#define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
	2175	+#define FARX_ACCESS_FLASH_CONF_28XX 0x7FFD0000
	2176	+#define FARX_ACCESS_FLASH_DATA_28XX 0x7F7D0000
2008	2177
2009	2178	/* FCP priority config defines *************************************/
2010	2179	/* operations */
..	..	@@ -2050,9 +2219,9 @@
2050	2219	#define FCP_PRIO_ATTR_ENABLE 0x1
2051	2220	#define FCP_PRIO_ATTR_PERSIST 0x2
2052	2221	uint8_t reserved; /* Reserved for future use */
2053		-#define FCP_PRIO_CFG_HDR_SIZE 0x10
2054		- struct qla_fcp_prio_entry entry[1]; /* fcp priority entries */
2055		-#define FCP_PRIO_CFG_ENTRY_SIZE 0x20
	2222	+#define FCP_PRIO_CFG_HDR_SIZE offsetof(struct qla_fcp_prio_cfg, entry)
	2223	+ struct qla_fcp_prio_entry entry[1023]; /* fcp priority entries */
	2224	+ uint8_t reserved2[16];
2056	2225	};
2057	2226
2058	2227	#define FCP_PRIO_CFG_SIZE (321024) / fcp prio data per port*/
..	..	@@ -2079,6 +2248,9 @@
2079	2248	#define FA_NPIV_CONF1_ADDR_81 0xD2000
2080	2249
2081	2250	/* 83XX Flash locations -- occupies second 8MB region. */
2082		-#define FA_FLASH_LAYOUT_ADDR_83 0xFC400
	2251	+#define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
	2252	+#define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
	2253	+
	2254	+#define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196
2083	2255
2084	2256	#endif