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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/scsi/megaraid/megaraid_sas.h
....@@ -1,32 +1,18 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  *  Linux MegaRAID driver for SAS based RAID controllers
34  *
45  *  Copyright (c) 2003-2013  LSI Corporation
5
- *  Copyright (c) 2013-2014  Avago Technologies
6
- *
7
- *  This program is free software; you can redistribute it and/or
8
- *  modify it under the terms of the GNU General Public License
9
- *  as published by the Free Software Foundation; either version 2
10
- *  of the License, or (at your option) any later version.
11
- *
12
- *  This program is distributed in the hope that it will be useful,
13
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
14
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
- *  GNU General Public License for more details.
16
- *
17
- *  You should have received a copy of the GNU General Public License
18
- *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
6
+ *  Copyright (c) 2013-2016  Avago Technologies
7
+ *  Copyright (c) 2016-2018  Broadcom Inc.
198  *
209  *  FILE: megaraid_sas.h
2110  *
22
- *  Authors: Avago Technologies
23
- *           Kashyap Desai <kashyap.desai@avagotech.com>
24
- *           Sumit Saxena <sumit.saxena@avagotech.com>
11
+ *  Authors: Broadcom Inc.
12
+ *           Kashyap Desai <kashyap.desai@broadcom.com>
13
+ *           Sumit Saxena <sumit.saxena@broadcom.com>
2514  *
26
- *  Send feedback to: megaraidlinux.pdl@avagotech.com
27
- *
28
- *  Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29
- *  San Jose, California 95131
15
+ *  Send feedback to: megaraidlinux.pdl@broadcom.com
3016  */
3117 
3218 #ifndef LSI_MEGARAID_SAS_H
....@@ -35,8 +21,10 @@
3521 /*
3622  * MegaRAID SAS Driver meta data
3723  */
38
-#define MEGASAS_VERSION				"07.706.03.00-rc1"
39
-#define MEGASAS_RELDATE				"May 21, 2018"
24
+#define MEGASAS_VERSION				"07.714.04.00-rc1"
25
+#define MEGASAS_RELDATE				"Apr 14, 2020"
26
+
27
+#define MEGASAS_MSIX_NAME_LEN			32
4028 
4129 /*
4230  * Device IDs
....@@ -62,6 +50,14 @@
6250 #define PCI_DEVICE_ID_LSI_TOMCAT		    0x0017
6351 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT		0x001B
6452 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT	0x001C
53
+#define PCI_DEVICE_ID_LSI_AERO_10E1		0x10e1
54
+#define PCI_DEVICE_ID_LSI_AERO_10E2		0x10e2
55
+#define PCI_DEVICE_ID_LSI_AERO_10E5		0x10e5
56
+#define PCI_DEVICE_ID_LSI_AERO_10E6		0x10e6
57
+#define PCI_DEVICE_ID_LSI_AERO_10E0		0x10e0
58
+#define PCI_DEVICE_ID_LSI_AERO_10E3		0x10e3
59
+#define PCI_DEVICE_ID_LSI_AERO_10E4		0x10e4
60
+#define PCI_DEVICE_ID_LSI_AERO_10E7		0x10e7
6561 
6662 /*
6763  * Intel HBA SSDIDs
....@@ -133,6 +129,8 @@
133129 #define MFI_RESET_ADAPTER			0x00000002
134130 #define MEGAMFI_FRAME_SIZE			64
135131 
132
+#define MFI_STATE_FAULT_CODE			0x0FFF0000
133
+#define MFI_STATE_FAULT_SUBCODE			0x0000FF00
136134 /*
137135  * During FW init, clear pending cmds & reset state using inbound_msg_0
138136  *
....@@ -142,6 +140,7 @@
142140  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
143141  * HOTPLUG	: Resume from Hotplug
144142  * MFI_STOP_ADP	: Send signal to FW to stop processing
143
+ * MFI_ADP_TRIGGER_SNAP_DUMP: Inform firmware to initiate snap dump
145144  */
146145 #define WRITE_SEQUENCE_OFFSET		(0x0000000FC) /* I20 */
147146 #define HOST_DIAGNOSTIC_OFFSET		(0x000000F8)  /* I20 */
....@@ -158,6 +157,7 @@
158157 #define MFI_RESET_FLAGS				MFI_INIT_READY| \
159158 						MFI_INIT_MFIMODE| \
160159 						MFI_INIT_ABORT
160
+#define MFI_ADP_TRIGGER_SNAP_DUMP		0x00000100
161161 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
162162 
163163 /*
....@@ -198,6 +198,7 @@
198198 	MFI_CMD_SMP		= 0x7,
199199 	MFI_CMD_STP		= 0x8,
200200 	MFI_CMD_NVME		= 0x9,
201
+	MFI_CMD_TOOLBOX		= 0xa,
201202 	MFI_CMD_OP_COUNT,
202203 	MFI_CMD_INVALID		= 0xff
203204 };
....@@ -510,7 +511,7 @@
510511  */
511512 struct MR_PD_PROGRESS {
512513 	struct {
513
-#ifndef MFI_BIG_ENDIAN
514
+#ifndef __BIG_ENDIAN_BITFIELD
514515 		u32     rbld:1;
515516 		u32     patrol:1;
516517 		u32     clear:1;
....@@ -536,7 +537,7 @@
536537 	};
537538 
538539 	struct {
539
-#ifndef MFI_BIG_ENDIAN
540
+#ifndef __BIG_ENDIAN_BITFIELD
540541 		u32     rbld:1;
541542 		u32     patrol:1;
542543 		u32     clear:1;
....@@ -786,6 +787,38 @@
786787 	u8	targetId[MAX_LOGICAL_DRIVES_EXT];
787788 };
788789 
790
+struct MR_HOST_DEVICE_LIST_ENTRY {
791
+	struct {
792
+		union {
793
+			struct {
794
+#if defined(__BIG_ENDIAN_BITFIELD)
795
+				u8 reserved:7;
796
+				u8 is_sys_pd:1;
797
+#else
798
+				u8 is_sys_pd:1;
799
+				u8 reserved:7;
800
+#endif
801
+			} bits;
802
+			u8 byte;
803
+		} u;
804
+	} flags;
805
+	u8 scsi_type;
806
+	__le16 target_id;
807
+	u8 reserved[4];
808
+	__le64 sas_addr[2];
809
+} __packed;
810
+
811
+struct MR_HOST_DEVICE_LIST {
812
+	__le32			size;
813
+	__le32			count;
814
+	__le32			reserved[2];
815
+	struct MR_HOST_DEVICE_LIST_ENTRY	host_device_list[1];
816
+} __packed;
817
+
818
+#define HOST_DEVICE_LIST_SZ (sizeof(struct MR_HOST_DEVICE_LIST) +	       \
819
+			      (sizeof(struct MR_HOST_DEVICE_LIST_ENTRY) *      \
820
+			      (MEGASAS_MAX_PD + MAX_LOGICAL_DRIVES_EXT - 1)))
821
+
789822 
790823 /*
791824  * SAS controller properties
....@@ -860,8 +893,26 @@
860893 		u32     reserved:18;
861894 #endif
862895 	} OnOffProperties;
863
-	u8 autoSnapVDSpace;
864
-	u8 viewSpace;
896
+
897
+	union {
898
+		u8 autoSnapVDSpace;
899
+		u8 viewSpace;
900
+		struct {
901
+#if   defined(__BIG_ENDIAN_BITFIELD)
902
+			u16 reserved3:9;
903
+			u16 enable_fw_dev_list:1;
904
+			u16 reserved2:1;
905
+			u16 enable_snap_dump:1;
906
+			u16 reserved1:4;
907
+#else
908
+			u16 reserved1:4;
909
+			u16 enable_snap_dump:1;
910
+			u16 reserved2:1;
911
+			u16 enable_fw_dev_list:1;
912
+			u16 reserved3:9;
913
+#endif
914
+		} on_off_properties2;
915
+	};
865916 	__le16 spinDownTime;
866917 	u8  reserved[24];
867918 } __packed;
....@@ -1407,7 +1458,39 @@
14071458 
14081459 	u8 reserved6[64];
14091460 
1410
-	u32 rsvdForAdptOp[64];
1461
+	struct {
1462
+	#if defined(__BIG_ENDIAN_BITFIELD)
1463
+		u32 reserved:19;
1464
+		u32 support_pci_lane_margining: 1;
1465
+		u32 support_psoc_update:1;
1466
+		u32 support_force_personality_change:1;
1467
+		u32 support_fde_type_mix:1;
1468
+		u32 support_snap_dump:1;
1469
+		u32 support_nvme_tm:1;
1470
+		u32 support_oce_only:1;
1471
+		u32 support_ext_mfg_vpd:1;
1472
+		u32 support_pcie:1;
1473
+		u32 support_cvhealth_info:1;
1474
+		u32 support_profile_change:2;
1475
+		u32 mr_config_ext2_supported:1;
1476
+	#else
1477
+		u32 mr_config_ext2_supported:1;
1478
+		u32 support_profile_change:2;
1479
+		u32 support_cvhealth_info:1;
1480
+		u32 support_pcie:1;
1481
+		u32 support_ext_mfg_vpd:1;
1482
+		u32 support_oce_only:1;
1483
+		u32 support_nvme_tm:1;
1484
+		u32 support_snap_dump:1;
1485
+		u32 support_fde_type_mix:1;
1486
+		u32 support_force_personality_change:1;
1487
+		u32 support_psoc_update:1;
1488
+		u32 support_pci_lane_margining: 1;
1489
+		u32 reserved:19;
1490
+	#endif
1491
+	} adapter_operations5;
1492
+
1493
+	u32 rsvdForAdptOp[63];
14111494 
14121495 	u8 reserved7[3];
14131496 
....@@ -1434,6 +1517,8 @@
14341517 #define MEGASAS_MAX_LD_IDS			(MEGASAS_MAX_LD_CHANNELS * \
14351518 						MEGASAS_MAX_DEV_PER_CHANNEL)
14361519 
1520
+#define MEGASAS_MAX_SUPPORTED_LD_IDS		240
1521
+
14371522 #define MEGASAS_MAX_SECTORS                    (2*1024)
14381523 #define MEGASAS_MAX_SECTORS_IEEE		(2*128)
14391524 #define MEGASAS_DBG_LVL				1
....@@ -1441,7 +1526,9 @@
14411526 #define MEGASAS_FW_BUSY				1
14421527 
14431528 /* Driver's internal Logging levels*/
1444
-#define OCR_LOGS    (1 << 0)
1529
+#define OCR_DEBUG    (1 << 0)
1530
+#define TM_DEBUG     (1 << 1)
1531
+#define LD_PD_DEBUG    (1 << 2)
14451532 
14461533 #define SCAN_PD_CHANNEL	0x1
14471534 #define SCAN_VD_CHANNEL	0x2
....@@ -1485,7 +1572,6 @@
14851572 #define MEGASAS_IOCTL_CMD			0
14861573 #define MEGASAS_DEFAULT_CMD_TIMEOUT		90
14871574 #define MEGASAS_THROTTLE_QUEUE_DEPTH		16
1488
-#define MEGASAS_BLOCKED_CMD_TIMEOUT		60
14891575 #define MEGASAS_DEFAULT_TM_TIMEOUT		50
14901576 /*
14911577  * FW reports the maximum of number of commands that it can accept (maximum
....@@ -1518,6 +1604,7 @@
15181604 #define MFI_IO_TIMEOUT_SECS			180
15191605 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF	(5 * HZ)
15201606 #define MEGASAS_OCR_SETTLE_TIME_VF		(1000 * 30)
1607
+#define MEGASAS_SRIOV_MAX_RESET_TRIES_VF	1
15211608 #define MEGASAS_ROUTINE_WAIT_TIME_VF		300
15221609 #define MFI_REPLY_1078_MESSAGE_INTERRUPT	0x80000000
15231610 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT	0x00000001
....@@ -1542,13 +1629,21 @@
15421629 
15431630 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET		0X01000000
15441631 
1632
+#define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET	(1 << 24)
1633
+
15451634 #define MR_CAN_HANDLE_64_BIT_DMA_OFFSET		(1 << 25)
1635
+#define MR_INTR_COALESCING_SUPPORT_OFFSET	(1 << 26)
1636
+
1637
+#define MEGASAS_WATCHDOG_THREAD_INTERVAL	1000
1638
+#define MEGASAS_WAIT_FOR_NEXT_DMA_MSECS		20
1639
+#define MEGASAS_WATCHDOG_WAIT_COUNT		50
15461640 
15471641 enum MR_ADAPTER_TYPE {
15481642 	MFI_SERIES = 1,
15491643 	THUNDERBOLT_SERIES = 2,
15501644 	INVADER_SERIES = 3,
15511645 	VENTURA_SERIES = 4,
1646
+	AERO_SERIES = 5,
15521647 };
15531648 
15541649 /*
....@@ -1588,11 +1683,10 @@
15881683 
15891684 	u32 	reserved_3[3];			/*00A4h*/
15901685 
1591
-	u32 	outbound_scratch_pad ;		/*00B0h*/
1592
-	u32	outbound_scratch_pad_2;         /*00B4h*/
1593
-	u32	outbound_scratch_pad_3;         /*00B8h*/
1594
-	u32	outbound_scratch_pad_4;         /*00BCh*/
1595
-
1686
+	u32	outbound_scratch_pad_0;		/*00B0h*/
1687
+	u32	outbound_scratch_pad_1;         /*00B4h*/
1688
+	u32	outbound_scratch_pad_2;         /*00B8h*/
1689
+	u32	outbound_scratch_pad_3;         /*00BCh*/
15961690 
15971691 	u32 	inbound_low_queue_port ;	/*00C0h*/
15981692 
....@@ -1664,7 +1758,8 @@
16641758 typedef union _MFI_CAPABILITIES {
16651759 	struct {
16661760 #if   defined(__BIG_ENDIAN_BITFIELD)
1667
-	u32     reserved:17;
1761
+	u32     reserved:16;
1762
+	u32	support_fw_exposed_dev_list:1;
16681763 	u32	support_nvme_passthru:1;
16691764 	u32     support_64bit_mode:1;
16701765 	u32 support_pd_map_target_id:1;
....@@ -1696,7 +1791,8 @@
16961791 	u32	support_pd_map_target_id:1;
16971792 	u32     support_64bit_mode:1;
16981793 	u32	support_nvme_passthru:1;
1699
-	u32     reserved:17;
1794
+	u32	support_fw_exposed_dev_list:1;
1795
+	u32     reserved:16;
17001796 #endif
17011797 	} mfi_capabilities;
17021798 	__le32		reg;
....@@ -1715,7 +1811,7 @@
17151811 	__le32 pad_0;		/*0Ch */
17161812 
17171813 	__le16 flags;		/*10h */
1718
-	__le16 reserved_3;		/*12h */
1814
+	__le16 replyqueue_mask;		/*12h */
17191815 	__le32 data_xfer_len;	/*14h */
17201816 
17211817 	__le32 queue_info_new_phys_addr_lo;	/*18h */
....@@ -2111,8 +2207,13 @@
21112207 };
21122208 
21132209 struct megasas_irq_context {
2210
+	char name[MEGASAS_MSIX_NAME_LEN];
21142211 	struct megasas_instance *instance;
21152212 	u32 MSIxIndex;
2213
+	u32 os_irq;
2214
+	struct irq_poll irqpoll;
2215
+	bool irq_poll_scheduled;
2216
+	bool irq_line_enable;
21162217 };
21172218 
21182219 struct MR_DRV_SYSTEM_INFO {
....@@ -2134,14 +2235,40 @@
21342235 
21352236 /* JBOD Queue depth definitions */
21362237 #define MEGASAS_SATA_QD	32
2137
-#define MEGASAS_SAS_QD	64
2238
+#define MEGASAS_SAS_QD 256
21382239 #define MEGASAS_DEFAULT_PD_QD	64
2139
-#define MEGASAS_NVME_QD		32
2240
+#define MEGASAS_NVME_QD        64
21402241 
21412242 #define MR_DEFAULT_NVME_PAGE_SIZE	4096
21422243 #define MR_DEFAULT_NVME_PAGE_SHIFT	12
21432244 #define MR_DEFAULT_NVME_MDTS_KB		128
21442245 #define MR_NVME_PAGE_SIZE_MASK		0x000000FF
2246
+
2247
+/*Aero performance parameters*/
2248
+#define MR_HIGH_IOPS_QUEUE_COUNT	8
2249
+#define MR_DEVICE_HIGH_IOPS_DEPTH	8
2250
+#define MR_HIGH_IOPS_BATCH_COUNT	16
2251
+
2252
+enum MR_PERF_MODE {
2253
+	MR_BALANCED_PERF_MODE		= 0,
2254
+	MR_IOPS_PERF_MODE		= 1,
2255
+	MR_LATENCY_PERF_MODE		= 2,
2256
+};
2257
+
2258
+#define MEGASAS_PERF_MODE_2STR(mode) \
2259
+		((mode) == MR_BALANCED_PERF_MODE ? "Balanced" : \
2260
+		 (mode) == MR_IOPS_PERF_MODE ? "IOPS" : \
2261
+		 (mode) == MR_LATENCY_PERF_MODE ? "Latency" : \
2262
+		 "Unknown")
2263
+
2264
+enum MEGASAS_LD_TARGET_ID_STATUS {
2265
+	LD_TARGET_ID_INITIAL,
2266
+	LD_TARGET_ID_ACTIVE,
2267
+	LD_TARGET_ID_DELETED,
2268
+};
2269
+
2270
+#define MEGASAS_TARGET_ID(sdev)						\
2271
+	(((sdev->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + sdev->id)
21452272 
21462273 struct megasas_instance {
21472274 
....@@ -2181,6 +2308,12 @@
21812308 	struct MR_LD_TARGETID_LIST *ld_targetid_list_buf;
21822309 	dma_addr_t ld_targetid_list_buf_h;
21832310 
2311
+	struct MR_HOST_DEVICE_LIST *host_device_list_buf;
2312
+	dma_addr_t host_device_list_buf_h;
2313
+
2314
+	struct MR_SNAPDUMP_PROPERTIES *snapdump_prop;
2315
+	dma_addr_t snapdump_prop_h;
2316
+
21842317 	void *crash_buf[MAX_CRASH_DUMP_SIZE];
21852318 	unsigned int    fw_crash_buffer_size;
21862319 	unsigned int    fw_crash_state;
....@@ -2193,13 +2326,17 @@
21932326 	u32 secure_jbod_support;
21942327 	u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
21952328 	bool use_seqnum_jbod_fp;   /* Added for PD sequence */
2196
-	spinlock_t crashdump_lock;
2329
+	bool smp_affinity_enable;
2330
+	struct mutex crashdump_lock;
21972331 
21982332 	struct megasas_register_set __iomem *reg_set;
21992333 	u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
22002334 	struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
22012335 	struct megasas_pd_list          local_pd_list[MEGASAS_MAX_PD];
22022336 	u8 ld_ids[MEGASAS_MAX_LD_IDS];
2337
+	u8 ld_tgtid_status[MEGASAS_MAX_LD_IDS];
2338
+	u8 ld_ids_prev[MEGASAS_MAX_LD_IDS];
2339
+	u8 ld_ids_from_raidmap[MEGASAS_MAX_LD_IDS];
22032340 	s8 init_id;
22042341 
22052342 	u16 max_num_sge;
....@@ -2210,6 +2347,7 @@
22102347 	u16 ldio_threshold;
22112348 	u16 cur_can_queue;
22122349 	u32 max_sectors_per_req;
2350
+	bool msix_load_balance;
22132351 	struct megasas_aen_event *ev;
22142352 
22152353 	struct megasas_cmd **cmd_list;
....@@ -2237,20 +2375,20 @@
22372375 	struct pci_dev *pdev;
22382376 	u32 unique_id;
22392377 	u32 fw_support_ieee;
2378
+	u32 threshold_reply_count;
22402379 
22412380 	atomic_t fw_outstanding;
22422381 	atomic_t ldio_outstanding;
22432382 	atomic_t fw_reset_no_pci_access;
2244
-	atomic_t ieee_sgl;
2245
-	atomic_t prp_sgl;
2246
-	atomic_t sge_holes_type1;
2247
-	atomic_t sge_holes_type2;
2248
-	atomic_t sge_holes_type3;
2383
+	atomic64_t total_io_count;
2384
+	atomic64_t high_iops_outstanding;
22492385 
22502386 	struct megasas_instance_template *instancet;
22512387 	struct tasklet_struct isr_tasklet;
22522388 	struct work_struct work_init;
2253
-	struct work_struct crash_init;
2389
+	struct delayed_work fw_fault_work;
2390
+	struct workqueue_struct *fw_fault_work_q;
2391
+	char fault_handler_work_q_name[48];
22542392 
22552393 	u8 flag;
22562394 	u8 unload;
....@@ -2308,9 +2446,22 @@
23082446 	u8 adapter_type;
23092447 	bool consistent_mask_64bit;
23102448 	bool support_nvme_passthru;
2449
+	bool enable_sdev_max_qd;
23112450 	u8 task_abort_tmo;
23122451 	u8 max_reset_tmo;
2452
+	u8 snapdump_wait_time;
2453
+#ifdef CONFIG_DEBUG_FS
2454
+	struct dentry *debugfs_root;
2455
+	struct dentry *raidmap_dump;
2456
+#endif
2457
+	u8 enable_fw_dev_list;
2458
+	bool atomic_desc_support;
2459
+	bool support_seqnum_jbod_fp;
2460
+	bool support_pci_lane_margining;
2461
+	u8  low_latency_index_start;
2462
+	int perf_mode;
23132463 };
2464
+
23142465 struct MR_LD_VF_MAP {
23152466 	u32 size;
23162467 	union MR_LD_REF ref;
....@@ -2386,9 +2537,9 @@
23862537 	void (*enable_intr)(struct megasas_instance *);
23872538 	void (*disable_intr)(struct megasas_instance *);
23882539 
2389
-	int (*clear_intr)(struct megasas_register_set __iomem *);
2540
+	int (*clear_intr)(struct megasas_instance *);
23902541 
2391
-	u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
2542
+	u32 (*read_fw_status_reg)(struct megasas_instance *);
23922543 	int (*adp_reset)(struct megasas_instance *, \
23932544 		struct megasas_register_set __iomem *);
23942545 	int (*check_reset)(struct megasas_instance *, \
....@@ -2404,6 +2555,9 @@
24042555 
24052556 #define MEGASAS_IS_LOGICAL(sdev)					\
24062557 	((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2558
+
2559
+#define MEGASAS_IS_LUN_VALID(sdev)					\
2560
+	(((sdev)->lun == 0) ? 1 : 0)
24072561 
24082562 #define MEGASAS_DEV_INDEX(scp)						\
24092563 	(((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +	\
....@@ -2503,10 +2657,11 @@
25032657 };
25042658 
25052659 enum DCMD_RETURN_STATUS {
2506
-	DCMD_SUCCESS		= 0,
2507
-	DCMD_TIMEOUT		= 1,
2508
-	DCMD_FAILED		= 2,
2509
-	DCMD_NOT_FIRED		= 3,
2660
+	DCMD_SUCCESS    = 0x00,
2661
+	DCMD_TIMEOUT    = 0x01,
2662
+	DCMD_FAILED     = 0x02,
2663
+	DCMD_BUSY       = 0x03,
2664
+	DCMD_INIT       = 0xff,
25102665 };
25112666 
25122667 u8
....@@ -2535,11 +2690,11 @@
25352690 					   bool is_target_prop);
25362691 int megasas_get_target_prop(struct megasas_instance *instance,
25372692 			    struct scsi_device *sdev);
2693
+void megasas_get_snapdump_properties(struct megasas_instance *instance);
25382694 
25392695 int megasas_set_crash_dump_params(struct megasas_instance *instance,
25402696 	u8 crash_buf_state);
25412697 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2542
-void megasas_fusion_crash_dump_wq(struct work_struct *work);
25432698 
25442699 void megasas_return_cmd_fusion(struct megasas_instance *instance,
25452700 	struct megasas_cmd_fusion *cmd);
....@@ -2560,7 +2715,35 @@
25602715 u32 mega_mod64(u64 dividend, u32 divisor);
25612716 int megasas_alloc_fusion_context(struct megasas_instance *instance);
25622717 void megasas_free_fusion_context(struct megasas_instance *instance);
2718
+int megasas_fusion_start_watchdog(struct megasas_instance *instance);
2719
+void megasas_fusion_stop_watchdog(struct megasas_instance *instance);
2720
+
25632721 void megasas_set_dma_settings(struct megasas_instance *instance,
25642722 			      struct megasas_dcmd_frame *dcmd,
25652723 			      dma_addr_t dma_addr, u32 dma_len);
2724
+int megasas_adp_reset_wait_for_ready(struct megasas_instance *instance,
2725
+				     bool do_adp_reset,
2726
+				     int ocr_context);
2727
+int megasas_irqpoll(struct irq_poll *irqpoll, int budget);
2728
+void megasas_dump_fusion_io(struct scsi_cmnd *scmd);
2729
+u32 megasas_readl(struct megasas_instance *instance,
2730
+		  const volatile void __iomem *addr);
2731
+struct megasas_cmd *megasas_get_cmd(struct megasas_instance *instance);
2732
+void megasas_return_cmd(struct megasas_instance *instance,
2733
+			struct megasas_cmd *cmd);
2734
+int megasas_issue_polled(struct megasas_instance *instance,
2735
+			 struct megasas_cmd *cmd);
2736
+void megaraid_sas_kill_hba(struct megasas_instance *instance);
2737
+void megasas_check_and_restore_queue_depth(struct megasas_instance *instance);
2738
+void megasas_start_timer(struct megasas_instance *instance);
2739
+int megasas_sriov_start_heartbeat(struct megasas_instance *instance,
2740
+				  int initial);
2741
+int megasas_alloc_cmds(struct megasas_instance *instance);
2742
+void megasas_free_cmds(struct megasas_instance *instance);
2743
+
2744
+void megasas_init_debugfs(void);
2745
+void megasas_exit_debugfs(void);
2746
+void megasas_setup_debugfs(struct megasas_instance *instance);
2747
+void megasas_destroy_debugfs(struct megasas_instance *instance);
2748
+
25662749 #endif				/*LSI_MEGARAID_SAS_H */