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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/pinctrl/pinctrl-at91.c
....@@ -1,9 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * at91 pinctrl driver based on at91 pinmux core
34  *
45  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5
- *
6
- * Under GPLv2 only
76  */
87 
98 #include <linux/clk.h>
....@@ -16,7 +15,7 @@
1615 #include <linux/slab.h>
1716 #include <linux/interrupt.h>
1817 #include <linux/io.h>
19
-#include <linux/gpio.h>
18
+#include <linux/gpio/driver.h>
2019 #include <linux/pinctrl/machine.h>
2120 #include <linux/pinctrl/pinconf.h>
2221 #include <linux/pinctrl/pinctrl.h>
....@@ -59,11 +58,14 @@
5958 #define OUTPUT		(1 << 7)
6059 #define OUTPUT_VAL_SHIFT	8
6160 #define OUTPUT_VAL	(0x1 << OUTPUT_VAL_SHIFT)
61
+#define SLEWRATE_SHIFT	9
62
+#define SLEWRATE_MASK	0x1
63
+#define SLEWRATE	(SLEWRATE_MASK << SLEWRATE_SHIFT)
6264 #define DEBOUNCE	(1 << 16)
6365 #define DEBOUNCE_VAL_SHIFT	17
6466 #define DEBOUNCE_VAL	(0x3fff << DEBOUNCE_VAL_SHIFT)
6567 
66
-/**
68
+/*
6769  * These defines will translated the dt binding settings to our internal
6870  * settings. They are not necessarily the same value as the register setting.
6971  * The actual drive strength current of low, medium and high must be looked up
....@@ -72,10 +74,22 @@
7274  * DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
7375  * strength when there is no dt config for it.
7476  */
75
-#define DRIVE_STRENGTH_DEFAULT		(0 << DRIVE_STRENGTH_SHIFT)
76
-#define DRIVE_STRENGTH_LOW          (1 << DRIVE_STRENGTH_SHIFT)
77
-#define DRIVE_STRENGTH_MED          (2 << DRIVE_STRENGTH_SHIFT)
78
-#define DRIVE_STRENGTH_HI           (3 << DRIVE_STRENGTH_SHIFT)
77
+enum drive_strength_bit {
78
+	DRIVE_STRENGTH_BIT_DEF,
79
+	DRIVE_STRENGTH_BIT_LOW,
80
+	DRIVE_STRENGTH_BIT_MED,
81
+	DRIVE_STRENGTH_BIT_HI,
82
+};
83
+
84
+#define DRIVE_STRENGTH_BIT_MSK(name)	(DRIVE_STRENGTH_BIT_##name << \
85
+					 DRIVE_STRENGTH_SHIFT)
86
+
87
+enum slewrate_bit {
88
+	SLEWRATE_BIT_ENA,
89
+	SLEWRATE_BIT_DIS,
90
+};
91
+
92
+#define SLEWRATE_BIT_MSK(name)		(SLEWRATE_BIT_##name << SLEWRATE_SHIFT)
7993 
8094 /**
8195  * struct at91_pmx_func - describes AT91 pinmux functions
....@@ -147,6 +161,10 @@
147161  * @set_pulldown: enable/disable pulldown
148162  * @get_schmitt_trig: get schmitt trigger status
149163  * @disable_schmitt_trig: disable schmitt trigger
164
+ * @get_drivestrength: get driver strength
165
+ * @set_drivestrength: set driver strength
166
+ * @get_slewrate: get slew rate
167
+ * @set_slewrate: set slew rate
150168  * @irq_type: return irq type
151169  */
152170 struct at91_pinctrl_mux_ops {
....@@ -166,6 +184,8 @@
166184 	unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
167185 	void (*set_drivestrength)(void __iomem *pio, unsigned pin,
168186 					u32 strength);
187
+	unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
188
+	void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
169189 	/* irq */
170190 	int (*irq_type)(struct irq_data *d, unsigned type);
171191 };
....@@ -263,8 +283,8 @@
263283 	 */
264284 	grp = at91_pinctrl_find_group_by_name(info, np->name);
265285 	if (!grp) {
266
-		dev_err(info->dev, "unable to find group for node %s\n",
267
-			np->name);
286
+		dev_err(info->dev, "unable to find group for node %pOFn\n",
287
+			np);
268288 		return -EINVAL;
269289 	}
270290 
....@@ -551,7 +571,7 @@
551571 	/* SAMA5 strength is 1:1 with our defines,
552572 	 * except 0 is equivalent to low per datasheet */
553573 	if (!tmp)
554
-		tmp = DRIVE_STRENGTH_LOW;
574
+		tmp = DRIVE_STRENGTH_BIT_MSK(LOW);
555575 
556576 	return tmp;
557577 }
....@@ -564,9 +584,30 @@
564584 
565585 	/* strength is inverse in SAM9x5s hardware with the pinctrl defines
566586 	 * hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
567
-	tmp = DRIVE_STRENGTH_HI - tmp;
587
+	tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp;
568588 
569589 	return tmp;
590
+}
591
+
592
+static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio,
593
+						   unsigned pin)
594
+{
595
+	unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
596
+
597
+	if (tmp & BIT(pin))
598
+		return DRIVE_STRENGTH_BIT_HI;
599
+
600
+	return DRIVE_STRENGTH_BIT_LOW;
601
+}
602
+
603
+static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin)
604
+{
605
+	unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
606
+
607
+	if ((tmp & BIT(pin)))
608
+		return SLEWRATE_BIT_ENA;
609
+
610
+	return SLEWRATE_BIT_DIS;
570611 }
571612 
572613 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
....@@ -600,10 +641,49 @@
600641 
601642 	/* strength is inverse on SAM9x5s with our defines
602643 	 * 0 = hi, 1 = med, 2 = low, 3 = rsvd */
603
-	setting = DRIVE_STRENGTH_HI - setting;
644
+	setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting;
604645 
605646 	set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
606647 				setting);
648
+}
649
+
650
+static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin,
651
+					       u32 setting)
652
+{
653
+	unsigned int tmp;
654
+
655
+	if (setting <= DRIVE_STRENGTH_BIT_DEF ||
656
+	    setting == DRIVE_STRENGTH_BIT_MED ||
657
+	    setting > DRIVE_STRENGTH_BIT_HI)
658
+		return;
659
+
660
+	tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1);
661
+
662
+	/* Strength is 0: low, 1: hi */
663
+	if (setting == DRIVE_STRENGTH_BIT_LOW)
664
+		tmp &= ~BIT(pin);
665
+	else
666
+		tmp |= BIT(pin);
667
+
668
+	writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1);
669
+}
670
+
671
+static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin,
672
+					  u32 setting)
673
+{
674
+	unsigned int tmp;
675
+
676
+	if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS)
677
+		return;
678
+
679
+	tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR);
680
+
681
+	if (setting == SLEWRATE_BIT_DIS)
682
+		tmp &= ~BIT(pin);
683
+	else
684
+		tmp |= BIT(pin);
685
+
686
+	writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR);
607687 }
608688 
609689 static struct at91_pinctrl_mux_ops at91rm9200_ops = {
....@@ -631,6 +711,27 @@
631711 	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
632712 	.get_drivestrength = at91_mux_sam9x5_get_drivestrength,
633713 	.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
714
+	.irq_type	= alt_gpio_irq_type,
715
+};
716
+
717
+static const struct at91_pinctrl_mux_ops sam9x60_ops = {
718
+	.get_periph	= at91_mux_pio3_get_periph,
719
+	.mux_A_periph	= at91_mux_pio3_set_A_periph,
720
+	.mux_B_periph	= at91_mux_pio3_set_B_periph,
721
+	.mux_C_periph	= at91_mux_pio3_set_C_periph,
722
+	.mux_D_periph	= at91_mux_pio3_set_D_periph,
723
+	.get_deglitch	= at91_mux_pio3_get_deglitch,
724
+	.set_deglitch	= at91_mux_pio3_set_deglitch,
725
+	.get_debounce	= at91_mux_pio3_get_debounce,
726
+	.set_debounce	= at91_mux_pio3_set_debounce,
727
+	.get_pulldown	= at91_mux_pio3_get_pulldown,
728
+	.set_pulldown	= at91_mux_pio3_set_pulldown,
729
+	.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
730
+	.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
731
+	.get_drivestrength = at91_mux_sam9x60_get_drivestrength,
732
+	.set_drivestrength = at91_mux_sam9x60_set_drivestrength,
733
+	.get_slewrate   = at91_mux_sam9x60_get_slewrate,
734
+	.set_slewrate   = at91_mux_sam9x60_set_slewrate,
634735 	.irq_type	= alt_gpio_irq_type,
635736 };
636737 
....@@ -893,6 +994,8 @@
893994 	if (info->ops->get_drivestrength)
894995 		*config |= (info->ops->get_drivestrength(pio, pin)
895996 				<< DRIVE_STRENGTH_SHIFT);
997
+	if (info->ops->get_slewrate)
998
+		*config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT);
896999 	if (at91_mux_get_output(pio, pin, &out))
8971000 		*config |= OUTPUT | (out << OUTPUT_VAL_SHIFT);
8981001 
....@@ -944,6 +1047,9 @@
9441047 			info->ops->set_drivestrength(pio, pin,
9451048 				(config & DRIVE_STRENGTH)
9461049 					>> DRIVE_STRENGTH_SHIFT);
1050
+		if (info->ops->set_slewrate)
1051
+			info->ops->set_slewrate(pio, pin,
1052
+				(config & SLEWRATE) >> SLEWRATE_SHIFT);
9471053 
9481054 	} /* for each config */
9491055 
....@@ -959,11 +1065,11 @@
9591065 	}					\
9601066 } while (0)
9611067 
962
-#define DBG_SHOW_FLAG_MASKED(mask,flag) do {	\
1068
+#define DBG_SHOW_FLAG_MASKED(mask, flag, name) do { \
9631069 	if ((config & mask) == flag) {		\
9641070 		if (num_conf)			\
9651071 			seq_puts(s, "|");	\
966
-		seq_puts(s, #flag);		\
1072
+		seq_puts(s, #name);		\
9671073 		num_conf++;			\
9681074 	}					\
9691075 } while (0)
....@@ -981,9 +1087,13 @@
9811087 	DBG_SHOW_FLAG(PULL_DOWN);
9821088 	DBG_SHOW_FLAG(DIS_SCHMIT);
9831089 	DBG_SHOW_FLAG(DEGLITCH);
984
-	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
985
-	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
986
-	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
1090
+	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(LOW),
1091
+			     DRIVE_STRENGTH_LOW);
1092
+	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(MED),
1093
+			     DRIVE_STRENGTH_MED);
1094
+	DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_BIT_MSK(HI),
1095
+			     DRIVE_STRENGTH_HI);
1096
+	DBG_SHOW_FLAG(SLEWRATE);
9871097 	DBG_SHOW_FLAG(DEBOUNCE);
9881098 	if (config & DEBOUNCE) {
9891099 		val = config >> DEBOUNCE_VAL_SHIFT;
....@@ -1071,7 +1181,7 @@
10711181 	const __be32 *list;
10721182 	int i, j;
10731183 
1074
-	dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1184
+	dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
10751185 
10761186 	/* Initialise group */
10771187 	grp->name = np->name;
....@@ -1122,7 +1232,7 @@
11221232 	static u32 grp_index;
11231233 	u32 i = 0;
11241234 
1125
-	dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1235
+	dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
11261236 
11271237 	func = &info->functions[index];
11281238 
....@@ -1155,6 +1265,7 @@
11551265 	{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
11561266 	{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
11571267 	{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1268
+	{ .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
11581269 	{ /* sentinel */ }
11591270 };
11601271 
....@@ -1306,7 +1417,10 @@
13061417 	u32 osr;
13071418 
13081419 	osr = readl_relaxed(pio + PIO_OSR);
1309
-	return !(osr & mask);
1420
+	if (osr & mask)
1421
+		return GPIO_LINE_DIRECTION_OUT;
1422
+
1423
+	return GPIO_LINE_DIRECTION_IN;
13101424 }
13111425 
13121426 static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
....@@ -1375,14 +1489,11 @@
13751489 	int i;
13761490 	struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
13771491 	void __iomem *pio = at91_gpio->regbase;
1492
+	const char *gpio_label;
13781493 
1379
-	for (i = 0; i < chip->ngpio; i++) {
1494
+	for_each_requested_gpio(chip, i, gpio_label) {
13801495 		unsigned mask = pin_to_mask(i);
1381
-		const char *gpio_label;
13821496 
1383
-		gpio_label = gpiochip_is_requested(chip, i);
1384
-		if (!gpio_label)
1385
-			continue;
13861497 		mode = at91_gpio->ops->get_periph(pio, mask);
13871498 		seq_printf(s, "[%s] GPIO%s%d: ",
13881499 			   gpio_label, chip->label, i);
....@@ -1487,7 +1598,7 @@
14871598 		return 0;
14881599 	case IRQ_TYPE_NONE:
14891600 	default:
1490
-		pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
1601
+		pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq);
14911602 		return -EINVAL;
14921603 	}
14931604 
....@@ -1615,9 +1726,11 @@
16151726 	struct at91_gpio_chip   *prev = NULL;
16161727 	struct irq_data		*d = irq_get_irq_data(at91_gpio->pioc_virq);
16171728 	struct irq_chip		*gpio_irqchip;
1618
-	int ret, i;
1729
+	struct gpio_irq_chip	*girq;
1730
+	int i;
16191731 
1620
-	gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), GFP_KERNEL);
1732
+	gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip),
1733
+				    GFP_KERNEL);
16211734 	if (!gpio_irqchip)
16221735 		return -ENOMEM;
16231736 
....@@ -1639,33 +1752,30 @@
16391752 	 * handler will perform the actual work of handling the parent
16401753 	 * interrupt.
16411754 	 */
1642
-	ret = gpiochip_irqchip_add(&at91_gpio->chip,
1643
-				   gpio_irqchip,
1644
-				   0,
1645
-				   handle_edge_irq,
1646
-				   IRQ_TYPE_NONE);
1647
-	if (ret) {
1648
-		dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
1649
-			at91_gpio->pioc_idx);
1650
-		return ret;
1651
-	}
1755
+	girq = &at91_gpio->chip.irq;
1756
+	girq->chip = gpio_irqchip;
1757
+	girq->default_type = IRQ_TYPE_NONE;
1758
+	girq->handler = handle_edge_irq;
16521759 
1653
-	/* The top level handler handles one bank of GPIOs, except
1760
+	/*
1761
+	 * The top level handler handles one bank of GPIOs, except
16541762 	 * on some SoC it can handle up to three...
16551763 	 * We only set up the handler for the first of the list.
16561764 	 */
16571765 	gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq);
16581766 	if (!gpiochip_prev) {
1659
-		/* Then register the chain on the parent IRQ */
1660
-		gpiochip_set_chained_irqchip(&at91_gpio->chip,
1661
-					     gpio_irqchip,
1662
-					     at91_gpio->pioc_virq,
1663
-					     gpio_irq_handler);
1767
+		girq->parent_handler = gpio_irq_handler;
1768
+		girq->num_parents = 1;
1769
+		girq->parents = devm_kcalloc(&pdev->dev, 1,
1770
+					     sizeof(*girq->parents),
1771
+					     GFP_KERNEL);
1772
+		if (!girq->parents)
1773
+			return -ENOMEM;
1774
+		girq->parents[0] = at91_gpio->pioc_virq;
16641775 		return 0;
16651776 	}
16661777 
16671778 	prev = gpiochip_get_data(gpiochip_prev);
1668
-
16691779 	/* we can only have 2 banks before */
16701780 	for (i = 0; i < 2; i++) {
16711781 		if (prev->next) {
....@@ -1697,13 +1807,13 @@
16971807 static const struct of_device_id at91_gpio_of_match[] = {
16981808 	{ .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
16991809 	{ .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1810
+	{ .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
17001811 	{ /* sentinel */ }
17011812 };
17021813 
17031814 static int at91_gpio_probe(struct platform_device *pdev)
17041815 {
17051816 	struct device_node *np = pdev->dev.of_node;
1706
-	struct resource *res;
17071817 	struct at91_gpio_chip *at91_chip = NULL;
17081818 	struct gpio_chip *chip;
17091819 	struct pinctrl_gpio_range *range;
....@@ -1731,8 +1841,7 @@
17311841 		goto err;
17321842 	}
17331843 
1734
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1735
-	at91_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1844
+	at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0);
17361845 	if (IS_ERR(at91_chip->regbase)) {
17371846 		ret = PTR_ERR(at91_chip->regbase);
17381847 		goto err;
....@@ -1782,7 +1891,7 @@
17821891 	}
17831892 
17841893 	for (i = 0; i < chip->ngpio; i++)
1785
-		names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
1894
+		names[i] = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pio%c%d", alias_idx + 'A', i);
17861895 
17871896 	chip->names = (const char *const *)names;
17881897 
....@@ -1794,6 +1903,10 @@
17941903 	range->npins = chip->ngpio;
17951904 	range->gc = chip;
17961905 
1906
+	ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1907
+	if (ret)
1908
+		goto gpiochip_add_err;
1909
+
17971910 	ret = gpiochip_add_data(chip, at91_chip);
17981911 	if (ret)
17991912 		goto gpiochip_add_err;
....@@ -1801,16 +1914,10 @@
18011914 	gpio_chips[alias_idx] = at91_chip;
18021915 	gpio_banks = max(gpio_banks, alias_idx + 1);
18031916 
1804
-	ret = at91_gpio_of_irq_setup(pdev, at91_chip);
1805
-	if (ret)
1806
-		goto irq_setup_err;
1807
-
18081917 	dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
18091918 
18101919 	return 0;
18111920 
1812
-irq_setup_err:
1813
-	gpiochip_remove(chip);
18141921 gpiochip_add_err:
18151922 clk_enable_err:
18161923 	clk_disable_unprepare(at91_chip->clock);