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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * HiSilicon SoC L3C uncore Hardware event counters support |
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3 | 4 | * |
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.. | .. |
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6 | 7 | * Shaokun Zhang <zhangshaokun@hisilicon.com> |
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7 | 8 | * |
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8 | 9 | * This code is based on the uncore PMUs like arm-cci and arm-ccn. |
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9 | | - * |
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10 | | - * This program is free software; you can redistribute it and/or modify |
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11 | | - * it under the terms of the GNU General Public License version 2 as |
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12 | | - * published by the Free Software Foundation. |
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13 | 10 | */ |
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14 | 11 | #include <linux/acpi.h> |
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15 | 12 | #include <linux/bug.h> |
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.. | .. |
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209 | 206 | |
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210 | 207 | /* Read and init IRQ */ |
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211 | 208 | irq = platform_get_irq(pdev, 0); |
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212 | | - if (irq < 0) { |
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213 | | - dev_err(&pdev->dev, "L3C PMU get irq fail; irq:%d\n", irq); |
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| 209 | + if (irq < 0) |
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214 | 210 | return irq; |
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215 | | - } |
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216 | 211 | |
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217 | 212 | ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr, |
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218 | 213 | IRQF_NOBALANCING | IRQF_NO_THREAD, |
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.. | .. |
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238 | 233 | struct hisi_pmu *l3c_pmu) |
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239 | 234 | { |
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240 | 235 | unsigned long long id; |
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241 | | - struct resource *res; |
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242 | 236 | acpi_status status; |
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243 | 237 | |
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244 | 238 | status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev), |
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.. | .. |
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264 | 258 | return -EINVAL; |
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265 | 259 | } |
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266 | 260 | |
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267 | | - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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268 | | - l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res); |
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| 261 | + l3c_pmu->base = devm_platform_ioremap_resource(pdev, 0); |
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269 | 262 | if (IS_ERR(l3c_pmu->base)) { |
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270 | 263 | dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n"); |
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271 | 264 | return PTR_ERR(l3c_pmu->base); |
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.. | .. |
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387 | 380 | l3c_pmu->sccl_id, l3c_pmu->index_id); |
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388 | 381 | l3c_pmu->pmu = (struct pmu) { |
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389 | 382 | .name = name, |
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| 383 | + .module = THIS_MODULE, |
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390 | 384 | .task_ctx_nr = perf_invalid_context, |
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391 | 385 | .event_init = hisi_uncore_pmu_event_init, |
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392 | 386 | .pmu_enable = hisi_uncore_pmu_enable, |
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.. | .. |
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397 | 391 | .stop = hisi_uncore_pmu_stop, |
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398 | 392 | .read = hisi_uncore_pmu_read, |
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399 | 393 | .attr_groups = hisi_l3c_pmu_attr_groups, |
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| 394 | + .capabilities = PERF_PMU_CAP_NO_EXCLUDE, |
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400 | 395 | }; |
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401 | 396 | |
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402 | 397 | ret = perf_pmu_register(&l3c_pmu->pmu, name, -1); |
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403 | 398 | if (ret) { |
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404 | 399 | dev_err(l3c_pmu->dev, "L3C PMU register failed!\n"); |
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405 | | - cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE, |
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406 | | - &l3c_pmu->node); |
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| 400 | + cpuhp_state_remove_instance_nocalls( |
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| 401 | + CPUHP_AP_PERF_ARM_HISI_L3_ONLINE, &l3c_pmu->node); |
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| 402 | + irq_set_affinity_hint(l3c_pmu->irq, NULL); |
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407 | 403 | } |
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408 | 404 | |
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409 | 405 | return ret; |
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.. | .. |
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414 | 410 | struct hisi_pmu *l3c_pmu = platform_get_drvdata(pdev); |
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415 | 411 | |
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416 | 412 | perf_pmu_unregister(&l3c_pmu->pmu); |
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417 | | - cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE, |
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418 | | - &l3c_pmu->node); |
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| 413 | + cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE, |
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| 414 | + &l3c_pmu->node); |
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| 415 | + irq_set_affinity_hint(l3c_pmu->irq, NULL); |
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419 | 416 | |
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420 | 417 | return 0; |
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421 | 418 | } |
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.. | .. |
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424 | 421 | .driver = { |
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425 | 422 | .name = "hisi_l3c_pmu", |
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426 | 423 | .acpi_match_table = ACPI_PTR(hisi_l3c_pmu_acpi_match), |
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| 424 | + .suppress_bind_attrs = true, |
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427 | 425 | }, |
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428 | 426 | .probe = hisi_l3c_pmu_probe, |
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429 | 427 | .remove = hisi_l3c_pmu_remove, |
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