modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h
..
..
@@ -1,27 +1,5 @@
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-/******************************************************************************
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- *
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- * Copyright(c) 2009-2012  Realtek Corporation.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of version 2 of the GNU General Public License as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * The full GNU General Public License is included in this distribution in the
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- * file called LICENSE.
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- *
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- * Contact Information:
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- * wlanfae <wlanfae@realtek.com>
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- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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- * Hsinchu 300, Taiwan.
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- *
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- * Larry Finger <Larry.Finger@lwfinger.net>
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- *
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- *****************************************************************************/
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/* Copyright(c) 2009-2012  Realtek Corporation.*/
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3
 
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 #ifndef __RTL92D_REG_H__
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 #define __RTL92D_REG_H__
..
..
@@ -752,7 +730,7 @@
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730
 
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 /* SYS_FUNC_EN */
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 #define FEN_BBRSTB				BIT(0)
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-#define FEN_BB_GLB_RSTn				BIT(1)
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+#define FEN_BB_GLB_RSTN				BIT(1)
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 #define FEN_USBA				BIT(2)
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 #define FEN_UPLL				BIT(3)
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 #define FEN_USBD				BIT(4)
..
..
@@ -773,7 +751,7 @@
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 #define PFM_ALDN				BIT(1)
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 #define PFM_LDKP				BIT(2)
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 #define PFM_WOWL				BIT(3)
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-#define EnPDN					BIT(4)
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+#define ENPDN					BIT(4)
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 #define PDN_PL					BIT(5)
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 #define APFM_ONMAC				BIT(8)
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 #define APFM_OFF				BIT(9)
..
..
@@ -910,7 +888,7 @@
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 /* MCUFWDL  */
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 #define MCUFWDL_EN				BIT(0)
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 #define MCUFWDL_RDY				BIT(1)
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-#define FWDL_ChkSum_rpt				BIT(2)
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+#define FWDL_CHKSUM_RPT				BIT(2)
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 #define MACINI_RDY				BIT(3)
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 #define BBINI_RDY				BIT(4)
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 #define RFINI_RDY				BIT(5)
..
..
@@ -1033,7 +1011,7 @@
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 #define	RFPGA0_XA_LSSIPARAMETER			0x840
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 #define	RFPGA0_XB_LSSIPARAMETER			0x844
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-#define	RFPGA0_RFWAkEUPPARAMETER		0x850
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+#define	RFPGA0_RFWAKEUPPARAMETER		0x850
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 #define	RFPGA0_RFSLEEPUPPARAMETER		0x854
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1016
 
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 #define	RFPGA0_XAB_SWITCHCONTROL		0x858
..
..
@@ -1135,14 +1113,14 @@
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 #define	ROFDM0_AGCRSSITABLE			0xc78
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 #define	ROFDM0_HTSTFAGC				0xc7c
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1115
 
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-#define	ROFDM0_XATxIQIMBALANCE			0xc80
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-#define	ROFDM0_XATxAFE				0xc84
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-#define	ROFDM0_XBTxIQIMBALANCE			0xc88
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-#define	ROFDM0_XBTxAFE				0xc8c
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-#define	ROFDM0_XCTxIQIMBALANCE			0xc90
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-#define	ROFDM0_XCTxAFE				0xc94
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-#define	ROFDM0_XDTxIQIMBALANCE			0xc98
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-#define	ROFDM0_XDTxAFE				0xc9c
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+#define	ROFDM0_XATXIQIMBALANCE			0xc80
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+#define	ROFDM0_XATXAFE				0xc84
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+#define	ROFDM0_XBTXIQIMBALANCE			0xc88
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+#define	ROFDM0_XBTXAFE				0xc8c
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+#define	ROFDM0_XCTXIQIMBALANCE			0xc90
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+#define	ROFDM0_XCTXAFE				0xc94
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+#define	ROFDM0_XDTXIQIMBALANCE			0xc98
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+#define	ROFDM0_XDTXAFE				0xc9c
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 #define	ROFDM0_RXHPPARAMETER			0xce0
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 #define	ROFDM0_TXPSEUDONOISEWGT			0xce4
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@@ -1186,7 +1164,7 @@
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 #define	ROFDM_AGCREPORT				0xdd0
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 #define	ROFDM_RXSNR				0xdd4
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 #define	ROFDM_RXEVMCSI				0xdd8
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-#define	ROFDM_SIGReport				0xddc
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+#define	ROFDM_SIGREPORT				0xddc
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 /* 8. PageE(0xE00) */
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 #define	RTXAGC_A_RATE18_06			0xe00
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..
@@ -1228,7 +1206,7 @@
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 #define	RF_IPA					0x15
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 #define	RF_POW_ABILITY				0x17
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 #define	RF_MODE_AG				0x18
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-#define	rRfChannel				0x18
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+#define	rfchannel				0x18
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 #define	RF_CHNLBW				0x18
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 #define	RF_TOP					0x19
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