modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c
..
..
@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2012  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
25
3
 
26
4
 #include "../wifi.h"
27
5
 #include "../efuse.h"
..
..
@@ -124,12 +102,12 @@
124
102
 		*((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
125
103
 		break;
126
104
 	case HW_VAR_FWLPS_RF_ON:{
127
-		enum rf_pwrstate rfState;
105
+		enum rf_pwrstate rfstate;
128
106
 		u32 val_rcr;
129
107
 
130
108
 		rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
131
-					      (u8 *) (&rfState));
132
-		if (rfState == ERFOFF) {
109
+					      (u8 *)(&rfstate));
110
+		if (rfstate == ERFOFF) {
133
111
 			*((bool *) (val)) = true;
134
112
 		} else {
135
113
 			val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
..
..
@@ -226,8 +204,8 @@
226
204
 	case HW_VAR_SLOT_TIME: {
227
205
 		u8 e_aci;
228
206
 
229
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
230
-			 "HW_VAR_SLOT_TIME %x\n", val[0]);
207
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
208
+			"HW_VAR_SLOT_TIME %x\n", val[0]);
231
209
 		rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
232
210
 		for (e_aci = 0; e_aci < AC_MAX; e_aci++)
233
211
 			rtlpriv->cfg->ops->set_hw_reg(hw,
..
..
@@ -257,9 +235,9 @@
257
235
 			mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
258
236
 					      min_spacing_to_set);
259
237
 			*val = min_spacing_to_set;
260
-			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
261
-				 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
262
-				 mac->min_space_cfg);
238
+			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
239
+				"Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
240
+				mac->min_space_cfg);
263
241
 			rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
264
242
 				       mac->min_space_cfg);
265
243
 		}
..
..
@@ -271,32 +249,32 @@
271
249
 		density_to_set = *val;
272
250
 		mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
273
251
 		mac->min_space_cfg |= (density_to_set << 3);
274
-		RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
275
-			 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
276
-			 mac->min_space_cfg);
252
+		rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
253
+			"Set HW_VAR_SHORTGI_DENSITY: %#x\n",
254
+			mac->min_space_cfg);
277
255
 		rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
278
256
 			       mac->min_space_cfg);
279
257
 		break;
280
258
 	}
281
259
 	case HW_VAR_AMPDU_FACTOR: {
282
260
 		u8 factor_toset;
283
-		u32 regtoSet;
261
+		u32 regtoset;
284
262
 		u8 *ptmp_byte = NULL;
285
263
 		u8 index;
286
264
 
287
265
 		if (rtlhal->macphymode == DUALMAC_DUALPHY)
288
-			regtoSet = 0xb9726641;
266
+			regtoset = 0xb9726641;
289
267
 		else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
290
-			regtoSet = 0x66626641;
268
+			regtoset = 0x66626641;
291
269
 		else
292
-			regtoSet = 0xb972a841;
270
+			regtoset = 0xb972a841;
293
271
 		factor_toset = *val;
294
272
 		if (factor_toset <= 3) {
295
273
 			factor_toset = (1 << (factor_toset + 2));
296
274
 			if (factor_toset > 0xf)
297
275
 				factor_toset = 0xf;
298
276
 			for (index = 0; index < 4; index++) {
299
-				ptmp_byte = (u8 *) (&regtoSet) + index;
277
+				ptmp_byte = (u8 *)(&regtoset) + index;
300
278
 				if ((*ptmp_byte & 0xf0) >
301
279
 				    (factor_toset << 4))
302
280
 					*ptmp_byte = (*ptmp_byte & 0x0f)
..
..
@@ -305,10 +283,10 @@
305
283
 					*ptmp_byte = (*ptmp_byte & 0xf0)
306
284
 						     | (factor_toset);
307
285
 			}
308
-			rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
309
-			RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
310
-				 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
311
-				 factor_toset);
286
+			rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset);
287
+			rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
288
+				"Set HW_VAR_AMPDU_FACTOR: %#x\n",
289
+				factor_toset);
312
290
 		}
313
291
 		break;
314
292
 	}
..
..
@@ -340,9 +318,9 @@
340
318
 				acm_ctrl |= ACMHW_VOQEN;
341
319
 				break;
342
320
 			default:
343
-				RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
344
-					 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
345
-					 acm);
321
+				rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
322
+					"HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
323
+					acm);
346
324
 				break;
347
325
 			}
348
326
 		} else {
..
..
@@ -362,9 +340,9 @@
362
340
 				break;
363
341
 			}
364
342
 		}
365
-		RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
366
-			 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
367
-			 acm_ctrl);
343
+		rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
344
+			"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
345
+			acm_ctrl);
368
346
 		rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
369
347
 		break;
370
348
 	}
..
..
@@ -531,18 +509,18 @@
531
509
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
532
510
 	unsigned short i;
533
511
 	u8 txpktbuf_bndy;
534
-	u8 maxPage;
512
+	u8 maxpage;
535
513
 	bool status;
536
514
 	u32 value32; /* High+low page number */
537
515
 	u8 value8;	 /* normal page number */
538
516
 
539
517
 	if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
540
-		maxPage = 255;
518
+		maxpage = 255;
541
519
 		txpktbuf_bndy = 246;
542
520
 		value8 = 0;
543
521
 		value32 = 0x80bf0d29;
544
522
 	} else {
545
-		maxPage = 127;
523
+		maxpage = 127;
546
524
 		txpktbuf_bndy = 123;
547
525
 		value8 = 0;
548
526
 		value32 = 0x80750005;
..
..
@@ -585,28 +563,28 @@
585
563
 	/* 18.  LLT_table_init(Adapter);  */
586
564
 	for (i = 0; i < (txpktbuf_bndy - 1); i++) {
587
565
 		status = _rtl92de_llt_write(hw, i, i + 1);
588
-		if (true != status)
566
+		if (!status)
589
567
 			return status;
590
568
 	}
591
569
 
592
570
 	/* end of list */
593
571
 	status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
594
-	if (true != status)
572
+	if (!status)
595
573
 		return status;
596
574
 
597
575
 	/* Make the other pages as ring buffer */
598
576
 	/* This ring buffer is used as beacon buffer if we */
599
577
 	/* config this MAC as two MAC transfer. */
600
578
 	/* Otherwise used as local loopback buffer.  */
601
-	for (i = txpktbuf_bndy; i < maxPage; i++) {
579
+	for (i = txpktbuf_bndy; i < maxpage; i++) {
602
580
 		status = _rtl92de_llt_write(hw, i, (i + 1));
603
-		if (true != status)
581
+		if (!status)
604
582
 			return status;
605
583
 	}
606
584
 
607
585
 	/* Let last entry point to the start entry of ring buffer */
608
-	status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
609
-	if (true != status)
586
+	status = _rtl92de_llt_write(hw, maxpage, txpktbuf_bndy);
587
+	if (!status)
610
588
 		return status;
611
589
 
612
590
 	return true;
..
..
@@ -873,13 +851,13 @@
873
851
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
874
852
 	u8 sec_reg_value;
875
853
 
876
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
877
-		 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
878
-		 rtlpriv->sec.pairwise_enc_algorithm,
879
-		 rtlpriv->sec.group_enc_algorithm);
854
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
855
+		"PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
856
+		rtlpriv->sec.pairwise_enc_algorithm,
857
+		rtlpriv->sec.group_enc_algorithm);
880
858
 	if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
881
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
882
-			 "not open hw encryption\n");
859
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
860
+			"not open hw encryption\n");
883
861
 		return;
884
862
 	}
885
863
 	sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
..
..
@@ -889,8 +867,8 @@
889
867
 	}
890
868
 	sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
891
869
 	rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
892
-	RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
893
-		 "The SECR-value %x\n", sec_reg_value);
870
+	rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
871
+		"The SECR-value %x\n", sec_reg_value);
894
872
 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
895
873
 }
896
874
 
..
..
@@ -924,8 +902,8 @@
924
902
 	err = rtl92d_download_fw(hw);
925
903
 	spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
926
904
 	if (err) {
927
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
928
-			 "Failed to download FW. Init HW without FW..\n");
905
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
906
+			"Failed to download FW. Init HW without FW..\n");
929
907
 		return 1;
930
908
 	}
931
909
 	rtlhal->last_hmeboxnum = 0;
..
..
@@ -936,8 +914,8 @@
936
914
 	rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
937
915
 
938
916
 	if (rtlhal->earlymode_enable) {
939
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
940
-			 "EarlyMode Enabled!!!\n");
917
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
918
+			"EarlyMode Enabled!!!\n");
941
919
 
942
920
 		tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
943
921
 		tmp_u1b = tmp_u1b | 0x1f;
..
..
@@ -1055,10 +1033,10 @@
1055
1033
 	value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1056
1034
 	if (!(value32 & 0x000f0000)) {
1057
1035
 		version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1058
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1036
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1059
1037
 	} else {
1060
1038
 		version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1061
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1039
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1062
1040
 	}
1063
1041
 	return version;
1064
1042
 }
..
..
@@ -1082,9 +1060,9 @@
1082
1060
 		_rtl92de_resume_tx_beacon(hw);
1083
1061
 		_rtl92de_disable_bcn_sub_func(hw);
1084
1062
 	} else {
1085
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1086
-			 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1087
-			 type);
1063
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1064
+			"Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1065
+			type);
1088
1066
 	}
1089
1067
 	bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1090
1068
 	switch (type) {
..
..
@@ -1092,27 +1070,27 @@
1092
1070
 		bt_msr |= MSR_NOLINK;
1093
1071
 		ledaction = LED_CTL_LINK;
1094
1072
 		bcnfunc_enable &= 0xF7;
1095
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1096
-			 "Set Network type to NO LINK!\n");
1073
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1074
+			"Set Network type to NO LINK!\n");
1097
1075
 		break;
1098
1076
 	case NL80211_IFTYPE_ADHOC:
1099
1077
 		bt_msr |= MSR_ADHOC;
1100
1078
 		bcnfunc_enable |= 0x08;
1101
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1102
-			 "Set Network type to Ad Hoc!\n");
1079
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1080
+			"Set Network type to Ad Hoc!\n");
1103
1081
 		break;
1104
1082
 	case NL80211_IFTYPE_STATION:
1105
1083
 		bt_msr |= MSR_INFRA;
1106
1084
 		ledaction = LED_CTL_LINK;
1107
1085
 		bcnfunc_enable &= 0xF7;
1108
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1109
-			 "Set Network type to STA!\n");
1086
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1087
+			"Set Network type to STA!\n");
1110
1088
 		break;
1111
1089
 	case NL80211_IFTYPE_AP:
1112
1090
 		bt_msr |= MSR_AP;
1113
1091
 		bcnfunc_enable |= 0x08;
1114
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1115
-			 "Set Network type to AP!\n");
1092
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1093
+			"Set Network type to AP!\n");
1116
1094
 		break;
1117
1095
 	default:
1118
1096
 		pr_err("Network type %d not supported!\n", type);
..
..
@@ -1178,8 +1156,8 @@
1178
1156
 
1179
1157
 	indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1180
1158
 	if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1181
-		RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1182
-			 "Do IQK for channel:%d\n", channel);
1159
+		rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1160
+			"Do IQK for channel:%d\n", channel);
1183
1161
 		rtl92d_phy_iq_calibrate(hw);
1184
1162
 	}
1185
1163
 }
..
..
@@ -1277,9 +1255,9 @@
1277
1255
 	/* is set as 0x18, they had ever met auto load fail problem. */
1278
1256
 	rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1279
1257
 
1280
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1281
-		 "In PowerOff,reg0x%x=%X\n",
1282
-		 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1258
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1259
+		"In PowerOff,reg0x%x=%X\n",
1260
+		REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1283
1261
 	/* r.   Note: for PCIe interface, PON will not turn */
1284
1262
 	/* off m-bias and BandGap in PCIe suspend mode.  */
1285
1263
 
..
..
@@ -1292,7 +1270,7 @@
1292
1270
 		spin_unlock_irqrestore(&globalmutex_power, flags);
1293
1271
 	}
1294
1272
 
1295
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1273
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1296
1274
 }
1297
1275
 
1298
1276
 void rtl92de_card_disable(struct ieee80211_hw *hw)
..
..
@@ -1350,7 +1328,7 @@
1350
1328
 	rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1351
1329
 	udelay(50);
1352
1330
 	rtl_write_byte(rtlpriv, REG_CR, 0x0);
1353
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1331
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1354
1332
 	if (rtl92d_phy_check_poweroff(hw))
1355
1333
 		_rtl92de_poweroff_adapter(hw);
1356
1334
 	return;
..
..
@@ -1392,8 +1370,8 @@
1392
1370
 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1393
1371
 	u16 bcn_interval = mac->beacon_interval;
1394
1372
 
1395
-	RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1396
-		 "beacon_interval:%d\n", bcn_interval);
1373
+	rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1374
+		"beacon_interval:%d\n", bcn_interval);
1397
1375
 	rtl92de_disable_interrupt(hw);
1398
1376
 	rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1399
1377
 	rtl92de_enable_interrupt(hw);
..
..
@@ -1405,8 +1383,8 @@
1405
1383
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
1406
1384
 	struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1407
1385
 
1408
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1409
-		 add_msr, rm_msr);
1386
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1387
+		add_msr, rm_msr);
1410
1388
 	if (add_msr)
1411
1389
 		rtlpci->irq_mask[0] |= add_msr;
1412
1390
 	if (rm_msr)
..
..
@@ -1416,13 +1394,13 @@
1416
1394
 }
1417
1395
 
1418
1396
 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1419
-				 u8 *rom_content, bool autoLoadfail)
1397
+				 u8 *rom_content, bool autoloadfail)
1420
1398
 {
1421
1399
 	u32 rfpath, eeaddr, group, offset1, offset2;
1422
1400
 	u8 i;
1423
1401
 
1424
1402
 	memset(pwrinfo, 0, sizeof(struct txpower_info));
1425
-	if (autoLoadfail) {
1403
+	if (autoloadfail) {
1426
1404
 		for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1427
1405
 			for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1428
1406
 				if (group < CHANNEL_GROUP_MAX_2G) {
..
..
@@ -1564,7 +1542,7 @@
1564
1542
 	struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1565
1543
 	struct txpower_info pwrinfo;
1566
1544
 	u8 tempval[2], i, pwr, diff;
1567
-	u32 ch, rfPath, group;
1545
+	u32 ch, rfpath, group;
1568
1546
 
1569
1547
 	_rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1570
1548
 	if (!autoload_fail) {
..
..
@@ -1582,10 +1560,10 @@
1582
1560
 				!((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1583
1561
 			rtlefuse->internal_pa_5g[1] =
1584
1562
 				!((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1585
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1586
-				 "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1587
-				 rtlefuse->internal_pa_5g[0],
1588
-				 rtlefuse->internal_pa_5g[1]);
1563
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1564
+				"Is D cut,Internal PA0 %d Internal PA1 %d\n",
1565
+				rtlefuse->internal_pa_5g[0],
1566
+				rtlefuse->internal_pa_5g[1]);
1589
1567
 		}
1590
1568
 		rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1591
1569
 		rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
..
..
@@ -1634,35 +1612,35 @@
1634
1612
 		rtlefuse->delta_lck = tempval[1] - 1;
1635
1613
 	if (rtlefuse->eeprom_c9 == 0xFF)
1636
1614
 		rtlefuse->eeprom_c9 = 0x00;
1637
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1638
-		 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1639
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1640
-		 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1641
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1642
-		 "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1643
-	RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1644
-		 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1645
-		 rtlefuse->delta_iqk, rtlefuse->delta_lck);
1615
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1616
+		"EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1617
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1618
+		"ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1619
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1620
+		"CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1621
+	rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1622
+		"Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1623
+		rtlefuse->delta_iqk, rtlefuse->delta_lck);
1646
1624
 
1647
-	for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1625
+	for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1648
1626
 		for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1649
1627
 			group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1650
1628
 			if (ch < CHANNEL_MAX_NUMBER_2G)
1651
-				rtlefuse->txpwrlevel_cck[rfPath][ch] =
1652
-				    pwrinfo.cck_index[rfPath][group];
1653
-			rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1654
-				    pwrinfo.ht40_1sindex[rfPath][group];
1655
-			rtlefuse->txpwr_ht20diff[rfPath][ch] =
1656
-				    pwrinfo.ht20indexdiff[rfPath][group];
1657
-			rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1658
-				    pwrinfo.ofdmindexdiff[rfPath][group];
1659
-			rtlefuse->pwrgroup_ht20[rfPath][ch] =
1660
-				    pwrinfo.ht20maxoffset[rfPath][group];
1661
-			rtlefuse->pwrgroup_ht40[rfPath][ch] =
1662
-				    pwrinfo.ht40maxoffset[rfPath][group];
1663
-			pwr = pwrinfo.ht40_1sindex[rfPath][group];
1664
-			diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1665
-			rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1629
+				rtlefuse->txpwrlevel_cck[rfpath][ch] =
1630
+				    pwrinfo.cck_index[rfpath][group];
1631
+			rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] =
1632
+				    pwrinfo.ht40_1sindex[rfpath][group];
1633
+			rtlefuse->txpwr_ht20diff[rfpath][ch] =
1634
+				    pwrinfo.ht20indexdiff[rfpath][group];
1635
+			rtlefuse->txpwr_legacyhtdiff[rfpath][ch] =
1636
+				    pwrinfo.ofdmindexdiff[rfpath][group];
1637
+			rtlefuse->pwrgroup_ht20[rfpath][ch] =
1638
+				    pwrinfo.ht20maxoffset[rfpath][group];
1639
+			rtlefuse->pwrgroup_ht40[rfpath][ch] =
1640
+				    pwrinfo.ht40maxoffset[rfpath][group];
1641
+			pwr = pwrinfo.ht40_1sindex[rfpath][group];
1642
+			diff = pwrinfo.ht40_2sindexdiff[rfpath][group];
1643
+			rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] =
1666
1644
 				    (pwr > diff) ? (pwr - diff) : 0;
1667
1645
 		}
1668
1646
 	}
..
..
@@ -1677,12 +1655,12 @@
1677
1655
 
1678
1656
 	if (macphy_crvalue & BIT(3)) {
1679
1657
 		rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1680
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1681
-			 "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1658
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1659
+			"MacPhyMode SINGLEMAC_SINGLEPHY\n");
1682
1660
 	} else {
1683
1661
 		rtlhal->macphymode = DUALMAC_DUALPHY;
1684
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1685
-			 "MacPhyMode DUALMAC_DUALPHY\n");
1662
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1663
+			"MacPhyMode DUALMAC_DUALPHY\n");
1686
1664
 	}
1687
1665
 }
1688
1666
 
..
..
@@ -1709,15 +1687,15 @@
1709
1687
 	switch (chipvalue) {
1710
1688
 	case 0xAA55:
1711
1689
 		chipver |= CHIP_92D_C_CUT;
1712
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1690
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1713
1691
 		break;
1714
1692
 	case 0x9966:
1715
1693
 		chipver |= CHIP_92D_D_CUT;
1716
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1694
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1717
1695
 		break;
1718
1696
 	case 0xCC33:
1719
1697
 		chipver |= CHIP_92D_E_CUT;
1720
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1698
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1721
1699
 		break;
1722
1700
 	default:
1723
1701
 		chipver |= CHIP_92D_D_CUT;
..
..
@@ -1759,7 +1737,7 @@
1759
1737
 	}
1760
1738
 	rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1761
1739
 				      rtlefuse->dev_addr);
1762
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1740
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1763
1741
 	_rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1764
1742
 
1765
1743
 	/* Read Channel Plan */
..
..
@@ -1793,14 +1771,14 @@
1793
1771
 	tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1794
1772
 	rtlefuse->autoload_status = tmp_u1b;
1795
1773
 	if (tmp_u1b & BIT(4)) {
1796
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1774
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1797
1775
 		rtlefuse->epromtype = EEPROM_93C46;
1798
1776
 	} else {
1799
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1777
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1800
1778
 		rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1801
1779
 	}
1802
1780
 	if (tmp_u1b & BIT(5)) {
1803
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1781
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1804
1782
 
1805
1783
 		rtlefuse->autoload_failflag = false;
1806
1784
 		_rtl92de_read_adapter_info(hw);
..
..
@@ -1888,8 +1866,8 @@
1888
1866
 		    (shortgi_rate << 4) | (shortgi_rate);
1889
1867
 	}
1890
1868
 	rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1891
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1892
-		 rtl_read_dword(rtlpriv, REG_ARFR0));
1869
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1870
+		rtl_read_dword(rtlpriv, REG_ARFR0));
1893
1871
 }
1894
1872
 
1895
1873
 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
..
..
@@ -2020,9 +1998,9 @@
2020
1998
 
2021
1999
 	value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2022
2000
 	value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2023
-	RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2024
-		 "ratr_bitmap :%x value0:%x value1:%x\n",
2025
-		 ratr_bitmap, value[0], value[1]);
2001
+	rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2002
+		"ratr_bitmap :%x value0:%x value1:%x\n",
2003
+		ratr_bitmap, value[0], value[1]);
2026
2004
 	rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2027
2005
 	if (macid != 0)
2028
2006
 		sta_entry->ratr_index = ratr_index;
..
..
@@ -2081,14 +2059,14 @@
2081
2059
 	u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2082
2060
 	e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2083
2061
 	if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2084
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2085
-			 "GPIOChangeRF  - HW Radio ON, RF ON\n");
2062
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2063
+			"GPIOChangeRF  - HW Radio ON, RF ON\n");
2086
2064
 		e_rfpowerstate_toset = ERFON;
2087
2065
 		ppsc->hwradiooff = false;
2088
2066
 		actuallyset = true;
2089
2067
 	} else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2090
-		RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2091
-			 "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2068
+		rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2069
+			"GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2092
2070
 		e_rfpowerstate_toset = ERFOFF;
2093
2071
 		ppsc->hwradiooff = true;
2094
2072
 		actuallyset = true;
..
..
@@ -2132,7 +2110,7 @@
2132
2110
 		u8 idx;
2133
2111
 		u8 cam_offset = 0;
2134
2112
 		u8 clear_number = 5;
2135
-		RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2113
+		rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2136
2114
 		for (idx = 0; idx < clear_number; idx++) {
2137
2115
 			rtl_cam_mark_invalid(hw, cam_offset + idx);
2138
2116
 			rtl_cam_empty_entry(hw, cam_offset + idx);
..
..
@@ -2186,38 +2164,38 @@
2186
2164
 			}
2187
2165
 		}
2188
2166
 		if (rtlpriv->sec.key_len[key_index] == 0) {
2189
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2190
-				 "delete one entry, entry_id is %d\n",
2191
-				 entry_id);
2167
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2168
+				"delete one entry, entry_id is %d\n",
2169
+				entry_id);
2192
2170
 			if (mac->opmode == NL80211_IFTYPE_AP)
2193
2171
 				rtl_cam_del_entry(hw, p_macaddr);
2194
2172
 			rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2195
2173
 		} else {
2196
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2197
-				 "The insert KEY length is %d\n",
2198
-				 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2199
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2200
-				 "The insert KEY is %x %x\n",
2201
-				 rtlpriv->sec.key_buf[0][0],
2202
-				 rtlpriv->sec.key_buf[0][1]);
2203
-			RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2204
-				 "add one entry\n");
2174
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2175
+				"The insert KEY length is %d\n",
2176
+				rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2177
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD,
2178
+				"The insert KEY is %x %x\n",
2179
+				rtlpriv->sec.key_buf[0][0],
2180
+				rtlpriv->sec.key_buf[0][1]);
2181
+			rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2182
+				"add one entry\n");
2205
2183
 			if (is_pairwise) {
2206
2184
 				RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2207
2185
 					      "Pairwise Key content",
2208
2186
 					      rtlpriv->sec.pairwise_key,
2209
2187
 					      rtlpriv->
2210
2188
 					      sec.key_len[PAIRWISE_KEYIDX]);
2211
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2212
-					 "set Pairwise key\n");
2189
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2190
+					"set Pairwise key\n");
2213
2191
 				rtl_cam_add_one_entry(hw, macaddr, key_index,
2214
2192
 						      entry_id, enc_algo,
2215
2193
 						      CAM_CONFIG_NO_USEDK,
2216
2194
 						      rtlpriv->
2217
2195
 						      sec.key_buf[key_index]);
2218
2196
 			} else {
2219
-				RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2220
-					 "set group key\n");
2197
+				rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2198
+					"set group key\n");
2221
2199
 				if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2222
2200
 					rtl_cam_add_one_entry(hw,
2223
2201
 						rtlefuse->dev_addr,