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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/reg.h
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
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- *
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- * Copyright(c) 2009-2012  Realtek Corporation.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of version 2 of the GNU General Public License as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * The full GNU General Public License is included in this distribution in the
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- * file called LICENSE.
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- *
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- * Contact Information:
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- * wlanfae <wlanfae@realtek.com>
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- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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- * Hsinchu 300, Taiwan.
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- *
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- * Larry Finger <Larry.Finger@lwfinger.net>
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- *
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- *****************************************************************************/
1
+/* SPDX-License-Identifier: GPL-2.0 */
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
253 
264 #ifndef __RTL92C_REG_H__
275 #define __RTL92C_REG_H__
....@@ -702,7 +680,7 @@
702680 #define PWC_EV12V				BIT(15)
703681 
704682 #define FEN_BBRSTB				BIT(0)
705
-#define FEN_BB_GLB_RSTn				BIT(1)
683
+#define FEN_BB_GLB_RSTN				BIT(1)
706684 #define FEN_USBA				BIT(2)
707685 #define FEN_UPLL				BIT(3)
708686 #define FEN_USBD				BIT(4)
....@@ -722,7 +700,7 @@
722700 #define PFM_ALDN				BIT(1)
723701 #define PFM_LDKP				BIT(2)
724702 #define PFM_WOWL				BIT(3)
725
-#define EnPDN					BIT(4)
703
+#define ENPDN					BIT(4)
726704 #define PDN_PL					BIT(5)
727705 #define APFM_ONMAC				BIT(8)
728706 #define APFM_OFF				BIT(9)
....@@ -837,19 +815,19 @@
837815 #define LDOE25_EN				BIT(31)
838816 
839817 #define RSM_EN					BIT(0)
840
-#define Timer_EN				BIT(4)
818
+#define TIMER_EN				BIT(4)
841819 
842820 #define TRSW0EN					BIT(2)
843821 #define TRSW1EN					BIT(3)
844822 #define EROM_EN					BIT(4)
845
-#define EnBT					BIT(5)
846
-#define EnUart					BIT(8)
847
-#define Uart_910				BIT(9)
848
-#define EnPMAC					BIT(10)
823
+#define ENBT					BIT(5)
824
+#define ENUART					BIT(8)
825
+#define UART_910				BIT(9)
826
+#define ENPMAC					BIT(10)
849827 #define SIC_SWRST				BIT(11)
850
-#define EnSIC					BIT(12)
828
+#define ENSIC					BIT(12)
851829 #define SIC_23					BIT(13)
852
-#define EnHDP					BIT(14)
830
+#define ENHDP					BIT(14)
853831 #define SIC_LBK					BIT(15)
854832 
855833 #define LED0PL					BIT(4)
....@@ -858,7 +836,7 @@
858836 
859837 #define MCUFWDL_EN				BIT(0)
860838 #define MCUFWDL_RDY				BIT(1)
861
-#define FWDL_ChkSum_rpt				BIT(2)
839
+#define FWDL_CHKSUM_RPT				BIT(2)
862840 #define MACINI_RDY				BIT(3)
863841 #define BBINI_RDY				BIT(4)
864842 #define RFINI_RDY				BIT(5)
....@@ -1076,13 +1054,13 @@
10761054 #define	DIS_TSF_UDT0_NORMAL_CHIP		BIT(4)
10771055 #define	DIS_TSF_UDT0_TEST_CHIP			BIT(5)
10781056 
1079
-#define	AcmHw_HwEn				BIT(0)
1080
-#define	AcmHw_BeqEn				BIT(1)
1081
-#define	AcmHw_ViqEn				BIT(2)
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-#define	AcmHw_VoqEn				BIT(3)
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-#define	AcmHw_BeqStatus				BIT(4)
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-#define	AcmHw_ViqStatus				BIT(5)
1085
-#define	AcmHw_VoqStatus				BIT(6)
1057
+#define	ACMHW_HWEN				BIT(0)
1058
+#define	ACMHW_BEQEN				BIT(1)
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+#define	ACMHW_VIQEN				BIT(2)
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+#define	ACMHW_VOQEN				BIT(3)
1061
+#define	ACMHW_BEQSTATUS				BIT(4)
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+#define	ACMHW_VIQSTATUS				BIT(5)
1063
+#define	ACMHW_VOQSTATUS				BIT(6)
10861064 
10871065 #define APSDOFF					BIT(6)
10881066 #define APSDOFF_STATUS				BIT(7)
....@@ -1121,7 +1099,7 @@
11211099 #define BM_DATA_EN				BIT(17)
11221100 #define MFBEN					BIT(22)
11231101 #define LSIGEN					BIT(23)
1124
-#define EnMBID					BIT(24)
1102
+#define ENMBID					BIT(24)
11251103 #define APP_BASSN				BIT(27)
11261104 #define APP_PHYSTS				BIT(28)
11271105 #define APP_ICV					BIT(29)
....@@ -1150,12 +1128,12 @@
11501128 #define RXERR_RPT_RST				BIT(27)
11511129 #define _RXERR_RPT_SEL(type)			((type) << 28)
11521130 
1153
-#define	SCR_TxUseDK				BIT(0)
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-#define	SCR_RxUseDK				BIT(1)
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-#define	SCR_TxEncEnable				BIT(2)
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-#define	SCR_RxDecEnable				BIT(3)
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-#define	SCR_SKByA2				BIT(4)
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-#define	SCR_NoSKMC				BIT(5)
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+#define	SCR_TXUSEDK				BIT(0)
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+#define	SCR_RXUSEDK				BIT(1)
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+#define	SCR_TXENCENABLE				BIT(2)
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+#define	SCR_RXDECENABLE				BIT(3)
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+#define	SCR_SKBYA2				BIT(4)
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+#define	SCR_NOSKMC				BIT(5)
11591137 #define SCR_TXBCUSEDK				BIT(6)
11601138 #define SCR_RXBCUSEDK				BIT(7)
11611139 
....@@ -1208,7 +1186,7 @@
12081186 #define	RPMAC_CCKPLCPHEADER			0x144
12091187 #define	RPMAC_CCKCRC16				0x148
12101188 #define	RPMAC_OFDMRXCRC32OK			0x170
1211
-#define	RPMAC_OFDMRXCRC32Er			0x174
1189
+#define	RPMAC_OFDMRXCRC32ER			0x174
12121190 #define	RPMAC_OFDMRXPARITYER			0x178
12131191 #define	RPMAC_OFDMRXCRC8ER			0x17c
12141192 #define	RPMAC_CCKCRXRC16ER			0x180
....@@ -1246,8 +1224,8 @@
12461224 #define	RFPGA0_XAB_RFINTERFACESW		0x870
12471225 #define	RFPGA0_XCD_RFINTERFACESW		0x874
12481226 
1249
-#define	rFPGA0_XAB_RFPARAMETER			0x878
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-#define	rFPGA0_XCD_RFPARAMETER			0x87c
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+#define	RFPGA0_XAB_RFPARAMETER			0x878
1228
+#define	RFPGA0_XCD_RFPARAMETER			0x87c
12511229 
12521230 #define	RFPGA0_ANALOGPARAMETER1			0x880
12531231 #define	RFPGA0_ANALOGPARAMETER2			0x884
....@@ -1521,8 +1499,8 @@
15211499 #define	BCCKTXCRC16				0xffff
15221500 #define	BCCKTXSTATUS				0x1
15231501 #define	BOFDMTXSTATUS				0x2
1524
-#define IS_BB_REG_OFFSET_92S(_Offset)		\
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-	((_Offset >= 0x800) && (_Offset <= 0xfff))
1502
+#define IS_BB_REG_OFFSET_92S(_offset)		\
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+	(((_offset) >= 0x800) && ((_offset) <= 0xfff))
15261504 
15271505 #define	BRFMOD					0x1
15281506 #define	BJAPANMODE				0x2
....@@ -1715,7 +1693,6 @@
17151693 #define	BCCK_RF_EXTEND				0x20000000
17161694 #define	BCCK_RXAGC_SATLEVEL			0x1f000000
17171695 #define	BCCK_RXAGC_SATCOUNT			0xe0
1718
-#define	bCCKRxRFSettle				0x1f
17191696 #define	BCCK_FIXED_RXAGC			0x8000
17201697 #define	BCCK_ANTENNA_POLARITY			0x2000
17211698 #define	BCCK_TXFILTER_TYPE			0x0c00