forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c
....@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2012  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
253 
264 #include "../wifi.h"
275 #include "../rtl8192ce/reg.h"
....@@ -36,15 +14,15 @@
3614 	struct rtl_priv *rtlpriv = rtl_priv(hw);
3715 	u32 returnvalue, originalvalue, bitshift;
3816 
39
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
40
-		 regaddr, bitmask);
17
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
18
+		regaddr, bitmask);
4119 	originalvalue = rtl_read_dword(rtlpriv, regaddr);
4220 	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
4321 	returnvalue = (originalvalue & bitmask) >> bitshift;
4422 
45
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
46
-		 "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
47
-		 bitmask, regaddr, originalvalue);
23
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
24
+		"BBR MASK=0x%x Addr[0x%x]=0x%x\n",
25
+		bitmask, regaddr, originalvalue);
4826 
4927 	return returnvalue;
5028 }
....@@ -56,9 +34,9 @@
5634 	struct rtl_priv *rtlpriv = rtl_priv(hw);
5735 	u32 originalvalue, bitshift;
5836 
59
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
60
-		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
61
-		 regaddr, bitmask, data);
37
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
38
+		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
39
+		regaddr, bitmask, data);
6240 
6341 	if (bitmask != MASKDWORD) {
6442 		originalvalue = rtl_read_dword(rtlpriv, regaddr);
....@@ -68,9 +46,9 @@
6846 
6947 	rtl_write_dword(rtlpriv, regaddr, data);
7048 
71
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
72
-		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
73
-		 regaddr, bitmask, data);
49
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
50
+		"regaddr(%#x), bitmask(%#x), data(%#x)\n",
51
+		regaddr, bitmask, data);
7452 }
7553 EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
7654 
....@@ -134,9 +112,9 @@
134112 	else
135113 		retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
136114 					 BLSSIREADBACKDATA);
137
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
138
-					       rfpath, pphyreg->rf_rb,
139
-					       retvalue);
115
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
116
+		rfpath, pphyreg->rf_rb,
117
+		retvalue);
140118 	return retvalue;
141119 }
142120 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
....@@ -159,21 +137,17 @@
159137 	newoffset = offset;
160138 	data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
161139 	rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
162
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
163
-					       rfpath, pphyreg->rf3wire_offset,
164
-					       data_and_addr);
140
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
141
+		rfpath, pphyreg->rf3wire_offset,
142
+		data_and_addr);
165143 }
166144 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
167145 
168146 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
169147 {
170
-	u32 i;
148
+	u32 i = ffs(bitmask);
171149 
172
-	for (i = 0; i <= 31; i++) {
173
-		if (((bitmask >> i) & 0x1) == 1)
174
-			break;
175
-	}
176
-	return i;
150
+	return i ? i - 1 : 32;
177151 }
178152 EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
179153 
....@@ -214,7 +188,7 @@
214188 	}
215189 	if (rtlphy->rf_type == RF_1T2R) {
216190 		_rtl92c_phy_bb_config_1t(hw);
217
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
191
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
218192 	}
219193 	if (rtlefuse->autoload_failflag == false) {
220194 		rtlphy->pwrgroup_cnt = 0;
....@@ -239,7 +213,7 @@
239213 
240214 EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
241215 
242
-void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
216
+void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
243217 					    u32 regaddr, u32 bitmask,
244218 					    u32 data)
245219 {
....@@ -249,151 +223,151 @@
249223 	if (regaddr == RTXAGC_A_RATE18_06) {
250224 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
251225 		    data;
252
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
253
-			 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
254
-			  rtlphy->pwrgroup_cnt,
255
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
256
-							    pwrgroup_cnt][0]);
226
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
227
+			"MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
228
+			rtlphy->pwrgroup_cnt,
229
+			rtlphy->mcs_txpwrlevel_origoffset
230
+			[rtlphy->pwrgroup_cnt][0]);
257231 	}
258232 	if (regaddr == RTXAGC_A_RATE54_24) {
259233 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
260234 		    data;
261
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
262
-			 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
263
-			  rtlphy->pwrgroup_cnt,
264
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
265
-							    pwrgroup_cnt][1]);
235
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
236
+			"MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
237
+			rtlphy->pwrgroup_cnt,
238
+			rtlphy->mcs_txpwrlevel_origoffset
239
+			[rtlphy->pwrgroup_cnt][1]);
266240 	}
267241 	if (regaddr == RTXAGC_A_CCK1_MCS32) {
268242 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
269243 		    data;
270
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
271
-			 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
272
-			  rtlphy->pwrgroup_cnt,
273
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
274
-							    pwrgroup_cnt][6]);
244
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
245
+			"MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
246
+			rtlphy->pwrgroup_cnt,
247
+			rtlphy->mcs_txpwrlevel_origoffset
248
+			[rtlphy->pwrgroup_cnt][6]);
275249 	}
276250 	if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
277251 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
278252 		    data;
279
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
280
-			 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
281
-			  rtlphy->pwrgroup_cnt,
282
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
253
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
254
+			"MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
255
+			rtlphy->pwrgroup_cnt,
256
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
283257 							    pwrgroup_cnt][7]);
284258 	}
285259 	if (regaddr == RTXAGC_A_MCS03_MCS00) {
286260 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
287261 		    data;
288
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
289
-			 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
290
-			  rtlphy->pwrgroup_cnt,
291
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
262
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
263
+			"MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
264
+			rtlphy->pwrgroup_cnt,
265
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
292266 							    pwrgroup_cnt][2]);
293267 	}
294268 	if (regaddr == RTXAGC_A_MCS07_MCS04) {
295269 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
296270 		    data;
297
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
298
-			 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
299
-			  rtlphy->pwrgroup_cnt,
300
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
271
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
272
+			"MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
273
+			rtlphy->pwrgroup_cnt,
274
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
301275 							    pwrgroup_cnt][3]);
302276 	}
303277 	if (regaddr == RTXAGC_A_MCS11_MCS08) {
304278 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
305279 		    data;
306
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
307
-			 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
308
-			  rtlphy->pwrgroup_cnt,
309
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
280
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
281
+			"MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
282
+			rtlphy->pwrgroup_cnt,
283
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
310284 							    pwrgroup_cnt][4]);
311285 	}
312286 	if (regaddr == RTXAGC_A_MCS15_MCS12) {
313287 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
314288 		    data;
315
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
316
-			 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
317
-			  rtlphy->pwrgroup_cnt,
318
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
289
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
290
+			"MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
291
+			rtlphy->pwrgroup_cnt,
292
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
319293 							    pwrgroup_cnt][5]);
320294 	}
321295 	if (regaddr == RTXAGC_B_RATE18_06) {
322296 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
323297 		    data;
324
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
325
-			 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
326
-			  rtlphy->pwrgroup_cnt,
327
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
298
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
299
+			"MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
300
+			rtlphy->pwrgroup_cnt,
301
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
328302 							    pwrgroup_cnt][8]);
329303 	}
330304 	if (regaddr == RTXAGC_B_RATE54_24) {
331305 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
332306 		    data;
333
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
334
-			 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
335
-			  rtlphy->pwrgroup_cnt,
336
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
307
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
308
+			"MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
309
+			rtlphy->pwrgroup_cnt,
310
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
337311 							    pwrgroup_cnt][9]);
338312 	}
339313 	if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
340314 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
341315 		    data;
342
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
343
-			 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
344
-			  rtlphy->pwrgroup_cnt,
345
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
316
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
317
+			"MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
318
+			rtlphy->pwrgroup_cnt,
319
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
346320 							    pwrgroup_cnt][14]);
347321 	}
348322 	if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
349323 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
350324 		    data;
351
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
352
-			 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
353
-			  rtlphy->pwrgroup_cnt,
354
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
325
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
326
+			"MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
327
+			rtlphy->pwrgroup_cnt,
328
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
355329 							    pwrgroup_cnt][15]);
356330 	}
357331 	if (regaddr == RTXAGC_B_MCS03_MCS00) {
358332 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
359333 		    data;
360
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
361
-			 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
362
-			  rtlphy->pwrgroup_cnt,
363
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
334
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
335
+			"MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
336
+			rtlphy->pwrgroup_cnt,
337
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
364338 							    pwrgroup_cnt][10]);
365339 	}
366340 	if (regaddr == RTXAGC_B_MCS07_MCS04) {
367341 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
368342 		    data;
369
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
370
-			 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
371
-			  rtlphy->pwrgroup_cnt,
372
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
343
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
344
+			"MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
345
+			rtlphy->pwrgroup_cnt,
346
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
373347 							    pwrgroup_cnt][11]);
374348 	}
375349 	if (regaddr == RTXAGC_B_MCS11_MCS08) {
376350 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
377351 		    data;
378
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
379
-			 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
380
-			  rtlphy->pwrgroup_cnt,
381
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
352
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
353
+			"MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
354
+			rtlphy->pwrgroup_cnt,
355
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
382356 							    pwrgroup_cnt][12]);
383357 	}
384358 	if (regaddr == RTXAGC_B_MCS15_MCS12) {
385359 		rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
386360 		    data;
387
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
388
-			 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
389
-			  rtlphy->pwrgroup_cnt,
390
-			  rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
361
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
362
+			"MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
363
+			rtlphy->pwrgroup_cnt,
364
+			rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
391365 							    pwrgroup_cnt][13]);
392366 
393367 		rtlphy->pwrgroup_cnt++;
394368 	}
395369 }
396
-EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);
370
+EXPORT_SYMBOL(_rtl92c_store_pwrindex_diffrate_offset);
397371 
398372 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
399373 {
....@@ -409,21 +383,21 @@
409383 	rtlphy->default_initialgain[3] =
410384 	    (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
411385 
412
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
413
-		 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
414
-		  rtlphy->default_initialgain[0],
415
-		  rtlphy->default_initialgain[1],
416
-		  rtlphy->default_initialgain[2],
417
-		  rtlphy->default_initialgain[3]);
386
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
387
+		"Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
388
+		rtlphy->default_initialgain[0],
389
+		rtlphy->default_initialgain[1],
390
+		rtlphy->default_initialgain[2],
391
+		rtlphy->default_initialgain[3]);
418392 
419393 	rtlphy->framesync = (u8)rtl_get_bbreg(hw,
420394 					       ROFDM0_RXDETECTOR3, MASKBYTE0);
421395 	rtlphy->framesync_c34 = rtl_get_bbreg(hw,
422396 					      ROFDM0_RXDETECTOR2, MASKDWORD);
423397 
424
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
425
-		 "Default framesync (0x%x) = 0x%x\n",
426
-		  ROFDM0_RXDETECTOR3, rtlphy->framesync);
398
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
399
+		"Default framesync (0x%x) = 0x%x\n",
400
+		ROFDM0_RXDETECTOR3, rtlphy->framesync);
427401 }
428402 
429403 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
....@@ -452,10 +426,10 @@
452426 	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
453427 	    RFPGA0_XB_LSSIPARAMETER;
454428 
455
-	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
456
-	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
457
-	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
458
-	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
429
+	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
430
+	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
431
+	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
432
+	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
459433 
460434 	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
461435 	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
....@@ -610,9 +584,9 @@
610584 		ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
611585 	else
612586 		ofdmtxpwridx = 0;
613
-	RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
614
-		 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
615
-		  power_indbm, ccktxpwridx, ofdmtxpwridx);
587
+	rtl_dbg(rtlpriv, COMP_TXAGC, DBG_TRACE,
588
+		"%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
589
+		power_indbm, ccktxpwridx, ofdmtxpwridx);
616590 	for (idx = 0; idx < 14; idx++) {
617591 		for (rf_path = 0; rf_path < 2; rf_path++) {
618592 			rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
....@@ -697,8 +671,8 @@
697671 	if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
698672 		rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
699673 	} else {
700
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
701
-			 "false driver sleep or unload\n");
674
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
675
+			"false driver sleep or unload\n");
702676 		rtlphy->set_bwmode_inprogress = false;
703677 		rtlphy->current_chan_bw = tmp_bw;
704678 	}
....@@ -712,8 +686,8 @@
712686 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
713687 	u32 delay;
714688 
715
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
716
-		 "switch to channel%d\n", rtlphy->current_channel);
689
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE,
690
+		"switch to channel%d\n", rtlphy->current_channel);
717691 	if (is_hal_stop(rtlhal))
718692 		return;
719693 	do {
....@@ -731,7 +705,7 @@
731705 		}
732706 		break;
733707 	} while (true);
734
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
708
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
735709 }
736710 EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
737711 
....@@ -752,12 +726,12 @@
752726 	rtlphy->sw_chnl_step = 0;
753727 	if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
754728 		rtl92c_phy_sw_chnl_callback(hw);
755
-		RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
756
-			 "sw_chnl_inprogress false schedule workitem\n");
729
+		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
730
+			"sw_chnl_inprogress false schedule workitem\n");
757731 		rtlphy->sw_chnl_inprogress = false;
758732 	} else {
759
-		RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
760
-			 "sw_chnl_inprogress false driver sleep or unload\n");
733
+		rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD,
734
+			"sw_chnl_inprogress false driver sleep or unload\n");
761735 		rtlphy->sw_chnl_inprogress = false;
762736 	}
763737 	return 1;
....@@ -769,6 +743,7 @@
769743 	struct rtl_priv *rtlpriv = rtl_priv(hw);
770744 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
771745 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
746
+
772747 	if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
773748 		if (channel == 6 &&
774749 		    rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
....@@ -905,9 +880,9 @@
905880 			_rtl92c_phy_sw_rf_seting(hw, channel);
906881 			break;
907882 		default:
908
-			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
909
-				 "switch case %#x not processed\n",
910
-				 currentcmd->cmdid);
883
+			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
884
+				"switch case %#x not processed\n",
885
+				currentcmd->cmdid);
911886 			break;
912887 		}
913888 
....@@ -1120,19 +1095,19 @@
11201095 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
11211096 				     u32 *addareg, bool is_patha_on, bool is2t)
11221097 {
1123
-	u32 pathOn;
1098
+	u32 pathon;
11241099 	u32 i;
11251100 
1126
-	pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1127
-	if (false == is2t) {
1128
-		pathOn = 0x0bdb25a0;
1101
+	pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1102
+	if (!is2t) {
1103
+		pathon = 0x0bdb25a0;
11291104 		rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
11301105 	} else {
1131
-		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1106
+		rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
11321107 	}
11331108 
11341109 	for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1135
-		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1110
+		rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
11361111 }
11371112 
11381113 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
....@@ -1241,10 +1216,9 @@
12411216 		0x522, 0x550, 0x551, 0x040
12421217 	};
12431218 	const u32 retrycount = 2;
1244
-	u32 bbvalue;
12451219 
12461220 	if (t == 0) {
1247
-		bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1221
+		rtl_get_bbreg(hw, 0x800, MASKDWORD);
12481222 
12491223 		_rtl92c_phy_save_adda_registers(hw, adda_reg,
12501224 						rtlphy->adda_backup, 16);
....@@ -1361,7 +1335,7 @@
13611335 
13621336 	if (is_hal_stop(rtlhal)) {
13631337 		rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1364
-		rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1338
+		rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
13651339 	}
13661340 	if (is2t) {
13671341 		if (bmain)
....@@ -1390,8 +1364,8 @@
13901364 	long result[4][8];
13911365 	u8 i, final_candidate;
13921366 	bool b_patha_ok, b_pathb_ok;
1393
-	long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1394
-	    reg_ecc, reg_tmp = 0;
1367
+	long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4,
1368
+	    reg_tmp = 0;
13951369 	bool is12simular, is13simular, is23simular;
13961370 	u32 iqk_bb_reg[10] = {
13971371 		ROFDM0_XARXIQIMBALANCE,
....@@ -1466,21 +1440,17 @@
14661440 		reg_e94 = result[i][0];
14671441 		reg_e9c = result[i][1];
14681442 		reg_ea4 = result[i][2];
1469
-		reg_eac = result[i][3];
14701443 		reg_eb4 = result[i][4];
14711444 		reg_ebc = result[i][5];
14721445 		reg_ec4 = result[i][6];
1473
-		reg_ecc = result[i][7];
14741446 	}
14751447 	if (final_candidate != 0xff) {
14761448 		rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
14771449 		rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
14781450 		reg_ea4 = result[final_candidate][2];
1479
-		reg_eac = result[final_candidate][3];
14801451 		rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
14811452 		rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
14821453 		reg_ec4 = result[final_candidate][6];
1483
-		reg_ecc = result[final_candidate][7];
14841454 		b_patha_ok = true;
14851455 		b_pathb_ok = true;
14861456 	} else {
....@@ -1547,24 +1517,24 @@
15471517 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
15481518 	bool postprocessing = false;
15491519 
1550
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1551
-		 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1552
-		  iotype, rtlphy->set_io_inprogress);
1520
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1521
+		"-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1522
+		iotype, rtlphy->set_io_inprogress);
15531523 	do {
15541524 		switch (iotype) {
15551525 		case IO_CMD_RESUME_DM_BY_SCAN:
1556
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1557
-				 "[IO CMD] Resume DM after scan.\n");
1526
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1527
+				"[IO CMD] Resume DM after scan.\n");
15581528 			postprocessing = true;
15591529 			break;
15601530 		case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1561
-			RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1562
-				 "[IO CMD] Pause DM before scan.\n");
1531
+			rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1532
+				"[IO CMD] Pause DM before scan.\n");
15631533 			postprocessing = true;
15641534 			break;
15651535 		default:
1566
-			RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1567
-				 "switch case %#x not processed\n", iotype);
1536
+			rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1537
+				"switch case %#x not processed\n", iotype);
15681538 			break;
15691539 		}
15701540 	} while (false);
....@@ -1575,7 +1545,7 @@
15751545 		return false;
15761546 	}
15771547 	rtl92c_phy_set_io(hw);
1578
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1548
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
15791549 	return true;
15801550 }
15811551 EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
....@@ -1586,9 +1556,9 @@
15861556 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
15871557 	struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
15881558 
1589
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1590
-		 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1591
-		  rtlphy->current_io_type, rtlphy->set_io_inprogress);
1559
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1560
+		"--->Cmd(%#x), set_io_inprogress(%d)\n",
1561
+		rtlphy->current_io_type, rtlphy->set_io_inprogress);
15921562 	switch (rtlphy->current_io_type) {
15931563 	case IO_CMD_RESUME_DM_BY_SCAN:
15941564 		dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
....@@ -1601,14 +1571,14 @@
16011571 		rtl92c_dm_write_dig(hw);
16021572 		break;
16031573 	default:
1604
-		RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1605
-			 "switch case %#x not processed\n",
1606
-			 rtlphy->current_io_type);
1574
+		rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1575
+			"switch case %#x not processed\n",
1576
+			rtlphy->current_io_type);
16071577 		break;
16081578 	}
16091579 	rtlphy->set_io_inprogress = false;
1610
-	RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1611
-		 "(%#x)\n", rtlphy->current_io_type);
1580
+	rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE,
1581
+		"(%#x)\n", rtlphy->current_io_type);
16121582 }
16131583 EXPORT_SYMBOL(rtl92c_phy_set_io);
16141584 
....@@ -1647,8 +1617,8 @@
16471617 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
16481618 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
16491619 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1650
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1651
-			 "Switch RF timeout !!!.\n");
1620
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
1621
+			"Switch RF timeout !!!.\n");
16521622 		return;
16531623 	}
16541624 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);