modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/net/wireless/mediatek/mt76/mmio.c
..
..
@@ -1,17 +1,6 @@
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+// SPDX-License-Identifier: ISC
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 /*
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  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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- *
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- * Permission to use, copy, modify, and/or distribute this software for any
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- * purpose with or without fee is hereby granted, provided that the above
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- * copyright notice and this permission notice appear in all copies.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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  */
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5
 
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 #include "mt76.h"
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@@ -21,7 +10,7 @@
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 {
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 	u32 val;
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12
 
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-	val = ioread32(dev->regs + offset);
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+	val = readl(dev->mmio.regs + offset);
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 	trace_reg_rr(dev, offset, val);
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 	return val;
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@@ -30,7 +19,7 @@
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 static void mt76_mmio_wr(struct mt76_dev *dev, u32 offset, u32 val)
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 {
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 	trace_reg_wr(dev, offset, val);
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-	iowrite32(val, dev->regs + offset);
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+	writel(val, dev->mmio.regs + offset);
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 }
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 static u32 mt76_mmio_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val)
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@@ -40,11 +29,55 @@
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 	return val;
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 }
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31
 
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-static void mt76_mmio_copy(struct mt76_dev *dev, u32 offset, const void *data,
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-			   int len)
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+static void mt76_mmio_write_copy(struct mt76_dev *dev, u32 offset,
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+				 const void *data, int len)
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 {
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-	__iowrite32_copy(dev->regs + offset, data, len >> 2);
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+	__iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4));
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 }
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+
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+static void mt76_mmio_read_copy(struct mt76_dev *dev, u32 offset,
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+				void *data, int len)
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+{
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+	__ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4));
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+}
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+
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+static int mt76_mmio_wr_rp(struct mt76_dev *dev, u32 base,
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+			   const struct mt76_reg_pair *data, int len)
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+{
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+	while (len > 0) {
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+		mt76_mmio_wr(dev, data->reg, data->value);
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+		data++;
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+		len--;
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+	}
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+
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+	return 0;
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+}
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+
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+static int mt76_mmio_rd_rp(struct mt76_dev *dev, u32 base,
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+			   struct mt76_reg_pair *data, int len)
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+{
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+	while (len > 0) {
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+		data->value = mt76_mmio_rr(dev, data->reg);
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+		data++;
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+		len--;
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+	}
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+
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+	return 0;
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+}
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+
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+void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr,
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+		       u32 clear, u32 set)
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+{
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+	unsigned long flags;
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+
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+	spin_lock_irqsave(&dev->mmio.irq_lock, flags);
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+	dev->mmio.irqmask &= ~clear;
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+	dev->mmio.irqmask |= set;
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+	if (addr)
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+		mt76_mmio_wr(dev, addr, dev->mmio.irqmask);
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+	spin_unlock_irqrestore(&dev->mmio.irq_lock, flags);
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+}
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+EXPORT_SYMBOL_GPL(mt76_set_irq_mask);
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 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs)
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 {
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@@ -52,10 +85,16 @@
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 		.rr = mt76_mmio_rr,
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 		.rmw = mt76_mmio_rmw,
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 		.wr = mt76_mmio_wr,
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-		.copy = mt76_mmio_copy,
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+		.write_copy = mt76_mmio_write_copy,
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+		.read_copy = mt76_mmio_read_copy,
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+		.wr_rp = mt76_mmio_wr_rp,
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+		.rd_rp = mt76_mmio_rd_rp,
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+		.type = MT76_BUS_MMIO,
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 	};
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 	dev->bus = &mt76_mmio_ops;
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-	dev->regs = regs;
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+	dev->mmio.regs = regs;
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+
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+	spin_lock_init(&dev->mmio.irq_lock);
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 }
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 EXPORT_SYMBOL_GPL(mt76_mmio_init);