modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/net/can/c_can/c_can_platform.c
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@@ -40,10 +40,11 @@
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 #include "c_can.h"
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-#define DCAN_RAM_INIT_BIT		(1 << 3)
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+#define DCAN_RAM_INIT_BIT BIT(3)
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+
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 static DEFINE_SPINLOCK(raminit_lock);
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-/*
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- * 16-bit c_can registers can be arranged differently in the memory
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+
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+/* 16-bit c_can registers can be arranged differently in the memory
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  * architecture of different implementations. For example: 16-bit
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  * registers can be aligned to a 16-bit boundary or 32-bit boundary etc.
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  * Handle the same by providing a common read/write interface.
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@@ -55,7 +56,7 @@
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 }
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 static void c_can_plat_write_reg_aligned_to_16bit(const struct c_can_priv *priv,
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-						enum reg index, u16 val)
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+						  enum reg index, u16 val)
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 {
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 	writew(val, priv->base + priv->regs[index]);
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 }
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@@ -67,7 +68,7 @@
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 }
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 static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv,
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-						enum reg index, u16 val)
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+						  enum reg index, u16 val)
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 {
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 	writew(val, priv->base + 2 * priv->regs[index]);
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 }
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@@ -145,13 +146,13 @@
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 	u32 val;
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 	val = priv->read_reg(priv, index);
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-	val |= ((u32) priv->read_reg(priv, index + 1)) << 16;
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+	val |= ((u32)priv->read_reg(priv, index + 1)) << 16;
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 	return val;
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 }
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-static void c_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
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-		u32 val)
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+static void c_can_plat_write_reg32(const struct c_can_priv *priv,
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+				   enum reg index, u32 val)
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 {
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 	priv->write_reg(priv, index + 1, val >> 16);
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 	priv->write_reg(priv, index, val);
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@@ -162,8 +163,8 @@
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 	return readl(priv->base + priv->regs[index]);
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 }
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-static void d_can_plat_write_reg32(const struct c_can_priv *priv, enum reg index,
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-		u32 val)
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+static void d_can_plat_write_reg32(const struct c_can_priv *priv,
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+				   enum reg index, u32 val)
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 {
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 	writel(val, priv->base + priv->regs[index]);
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 }