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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/mmc/host/sdhci.h
....@@ -1,24 +1,22 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
34  *
45  * Header file for Host Controller registers and I/O accessors.
56  *
67  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or (at
11
- * your option) any later version.
128  */
139 #ifndef __SDHCI_HW_H
1410 #define __SDHCI_HW_H
1511 
12
+#include <linux/bits.h>
1613 #include <linux/scatterlist.h>
1714 #include <linux/compiler.h>
1815 #include <linux/types.h>
1916 #include <linux/io.h>
2017 #include <linux/leds.h>
2118 #include <linux/interrupt.h>
19
+#include <linux/android_kabi.h>
2220 
2321 #include <linux/mmc/host.h>
2422 
....@@ -28,6 +26,7 @@
2826 
2927 #define SDHCI_DMA_ADDRESS	0x00
3028 #define SDHCI_ARGUMENT2		SDHCI_DMA_ADDRESS
29
+#define SDHCI_32BIT_BLK_CNT	SDHCI_DMA_ADDRESS
3130 
3231 #define SDHCI_BLOCK_SIZE	0x04
3332 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
....@@ -41,6 +40,7 @@
4140 #define  SDHCI_TRNS_BLK_CNT_EN	0x02
4241 #define  SDHCI_TRNS_AUTO_CMD12	0x04
4342 #define  SDHCI_TRNS_AUTO_CMD23	0x08
43
+#define  SDHCI_TRNS_AUTO_SEL	0x0C
4444 #define  SDHCI_TRNS_READ	0x10
4545 #define  SDHCI_TRNS_MULTI	0x20
4646 
....@@ -71,6 +71,10 @@
7171 #define  SDHCI_SPACE_AVAILABLE	0x00000400
7272 #define  SDHCI_DATA_AVAILABLE	0x00000800
7373 #define  SDHCI_CARD_PRESENT	0x00010000
74
+#define   SDHCI_CARD_PRES_SHIFT	16
75
+#define  SDHCI_CD_STABLE	0x00020000
76
+#define  SDHCI_CD_LVL		0x00040000
77
+#define   SDHCI_CD_LVL_SHIFT	18
7478 #define  SDHCI_WRITE_PROTECT	0x00080000
7579 #define  SDHCI_DATA_LVL_MASK	0x00F00000
7680 #define   SDHCI_DATA_LVL_SHIFT	20
....@@ -86,7 +90,8 @@
8690 #define   SDHCI_CTRL_ADMA1	0x08
8791 #define   SDHCI_CTRL_ADMA32	0x10
8892 #define   SDHCI_CTRL_ADMA64	0x18
89
-#define   SDHCI_CTRL_8BITBUS	0x20
93
+#define   SDHCI_CTRL_ADMA3	0x18
94
+#define  SDHCI_CTRL_8BITBUS	0x20
9095 #define  SDHCI_CTRL_CDTEST_INS	0x40
9196 #define  SDHCI_CTRL_CDTEST_EN	0x80
9297 
....@@ -111,6 +116,7 @@
111116 #define  SDHCI_DIV_HI_MASK	0x300
112117 #define  SDHCI_PROG_CLOCK_MODE	0x0020
113118 #define  SDHCI_CLOCK_CARD_EN	0x0004
119
+#define  SDHCI_CLOCK_PLL_EN	0x0008
114120 #define  SDHCI_CLOCK_INT_STABLE	0x0002
115121 #define  SDHCI_CLOCK_INT_EN	0x0001
116122 
....@@ -189,15 +195,16 @@
189195 #define   SDHCI_CTRL_DRV_TYPE_D		0x0030
190196 #define  SDHCI_CTRL_EXEC_TUNING		0x0040
191197 #define  SDHCI_CTRL_TUNED_CLK		0x0080
198
+#define  SDHCI_CMD23_ENABLE		0x0800
199
+#define  SDHCI_CTRL_V4_MODE		0x1000
200
+#define  SDHCI_CTRL_64BIT_ADDR		0x2000
192201 #define  SDHCI_CTRL_PRESET_VAL_ENABLE	0x8000
193202 
194203 #define SDHCI_CAPABILITIES	0x40
195
-#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
196
-#define  SDHCI_TIMEOUT_CLK_SHIFT 0
204
+#define  SDHCI_TIMEOUT_CLK_MASK		GENMASK(5, 0)
197205 #define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
198
-#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
199
-#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
200
-#define  SDHCI_CLOCK_BASE_SHIFT	8
206
+#define  SDHCI_CLOCK_BASE_MASK		GENMASK(13, 8)
207
+#define  SDHCI_CLOCK_V3_BASE_MASK	GENMASK(15, 8)
201208 #define  SDHCI_MAX_BLOCK_MASK	0x00030000
202209 #define  SDHCI_MAX_BLOCK_SHIFT  16
203210 #define  SDHCI_CAN_DO_8BIT	0x00040000
....@@ -209,33 +216,28 @@
209216 #define  SDHCI_CAN_VDD_330	0x01000000
210217 #define  SDHCI_CAN_VDD_300	0x02000000
211218 #define  SDHCI_CAN_VDD_180	0x04000000
219
+#define  SDHCI_CAN_64BIT_V4	0x08000000
212220 #define  SDHCI_CAN_64BIT	0x10000000
213221 
222
+#define SDHCI_CAPABILITIES_1	0x44
214223 #define  SDHCI_SUPPORT_SDR50	0x00000001
215224 #define  SDHCI_SUPPORT_SDR104	0x00000002
216225 #define  SDHCI_SUPPORT_DDR50	0x00000004
217226 #define  SDHCI_DRIVER_TYPE_A	0x00000010
218227 #define  SDHCI_DRIVER_TYPE_C	0x00000020
219228 #define  SDHCI_DRIVER_TYPE_D	0x00000040
220
-#define  SDHCI_RETUNING_TIMER_COUNT_MASK	0x00000F00
221
-#define  SDHCI_RETUNING_TIMER_COUNT_SHIFT	8
229
+#define  SDHCI_RETUNING_TIMER_COUNT_MASK	GENMASK(11, 8)
222230 #define  SDHCI_USE_SDR50_TUNING			0x00002000
223
-#define  SDHCI_RETUNING_MODE_MASK		0x0000C000
224
-#define  SDHCI_RETUNING_MODE_SHIFT		14
225
-#define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
226
-#define  SDHCI_CLOCK_MUL_SHIFT	16
231
+#define  SDHCI_RETUNING_MODE_MASK		GENMASK(15, 14)
232
+#define  SDHCI_CLOCK_MUL_MASK			GENMASK(23, 16)
233
+#define  SDHCI_CAN_DO_ADMA3	0x08000000
227234 #define  SDHCI_SUPPORT_HS400	0x80000000 /* Non-standard */
228235 
229
-#define SDHCI_CAPABILITIES_1	0x44
230
-
231236 #define SDHCI_MAX_CURRENT		0x48
232
-#define  SDHCI_MAX_CURRENT_LIMIT	0xFF
233
-#define  SDHCI_MAX_CURRENT_330_MASK	0x0000FF
234
-#define  SDHCI_MAX_CURRENT_330_SHIFT	0
235
-#define  SDHCI_MAX_CURRENT_300_MASK	0x00FF00
236
-#define  SDHCI_MAX_CURRENT_300_SHIFT	8
237
-#define  SDHCI_MAX_CURRENT_180_MASK	0xFF0000
238
-#define  SDHCI_MAX_CURRENT_180_SHIFT	16
237
+#define  SDHCI_MAX_CURRENT_LIMIT	GENMASK(7, 0)
238
+#define  SDHCI_MAX_CURRENT_330_MASK	GENMASK(7, 0)
239
+#define  SDHCI_MAX_CURRENT_300_MASK	GENMASK(15, 8)
240
+#define  SDHCI_MAX_CURRENT_180_MASK	GENMASK(23, 16)
239241 #define   SDHCI_MAX_CURRENT_MULTIPLIER	4
240242 
241243 /* 4C-4F reserved for more max current */
....@@ -259,12 +261,9 @@
259261 #define SDHCI_PRESET_FOR_SDR104        0x6C
260262 #define SDHCI_PRESET_FOR_DDR50 0x6E
261263 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
262
-#define SDHCI_PRESET_DRV_MASK  0xC000
263
-#define SDHCI_PRESET_DRV_SHIFT  14
264
-#define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
265
-#define SDHCI_PRESET_CLKGEN_SEL_SHIFT	10
266
-#define SDHCI_PRESET_SDCLK_FREQ_MASK   0x3FF
267
-#define SDHCI_PRESET_SDCLK_FREQ_SHIFT	0
264
+#define SDHCI_PRESET_DRV_MASK		GENMASK(15, 14)
265
+#define SDHCI_PRESET_CLKGEN_SEL		BIT(10)
266
+#define SDHCI_PRESET_SDCLK_FREQ_MASK	GENMASK(9, 0)
268267 
269268 #define SDHCI_SLOT_INT_STATUS	0xFC
270269 
....@@ -276,6 +275,9 @@
276275 #define   SDHCI_SPEC_100	0
277276 #define   SDHCI_SPEC_200	1
278277 #define   SDHCI_SPEC_300	2
278
+#define   SDHCI_SPEC_400	3
279
+#define   SDHCI_SPEC_410	4
280
+#define   SDHCI_SPEC_420	5
279281 
280282 /*
281283  * End of controller registers.
....@@ -311,8 +313,14 @@
311313  */
312314 #define SDHCI_ADMA2_DESC_ALIGN	8
313315 
314
-/* ADMA2 64-bit DMA descriptor size */
315
-#define SDHCI_ADMA2_64_DESC_SZ	12
316
+/*
317
+ * ADMA2 64-bit DMA descriptor size
318
+ * According to SD Host Controller spec v4.10, there are two kinds of
319
+ * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
320
+ * Descriptor, if Host Version 4 Enable is set in the Host Control 2
321
+ * register, 128-bit Descriptor will be selected.
322
+ */
323
+#define SDHCI_ADMA2_64_DESC_SZ(host)	((host)->v4_mode ? 16 : 12)
316324 
317325 /*
318326  * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
....@@ -396,6 +404,8 @@
396404 #define SDHCI_QUIRK_BROKEN_CQE				(1<<17)
397405 /* Controller does not like fast PIO transfers */
398406 #define SDHCI_QUIRK_PIO_NEEDS_DELAY			(1<<18)
407
+/* Controller does not have a LED */
408
+#define SDHCI_QUIRK_NO_LED				(1<<19)
399409 /* Controller has to be forced to use block size of 2048 bytes */
400410 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048			(1<<20)
401411 /* Controller cannot do multi-block transfers */
....@@ -458,9 +468,17 @@
458468  * obtainable timeout.
459469  */
460470 #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT			(1<<17)
471
+/*
472
+ * 32-bit block count may not support eMMC where upper bits of CMD23 are used
473
+ * for other purposes.  Consequently we support 16-bit block count by default.
474
+ * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
475
+ * block count.
476
+ */
477
+#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT			(1<<18)
461478 
462479 	int irq;		/* Device IRQ */
463480 	void __iomem *ioaddr;	/* Mapped address */
481
+	phys_addr_t mapbase;	/* physical address base */
464482 	char *bounce_buffer;	/* For packing SDMA reads/writes */
465483 	dma_addr_t bounce_addr;
466484 	unsigned int bounce_buffer_size;
....@@ -488,7 +506,6 @@
488506 #define SDHCI_AUTO_CMD12	(1<<6)	/* Auto CMD12 support */
489507 #define SDHCI_AUTO_CMD23	(1<<7)	/* Auto CMD23 support */
490508 #define SDHCI_PV_ENABLED	(1<<8)	/* Preset value enabled */
491
-#define SDHCI_SDIO_IRQ_ENABLED	(1<<9)	/* SDIO irq enabled */
492509 #define SDHCI_USE_64_BIT_DMA	(1<<12)	/* Use 64-bit DMA */
493510 #define SDHCI_HS400_TUNING	(1<<13)	/* Tuning for HS400 */
494511 #define SDHCI_SIGNALING_330	(1<<14)	/* Host is capable of 3.3V signaling */
....@@ -509,11 +526,14 @@
509526 	bool preset_enabled;	/* Preset is enabled */
510527 	bool pending_reset;	/* Cmd/data reset is pending */
511528 	bool irq_wake_enabled;	/* IRQ wakeup is enabled */
529
+	bool v4_mode;		/* Host Version 4 Enable */
530
+	bool use_external_dma;	/* Host selects to use external DMA */
512531 	bool always_defer_done;	/* Always defer to complete requests */
513532 
514533 	struct mmc_request *mrqs_done[SDHCI_MAX_MRQS];	/* Requests done */
515534 	struct mmc_command *cmd;	/* Current command */
516535 	struct mmc_command *data_cmd;	/* Current data command */
536
+	struct mmc_command *deferred_cmd;	/* Deferred command */
517537 	struct mmc_data *data;	/* Current data request */
518538 	unsigned int data_early:1;	/* Data finished before cmd */
519539 
....@@ -531,17 +551,25 @@
531551 	dma_addr_t adma_addr;	/* Mapped ADMA descr. table */
532552 	dma_addr_t align_addr;	/* Mapped bounce buffer */
533553 
534
-	unsigned int desc_sz;	/* ADMA descriptor size */
554
+	unsigned int desc_sz;	/* ADMA current descriptor size */
555
+	unsigned int alloc_desc_sz;	/* ADMA descr. max size host supports */
535556 
536
-	struct tasklet_struct finish_tasklet;	/* Tasklet structures */
557
+	struct workqueue_struct *complete_wq;	/* Request completion wq */
558
+	struct work_struct	complete_work;	/* Request completion work */
537559 
538560 	struct timer_list timer;	/* Timer for timeouts */
539561 	struct timer_list data_timer;	/* Timer for data timeouts */
562
+
563
+#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
564
+	struct dma_chan *rx_chan;
565
+	struct dma_chan *tx_chan;
566
+#endif
540567 
541568 	u32 caps;		/* CAPABILITY_0 */
542569 	u32 caps1;		/* CAPABILITY_1 */
543570 	bool read_caps;		/* Capability flags have been read */
544571 
572
+	bool sdhci_core_to_disable_vqmmc;  /* sdhci core can disable vqmmc */
545573 	unsigned int            ocr_avail_sdio;	/* OCR bit masks */
546574 	unsigned int            ocr_avail_sd;
547575 	unsigned int            ocr_avail_mmc;
....@@ -563,11 +591,13 @@
563591 
564592 	unsigned int		tuning_count;	/* Timer count for re-tuning */
565593 	unsigned int		tuning_mode;	/* Re-tuning mode supported by host */
594
+	unsigned int		tuning_err;	/* Error code for re-tuning */
566595 #define SDHCI_TUNING_MODE_1	0
567596 #define SDHCI_TUNING_MODE_2	1
568597 #define SDHCI_TUNING_MODE_3	2
569598 	/* Delay (ms) between tuning commands */
570599 	int			tuning_delay;
600
+	int			tuning_loop_count;
571601 
572602 	/* Host SDMA buffer boundary. */
573603 	u32			sdma_boundary;
....@@ -577,7 +607,9 @@
577607 
578608 	u64			data_timeout;
579609 
580
-	unsigned long private[0] ____cacheline_aligned;
610
+	ANDROID_KABI_RESERVE(1);
611
+
612
+	unsigned long private[] ____cacheline_aligned;
581613 };
582614 
583615 struct sdhci_ops {
....@@ -596,6 +628,7 @@
596628 
597629 	u32		(*irq)(struct sdhci_host *host, u32 intmask);
598630 
631
+	int		(*set_dma_mask)(struct sdhci_host *host);
599632 	int		(*enable_dma)(struct sdhci_host *host);
600633 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
601634 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
....@@ -617,8 +650,14 @@
617650 	void	(*voltage_switch)(struct sdhci_host *host);
618651 	void	(*adma_write_desc)(struct sdhci_host *host, void **desc,
619652 				   dma_addr_t addr, int len, unsigned int cmd);
653
+	void	(*copy_to_bounce_buffer)(struct sdhci_host *host,
654
+					 struct mmc_data *data,
655
+					 unsigned int length);
620656 	void	(*request_done)(struct sdhci_host *host,
621657 				struct mmc_request *mrq);
658
+	void    (*dump_vendor_regs)(struct sdhci_host *host);
659
+
660
+	ANDROID_KABI_RESERVE(1);
622661 };
623662 
624663 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
....@@ -714,23 +753,17 @@
714753 }
715754 
716755 void sdhci_card_detect(struct sdhci_host *host);
717
-void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps,
718
-		       u32 *caps1);
756
+void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
757
+		       const u32 *caps, const u32 *caps1);
719758 int sdhci_setup_host(struct sdhci_host *host);
720759 void sdhci_cleanup_host(struct sdhci_host *host);
721760 int __sdhci_add_host(struct sdhci_host *host);
722761 int sdhci_add_host(struct sdhci_host *host);
723762 void sdhci_remove_host(struct sdhci_host *host, int dead);
724
-void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
725763 
726764 static inline void sdhci_read_caps(struct sdhci_host *host)
727765 {
728766 	__sdhci_read_caps(host, NULL, NULL, NULL);
729
-}
730
-
731
-static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
732
-{
733
-	return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
734767 }
735768 
736769 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
....@@ -739,9 +772,13 @@
739772 void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
740773 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
741774 		     unsigned short vdd);
775
+void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
776
+				     unsigned char mode,
777
+				     unsigned short vdd);
742778 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
743779 			   unsigned short vdd);
744780 void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq);
781
+int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
745782 void sdhci_set_bus_width(struct sdhci_host *host, int width);
746783 void sdhci_reset(struct sdhci_host *host, u8 mask);
747784 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
....@@ -757,7 +794,7 @@
757794 int sdhci_suspend_host(struct sdhci_host *host);
758795 int sdhci_resume_host(struct sdhci_host *host);
759796 int sdhci_runtime_suspend_host(struct sdhci_host *host);
760
-int sdhci_runtime_resume_host(struct sdhci_host *host);
797
+int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
761798 #endif
762799 
763800 void sdhci_cqe_enable(struct mmc_host *mmc);
....@@ -766,10 +803,15 @@
766803 		   int *data_error);
767804 
768805 void sdhci_dumpregs(struct sdhci_host *host);
806
+void sdhci_enable_v4_mode(struct sdhci_host *host);
769807 
770808 void sdhci_start_tuning(struct sdhci_host *host);
771809 void sdhci_end_tuning(struct sdhci_host *host);
772810 void sdhci_reset_tuning(struct sdhci_host *host);
773811 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode);
812
+void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode);
813
+void sdhci_switch_external_dma(struct sdhci_host *host, bool en);
814
+void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable);
815
+void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);
774816 
775817 #endif /* __SDHCI_HW_H */