~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,19 +1,17 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3	4	*
4	5	* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5		- *
6		- * This program is free software; you can redistribute it and/or modify
7		- * it under the terms of the GNU General Public License as published by
8		- * the Free Software Foundation; either version 2 of the License, or (at
9		- * your option) any later version.
10	6	*
11	7	* Thanks to the following companies for their support:
12	8	*
13	9	* - JMicron (hardware and technical support)
14	10	*/
15	11
	12	+#include <linux/bitfield.h>
16	13	#include <linux/delay.h>
	14	+#include <linux/dmaengine.h>
17	15	#include <linux/ktime.h>
18	16	#include <linux/highmem.h>
19	17	#include <linux/io.h>
..	..	@@ -35,6 +33,8 @@
35	33	#include <linux/mmc/sdio.h>
36	34	#include <linux/mmc/slot-gpio.h>
37	35
	36	+#include <trace/hooks/mmc_core.h>
	37	+
38	38	#include "sdhci.h"
39	39
40	40	#define DRIVER_NAME "sdhci"
..	..	@@ -50,9 +50,9 @@
50	50	static unsigned int debug_quirks = 0;
51	51	static unsigned int debug_quirks2;
52	52
53		-static void sdhci_finish_data(struct sdhci_host *);
54		-
55	53	static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
	54	+
	55	+static bool sdhci_send_command(struct sdhci_host host, struct mmc_command cmd);
56	56
57	57	void sdhci_dumpregs(struct sdhci_host *host)
58	58	{
..	..	@@ -113,6 +113,9 @@
113	113	}
114	114	}
115	115
	116	+ if (host->ops->dump_vendor_regs)
	117	+ host->ops->dump_vendor_regs(host);
	118	+
116	119	SDHCI_DUMP("============================================\n");
117	120	}
118	121	EXPORT_SYMBOL_GPL(sdhci_dumpregs);
..	..	@@ -122,6 +125,29 @@
122	125	* Low level functions *
123	126	* *
124	127	\*****************************************************************************/
	128	+
	129	+static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
	130	+{
	131	+ u16 ctrl2;
	132	+
	133	+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	134	+ if (ctrl2 & SDHCI_CTRL_V4_MODE)
	135	+ return;
	136	+
	137	+ ctrl2 \|= SDHCI_CTRL_V4_MODE;
	138	+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
	139	+}
	140	+
	141	+/*
	142	+ * This can be called before sdhci_add_host() by Vendor's host controller
	143	+ * driver to enable v4 mode if supported.
	144	+ */
	145	+void sdhci_enable_v4_mode(struct sdhci_host *host)
	146	+{
	147	+ host->v4_mode = true;
	148	+ sdhci_do_enable_v4_mode(host);
	149	+}
	150	+EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode);
125	151
126	152	static inline bool sdhci_data_line_cmd(struct mmc_command *cmd)
127	153	{
..	..	@@ -247,16 +273,68 @@
247	273	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
248	274	}
249	275
	276	+static void sdhci_config_dma(struct sdhci_host *host)
	277	+{
	278	+ u8 ctrl;
	279	+ u16 ctrl2;
	280	+
	281	+ if (host->version < SDHCI_SPEC_200)
	282	+ return;
	283	+
	284	+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
	285	+
	286	+ /*
	287	+ * Always adjust the DMA selection as some controllers
	288	+ * (e.g. JMicron) can't do PIO properly when the selection
	289	+ * is ADMA.
	290	+ */
	291	+ ctrl &= ~SDHCI_CTRL_DMA_MASK;
	292	+ if (!(host->flags & SDHCI_REQ_USE_DMA))
	293	+ goto out;
	294	+
	295	+ /* Note if DMA Select is zero then SDMA is selected */
	296	+ if (host->flags & SDHCI_USE_ADMA)
	297	+ ctrl \|= SDHCI_CTRL_ADMA32;
	298	+
	299	+ if (host->flags & SDHCI_USE_64_BIT_DMA) {
	300	+ /*
	301	+ * If v4 mode, all supported DMA can be 64-bit addressing if
	302	+ * controller supports 64-bit system address, otherwise only
	303	+ * ADMA can support 64-bit addressing.
	304	+ */
	305	+ if (host->v4_mode) {
	306	+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	307	+ ctrl2 \|= SDHCI_CTRL_64BIT_ADDR;
	308	+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
	309	+ } else if (host->flags & SDHCI_USE_ADMA) {
	310	+ /*
	311	+ * Don't need to undo SDHCI_CTRL_ADMA32 in order to
	312	+ * set SDHCI_CTRL_ADMA64.
	313	+ */
	314	+ ctrl \|= SDHCI_CTRL_ADMA64;
	315	+ }
	316	+ }
	317	+
	318	+out:
	319	+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
	320	+}
	321	+
250	322	static void sdhci_init(struct sdhci_host *host, int soft)
251	323	{
252	324	struct mmc_host *mmc = host->mmc;
	325	+ unsigned long flags;
253	326
254	327	if (soft)
255	328	sdhci_do_reset(host, SDHCI_RESET_CMD \| SDHCI_RESET_DATA);
256	329	else
257	330	sdhci_do_reset(host, SDHCI_RESET_ALL);
258	331
	332	+ if (host->v4_mode)
	333	+ sdhci_do_enable_v4_mode(host);
	334	+
	335	+ spin_lock_irqsave(&host->lock, flags);
259	336	sdhci_set_default_irqs(host);
	337	+ spin_unlock_irqrestore(&host->lock, flags);
260	338
261	339	host->cqe_on = false;
262	340
..	..	@@ -269,13 +347,27 @@
269	347
270	348	static void sdhci_reinit(struct sdhci_host *host)
271	349	{
	350	+ u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE \| SDHCI_INT_CARD_INSERT);
	351	+
272	352	sdhci_init(host, 0);
273	353	sdhci_enable_card_detection(host);
	354	+
	355	+ /*
	356	+ * A change to the card detect bits indicates a change in present state,
	357	+ * refer sdhci_set_card_detection(). A card detect interrupt might have
	358	+ * been missed while the host controller was being reset, so trigger a
	359	+ * rescan to check.
	360	+ */
	361	+ if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE \| SDHCI_INT_CARD_INSERT)))
	362	+ mmc_detect_change(host->mmc, msecs_to_jiffies(200));
274	363	}
275	364
276	365	static void __sdhci_led_activate(struct sdhci_host *host)
277	366	{
278	367	u8 ctrl;
	368	+
	369	+ if (host->quirks & SDHCI_QUIRK_NO_LED)
	370	+ return;
279	371
280	372	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
281	373	ctrl \|= SDHCI_CTRL_LED;
..	..	@@ -285,6 +377,9 @@
285	377	static void __sdhci_led_deactivate(struct sdhci_host *host)
286	378	{
287	379	u8 ctrl;
	380	+
	381	+ if (host->quirks & SDHCI_QUIRK_NO_LED)
	382	+ return;
288	383
289	384	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
290	385	ctrl &= ~SDHCI_CTRL_LED;
..	..	@@ -315,6 +410,9 @@
315	410	{
316	411	struct mmc_host *mmc = host->mmc;
317	412
	413	+ if (host->quirks & SDHCI_QUIRK_NO_LED)
	414	+ return 0;
	415	+
318	416	snprintf(host->led_name, sizeof(host->led_name),
319	417	"%s::", mmc_hostname(mmc));
320	418
..	..	@@ -328,6 +426,9 @@
328	426
329	427	static void sdhci_led_unregister(struct sdhci_host *host)
330	428	{
	429	+ if (host->quirks & SDHCI_QUIRK_NO_LED)
	430	+ return;
	431	+
331	432	led_classdev_unregister(&host->led);
332	433	}
333	434
..	..	@@ -362,6 +463,28 @@
362	463
363	464	#endif
364	465
	466	+static void sdhci_mod_timer(struct sdhci_host host, struct mmc_request mrq,
	467	+ unsigned long timeout)
	468	+{
	469	+ if (sdhci_data_line_cmd(mrq->cmd))
	470	+ mod_timer(&host->data_timer, timeout);
	471	+ else
	472	+ mod_timer(&host->timer, timeout);
	473	+}
	474	+
	475	+static void sdhci_del_timer(struct sdhci_host host, struct mmc_request mrq)
	476	+{
	477	+ if (sdhci_data_line_cmd(mrq->cmd))
	478	+ del_timer(&host->data_timer);
	479	+ else
	480	+ del_timer(&host->timer);
	481	+}
	482	+
	483	+static inline bool sdhci_has_requests(struct sdhci_host *host)
	484	+{
	485	+ return host->cmd \|\| host->data_cmd;
	486	+}
	487	+
365	488	/*****************************************************************************\
366	489	* *
367	490	* Core functions *
..	..	@@ -372,7 +495,7 @@
372	495	{
373	496	unsigned long flags;
374	497	size_t blksize, len, chunk;
375		- u32 uninitialized_var(scratch);
	498	+ u32 scratch;
376	499	u8 *buf;
377	500
378	501	DBG("PIO reading\n");
..	..	@@ -519,9 +642,13 @@
519	642	}
520	643	if (mmc_get_dma_dir(data) == DMA_TO_DEVICE) {
521	644	/* Copy the data to the bounce buffer */
522		- sg_copy_to_buffer(data->sg, data->sg_len,
523		- host->bounce_buffer,
524		- length);
	645	+ if (host->ops->copy_to_bounce_buffer) {
	646	+ host->ops->copy_to_bounce_buffer(host,
	647	+ data, length);
	648	+ } else {
	649	+ sg_copy_to_buffer(data->sg, data->sg_len,
	650	+ host->bounce_buffer, length);
	651	+ }
525	652	}
526	653	/* Switch ownership to the DMA */
527	654	dma_sync_single_for_device(host->mmc->parent,
..	..	@@ -566,10 +693,10 @@
566	693	/* 32-bit and 64-bit descriptors have these members in same position */
567	694	dma_desc->cmd = cpu_to_le16(cmd);
568	695	dma_desc->len = cpu_to_le16(len);
569		- dma_desc->addr_lo = cpu_to_le32((u32)addr);
	696	+ dma_desc->addr_lo = cpu_to_le32(lower_32_bits(addr));
570	697
571	698	if (host->flags & SDHCI_USE_64_BIT_DMA)
572		- dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
	699	+ dma_desc->addr_hi = cpu_to_le32(upper_32_bits(addr));
573	700
574	701	*desc += host->desc_sz;
575	702	}
..	..	@@ -714,12 +841,27 @@
714	841	}
715	842	}
716	843
717		-static u32 sdhci_sdma_address(struct sdhci_host *host)
	844	+static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
	845	+{
	846	+ sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
	847	+ if (host->flags & SDHCI_USE_64_BIT_DMA)
	848	+ sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
	849	+}
	850	+
	851	+static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
718	852	{
719	853	if (host->bounce_buffer)
720	854	return host->bounce_addr;
721	855	else
722	856	return sg_dma_address(host->data->sg);
	857	+}
	858	+
	859	+static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
	860	+{
	861	+ if (host->v4_mode)
	862	+ sdhci_set_adma_addr(host, addr);
	863	+ else
	864	+ sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
723	865	}
724	866
725	867	static unsigned int sdhci_target_timeout(struct sdhci_host *host,
..	..	@@ -788,7 +930,7 @@
788	930	bool *too_big)
789	931	{
790	932	u8 count;
791		- struct mmc_data *data = cmd->data;
	933	+ struct mmc_data *data;
792	934	unsigned target_timeout, current_timeout;
793	935
794	936	*too_big = true;
..	..	@@ -802,6 +944,11 @@
802	944	if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
803	945	return 0xE;
804	946
	947	+ /* Unspecified command, asume max */
	948	+ if (cmd == NULL)
	949	+ return 0xE;
	950	+
	951	+ data = cmd->data;
805	952	/* Unspecified timeout, assume max */
806	953	if (!data && !cmd->busy_timeout)
807	954	return 0xE;
..	..	@@ -859,7 +1006,7 @@
859	1006	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
860	1007	}
861	1008
862		-static void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
	1009	+void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
863	1010	{
864	1011	if (enable)
865	1012	host->ier \|= SDHCI_INT_DATA_TIMEOUT;
..	..	@@ -868,43 +1015,36 @@
868	1015	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
869	1016	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
870	1017	}
	1018	+EXPORT_SYMBOL_GPL(sdhci_set_data_timeout_irq);
	1019	+
	1020	+void __sdhci_set_timeout(struct sdhci_host host, struct mmc_command cmd)
	1021	+{
	1022	+ bool too_big = false;
	1023	+ u8 count = sdhci_calc_timeout(host, cmd, &too_big);
	1024	+
	1025	+ if (too_big &&
	1026	+ host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
	1027	+ sdhci_calc_sw_timeout(host, cmd);
	1028	+ sdhci_set_data_timeout_irq(host, false);
	1029	+ } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
	1030	+ sdhci_set_data_timeout_irq(host, true);
	1031	+ }
	1032	+
	1033	+ sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
	1034	+}
	1035	+EXPORT_SYMBOL_GPL(__sdhci_set_timeout);
871	1036
872	1037	static void sdhci_set_timeout(struct sdhci_host host, struct mmc_command cmd)
873	1038	{
874		- u8 count;
875		-
876		- if (host->ops->set_timeout) {
	1039	+ if (host->ops->set_timeout)
877	1040	host->ops->set_timeout(host, cmd);
878		- } else {
879		- bool too_big = false;
880		-
881		- count = sdhci_calc_timeout(host, cmd, &too_big);
882		-
883		- if (too_big &&
884		- host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
885		- sdhci_calc_sw_timeout(host, cmd);
886		- sdhci_set_data_timeout_irq(host, false);
887		- } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
888		- sdhci_set_data_timeout_irq(host, true);
889		- }
890		-
891		- sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
892		- }
	1041	+ else
	1042	+ __sdhci_set_timeout(host, cmd);
893	1043	}
894	1044
895		-static void sdhci_prepare_data(struct sdhci_host host, struct mmc_command cmd)
	1045	+static void sdhci_initialize_data(struct sdhci_host *host,
	1046	+ struct mmc_data *data)
896	1047	{
897		- u8 ctrl;
898		- struct mmc_data *data = cmd->data;
899		-
900		- host->data_timeout = 0;
901		-
902		- if (sdhci_data_line_cmd(cmd))
903		- sdhci_set_timeout(host, cmd);
904		-
905		- if (!data)
906		- return;
907		-
908	1048	WARN_ON(host->data);
909	1049
910	1050	/* Sanity checks */
..	..	@@ -915,6 +1055,34 @@
915	1055	host->data = data;
916	1056	host->data_early = 0;
917	1057	host->data->bytes_xfered = 0;
	1058	+}
	1059	+
	1060	+static inline void sdhci_set_block_info(struct sdhci_host *host,
	1061	+ struct mmc_data *data)
	1062	+{
	1063	+ /* Set the DMA boundary value and block size */
	1064	+ sdhci_writew(host,
	1065	+ SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
	1066	+ SDHCI_BLOCK_SIZE);
	1067	+ /*
	1068	+ * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
	1069	+ * can be supported, in that case 16-bit block count register must be 0.
	1070	+ */
	1071	+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
	1072	+ (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
	1073	+ if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
	1074	+ sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
	1075	+ sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
	1076	+ } else {
	1077	+ sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
	1078	+ }
	1079	+}
	1080	+
	1081	+static void sdhci_prepare_data(struct sdhci_host host, struct mmc_command cmd)
	1082	+{
	1083	+ struct mmc_data *data = cmd->data;
	1084	+
	1085	+ sdhci_initialize_data(host, data);
918	1086
919	1087	if (host->flags & (SDHCI_USE_SDMA \| SDHCI_USE_ADMA)) {
920	1088	struct scatterlist *sg;
..	..	@@ -966,6 +1134,8 @@
966	1134	}
967	1135	}
968	1136
	1137	+ sdhci_config_dma(host);
	1138	+
969	1139	if (host->flags & SDHCI_REQ_USE_DMA) {
970	1140	int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
971	1141
..	..	@@ -978,37 +1148,11 @@
978	1148	host->flags &= ~SDHCI_REQ_USE_DMA;
979	1149	} else if (host->flags & SDHCI_USE_ADMA) {
980	1150	sdhci_adma_table_pre(host, data, sg_cnt);
981		-
982		- sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
983		- if (host->flags & SDHCI_USE_64_BIT_DMA)
984		- sdhci_writel(host,
985		- (u64)host->adma_addr >> 32,
986		- SDHCI_ADMA_ADDRESS_HI);
	1151	+ sdhci_set_adma_addr(host, host->adma_addr);
987	1152	} else {
988	1153	WARN_ON(sg_cnt != 1);
989		- sdhci_writel(host, sdhci_sdma_address(host),
990		- SDHCI_DMA_ADDRESS);
	1154	+ sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
991	1155	}
992		- }
993		-
994		- /*
995		- * Always adjust the DMA selection as some controllers
996		- * (e.g. JMicron) can't do PIO properly when the selection
997		- * is ADMA.
998		- */
999		- if (host->version >= SDHCI_SPEC_200) {
1000		- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1001		- ctrl &= ~SDHCI_CTRL_DMA_MASK;
1002		- if ((host->flags & SDHCI_REQ_USE_DMA) &&
1003		- (host->flags & SDHCI_USE_ADMA)) {
1004		- if (host->flags & SDHCI_USE_64_BIT_DMA)
1005		- ctrl \|= SDHCI_CTRL_ADMA64;
1006		- else
1007		- ctrl \|= SDHCI_CTRL_ADMA32;
1008		- } else {
1009		- ctrl \|= SDHCI_CTRL_SDMA;
1010		- }
1011		- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1012	1156	}
1013	1157
1014	1158	if (!(host->flags & SDHCI_REQ_USE_DMA)) {
..	..	@@ -1025,17 +1169,249 @@
1025	1169
1026	1170	sdhci_set_transfer_irqs(host);
1027	1171
1028		- /* Set the DMA boundary value and block size */
1029		- sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1030		- SDHCI_BLOCK_SIZE);
1031		- sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
	1172	+ sdhci_set_block_info(host, data);
1032	1173	}
	1174	+
	1175	+#if IS_ENABLED(CONFIG_MMC_SDHCI_EXTERNAL_DMA)
	1176	+
	1177	+static int sdhci_external_dma_init(struct sdhci_host *host)
	1178	+{
	1179	+ int ret = 0;
	1180	+ struct mmc_host *mmc = host->mmc;
	1181	+
	1182	+ host->tx_chan = dma_request_chan(mmc->parent, "tx");
	1183	+ if (IS_ERR(host->tx_chan)) {
	1184	+ ret = PTR_ERR(host->tx_chan);
	1185	+ if (ret != -EPROBE_DEFER)
	1186	+ pr_warn("Failed to request TX DMA channel.\n");
	1187	+ host->tx_chan = NULL;
	1188	+ return ret;
	1189	+ }
	1190	+
	1191	+ host->rx_chan = dma_request_chan(mmc->parent, "rx");
	1192	+ if (IS_ERR(host->rx_chan)) {
	1193	+ if (host->tx_chan) {
	1194	+ dma_release_channel(host->tx_chan);
	1195	+ host->tx_chan = NULL;
	1196	+ }
	1197	+
	1198	+ ret = PTR_ERR(host->rx_chan);
	1199	+ if (ret != -EPROBE_DEFER)
	1200	+ pr_warn("Failed to request RX DMA channel.\n");
	1201	+ host->rx_chan = NULL;
	1202	+ }
	1203	+
	1204	+ return ret;
	1205	+}
	1206	+
	1207	+static struct dma_chan sdhci_external_dma_channel(struct sdhci_host host,
	1208	+ struct mmc_data *data)
	1209	+{
	1210	+ return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
	1211	+}
	1212	+
	1213	+static int sdhci_external_dma_setup(struct sdhci_host *host,
	1214	+ struct mmc_command *cmd)
	1215	+{
	1216	+ int ret, i;
	1217	+ enum dma_transfer_direction dir;
	1218	+ struct dma_async_tx_descriptor *desc;
	1219	+ struct mmc_data *data = cmd->data;
	1220	+ struct dma_chan *chan;
	1221	+ struct dma_slave_config cfg;
	1222	+ dma_cookie_t cookie;
	1223	+ int sg_cnt;
	1224	+
	1225	+ if (!host->mapbase)
	1226	+ return -EINVAL;
	1227	+
	1228	+ memset(&cfg, 0, sizeof(cfg));
	1229	+ cfg.src_addr = host->mapbase + SDHCI_BUFFER;
	1230	+ cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
	1231	+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	1232	+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	1233	+ cfg.src_maxburst = data->blksz / 4;
	1234	+ cfg.dst_maxburst = data->blksz / 4;
	1235	+
	1236	+ /* Sanity check: all the SG entries must be aligned by block size. */
	1237	+ for (i = 0; i < data->sg_len; i++) {
	1238	+ if ((data->sg + i)->length % data->blksz)
	1239	+ return -EINVAL;
	1240	+ }
	1241	+
	1242	+ chan = sdhci_external_dma_channel(host, data);
	1243	+
	1244	+ ret = dmaengine_slave_config(chan, &cfg);
	1245	+ if (ret)
	1246	+ return ret;
	1247	+
	1248	+ sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
	1249	+ if (sg_cnt <= 0)
	1250	+ return -EINVAL;
	1251	+
	1252	+ dir = data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
	1253	+ desc = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, dir,
	1254	+ DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	1255	+ if (!desc)
	1256	+ return -EINVAL;
	1257	+
	1258	+ desc->callback = NULL;
	1259	+ desc->callback_param = NULL;
	1260	+
	1261	+ cookie = dmaengine_submit(desc);
	1262	+ if (dma_submit_error(cookie))
	1263	+ ret = cookie;
	1264	+
	1265	+ return ret;
	1266	+}
	1267	+
	1268	+static void sdhci_external_dma_release(struct sdhci_host *host)
	1269	+{
	1270	+ if (host->tx_chan) {
	1271	+ dma_release_channel(host->tx_chan);
	1272	+ host->tx_chan = NULL;
	1273	+ }
	1274	+
	1275	+ if (host->rx_chan) {
	1276	+ dma_release_channel(host->rx_chan);
	1277	+ host->rx_chan = NULL;
	1278	+ }
	1279	+
	1280	+ sdhci_switch_external_dma(host, false);
	1281	+}
	1282	+
	1283	+static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
	1284	+ struct mmc_command *cmd)
	1285	+{
	1286	+ struct mmc_data *data = cmd->data;
	1287	+
	1288	+ sdhci_initialize_data(host, data);
	1289	+
	1290	+ host->flags \|= SDHCI_REQ_USE_DMA;
	1291	+ sdhci_set_transfer_irqs(host);
	1292	+
	1293	+ sdhci_set_block_info(host, data);
	1294	+}
	1295	+
	1296	+static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
	1297	+ struct mmc_command *cmd)
	1298	+{
	1299	+ if (!sdhci_external_dma_setup(host, cmd)) {
	1300	+ __sdhci_external_dma_prepare_data(host, cmd);
	1301	+ } else {
	1302	+ sdhci_external_dma_release(host);
	1303	+ pr_err("%s: Cannot use external DMA, switch to the DMA/PIO which standard SDHCI provides.\n",
	1304	+ mmc_hostname(host->mmc));
	1305	+ sdhci_prepare_data(host, cmd);
	1306	+ }
	1307	+}
	1308	+
	1309	+static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
	1310	+ struct mmc_command *cmd)
	1311	+{
	1312	+ struct dma_chan *chan;
	1313	+
	1314	+ if (!cmd->data)
	1315	+ return;
	1316	+
	1317	+ chan = sdhci_external_dma_channel(host, cmd->data);
	1318	+ if (chan)
	1319	+ dma_async_issue_pending(chan);
	1320	+}
	1321	+
	1322	+#else
	1323	+
	1324	+static inline int sdhci_external_dma_init(struct sdhci_host *host)
	1325	+{
	1326	+ return -EOPNOTSUPP;
	1327	+}
	1328	+
	1329	+static inline void sdhci_external_dma_release(struct sdhci_host *host)
	1330	+{
	1331	+}
	1332	+
	1333	+static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
	1334	+ struct mmc_command *cmd)
	1335	+{
	1336	+ /* This should never happen */
	1337	+ WARN_ON_ONCE(1);
	1338	+}
	1339	+
	1340	+static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
	1341	+ struct mmc_command *cmd)
	1342	+{
	1343	+}
	1344	+
	1345	+static inline struct dma_chan sdhci_external_dma_channel(struct sdhci_host host,
	1346	+ struct mmc_data *data)
	1347	+{
	1348	+ return NULL;
	1349	+}
	1350	+
	1351	+#endif
	1352	+
	1353	+void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
	1354	+{
	1355	+ host->use_external_dma = en;
	1356	+}
	1357	+EXPORT_SYMBOL_GPL(sdhci_switch_external_dma);
1033	1358
1034	1359	static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1035	1360	struct mmc_request *mrq)
1036	1361	{
1037	1362	return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1038	1363	!mrq->cap_cmd_during_tfr;
	1364	+}
	1365	+
	1366	+static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
	1367	+ struct mmc_request *mrq)
	1368	+{
	1369	+ return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
	1370	+}
	1371	+
	1372	+static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
	1373	+ struct mmc_request *mrq)
	1374	+{
	1375	+ return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
	1376	+}
	1377	+
	1378	+static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
	1379	+ struct mmc_command *cmd,
	1380	+ u16 *mode)
	1381	+{
	1382	+ bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
	1383	+ (cmd->opcode != SD_IO_RW_EXTENDED);
	1384	+ bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
	1385	+ u16 ctrl2;
	1386	+
	1387	+ /*
	1388	+ * In case of Version 4.10 or later, use of 'Auto CMD Auto
	1389	+ * Select' is recommended rather than use of 'Auto CMD12
	1390	+ * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
	1391	+ * here because some controllers (e.g sdhci-of-dwmshc) expect it.
	1392	+ */
	1393	+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
	1394	+ (use_cmd12 \|\| use_cmd23)) {
	1395	+ *mode \|= SDHCI_TRNS_AUTO_SEL;
	1396	+
	1397	+ ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	1398	+ if (use_cmd23)
	1399	+ ctrl2 \|= SDHCI_CMD23_ENABLE;
	1400	+ else
	1401	+ ctrl2 &= ~SDHCI_CMD23_ENABLE;
	1402	+ sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
	1403	+
	1404	+ return;
	1405	+ }
	1406	+
	1407	+ /*
	1408	+ * If we are sending CMD23, CMD12 never gets sent
	1409	+ * on successful completion (so no Auto-CMD12).
	1410	+ */
	1411	+ if (use_cmd12)
	1412	+ *mode \|= SDHCI_TRNS_AUTO_CMD12;
	1413	+ else if (use_cmd23)
	1414	+ *mode \|= SDHCI_TRNS_AUTO_CMD23;
1039	1415	}
1040	1416
1041	1417	static void sdhci_set_transfer_mode(struct sdhci_host *host,
..	..	@@ -1066,17 +1442,9 @@
1066	1442
1067	1443	if (mmc_op_multi(cmd->opcode) \|\| data->blocks > 1) {
1068	1444	mode = SDHCI_TRNS_BLK_CNT_EN \| SDHCI_TRNS_MULTI;
1069		- /*
1070		- * If we are sending CMD23, CMD12 never gets sent
1071		- * on successful completion (so no Auto-CMD12).
1072		- */
1073		- if (sdhci_auto_cmd12(host, cmd->mrq) &&
1074		- (cmd->opcode != SD_IO_RW_EXTENDED))
1075		- mode \|= SDHCI_TRNS_AUTO_CMD12;
1076		- else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
1077		- mode \|= SDHCI_TRNS_AUTO_CMD23;
	1445	+ sdhci_auto_cmd_select(host, cmd, &mode);
	1446	+ if (sdhci_auto_cmd23(host, cmd->mrq))
1078	1447	sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1079		- }
1080	1448	}
1081	1449
1082	1450	if (data->flags & MMC_DATA_READ)
..	..	@@ -1096,7 +1464,7 @@
1096	1464	(host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1097	1465	}
1098	1466
1099		-static void __sdhci_finish_mrq(struct sdhci_host host, struct mmc_request mrq)
	1467	+static void sdhci_set_mrq_done(struct sdhci_host host, struct mmc_request mrq)
1100	1468	{
1101	1469	int i;
1102	1470
..	..	@@ -1115,11 +1483,9 @@
1115	1483	}
1116	1484
1117	1485	WARN_ON(i >= SDHCI_MAX_MRQS);
1118		-
1119		- tasklet_schedule(&host->finish_tasklet);
1120	1486	}
1121	1487
1122		-static void sdhci_finish_mrq(struct sdhci_host host, struct mmc_request mrq)
	1488	+static void __sdhci_finish_mrq(struct sdhci_host host, struct mmc_request mrq)
1123	1489	{
1124	1490	if (host->cmd && host->cmd->mrq == mrq)
1125	1491	host->cmd = NULL;
..	..	@@ -1127,16 +1493,31 @@
1127	1493	if (host->data_cmd && host->data_cmd->mrq == mrq)
1128	1494	host->data_cmd = NULL;
1129	1495
	1496	+ if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
	1497	+ host->deferred_cmd = NULL;
	1498	+
1130	1499	if (host->data && host->data->mrq == mrq)
1131	1500	host->data = NULL;
1132	1501
1133	1502	if (sdhci_needs_reset(host, mrq))
1134	1503	host->pending_reset = true;
1135	1504
1136		- __sdhci_finish_mrq(host, mrq);
	1505	+ sdhci_set_mrq_done(host, mrq);
	1506	+
	1507	+ sdhci_del_timer(host, mrq);
	1508	+
	1509	+ if (!sdhci_has_requests(host))
	1510	+ sdhci_led_deactivate(host);
1137	1511	}
1138	1512
1139		-static void sdhci_finish_data(struct sdhci_host *host)
	1513	+static void sdhci_finish_mrq(struct sdhci_host host, struct mmc_request mrq)
	1514	+{
	1515	+ __sdhci_finish_mrq(host, mrq);
	1516	+
	1517	+ queue_work(host->complete_wq, &host->complete_work);
	1518	+}
	1519	+
	1520	+static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1140	1521	{
1141	1522	struct mmc_command *data_cmd = host->data_cmd;
1142	1523	struct mmc_data *data = host->data;
..	..	@@ -1172,47 +1553,47 @@
1172	1553
1173	1554	/*
1174	1555	* Need to send CMD12 if -
1175		- * a) open-ended multiblock transfer (no CMD23)
	1556	+ * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
1176	1557	* b) error in multiblock transfer
1177	1558	*/
1178	1559	if (data->stop &&
1179		- (data->error \|\|
1180		- !data->mrq->sbc)) {
	1560	+ ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) \|\|
	1561	+ data->error)) {
1181	1562	/*
1182	1563	* 'cap_cmd_during_tfr' request must not use the command line
1183	1564	* after mmc_command_done() has been called. It is upper layer's
1184	1565	* responsibility to send the stop command if required.
1185	1566	*/
1186	1567	if (data->mrq->cap_cmd_during_tfr) {
1187		- sdhci_finish_mrq(host, data->mrq);
	1568	+ __sdhci_finish_mrq(host, data->mrq);
1188	1569	} else {
1189	1570	/* Avoid triggering warning in sdhci_send_command() */
1190	1571	host->cmd = NULL;
1191		- sdhci_send_command(host, data->stop);
	1572	+ if (!sdhci_send_command(host, data->stop)) {
	1573	+ if (sw_data_timeout) {
	1574	+ /*
	1575	+ * This is anyway a sw data timeout, so
	1576	+ * give up now.
	1577	+ */
	1578	+ data->stop->error = -EIO;
	1579	+ __sdhci_finish_mrq(host, data->mrq);
	1580	+ } else {
	1581	+ WARN_ON(host->deferred_cmd);
	1582	+ host->deferred_cmd = data->stop;
	1583	+ }
	1584	+ }
1192	1585	}
1193	1586	} else {
1194		- sdhci_finish_mrq(host, data->mrq);
	1587	+ __sdhci_finish_mrq(host, data->mrq);
1195	1588	}
1196	1589	}
1197	1590
1198		-static void sdhci_mod_timer(struct sdhci_host host, struct mmc_request mrq,
1199		- unsigned long timeout)
	1591	+static void sdhci_finish_data(struct sdhci_host *host)
1200	1592	{
1201		- if (sdhci_data_line_cmd(mrq->cmd))
1202		- mod_timer(&host->data_timer, timeout);
1203		- else
1204		- mod_timer(&host->timer, timeout);
	1593	+ __sdhci_finish_data(host, false);
1205	1594	}
1206	1595
1207		-static void sdhci_del_timer(struct sdhci_host host, struct mmc_request mrq)
1208		-{
1209		- if (sdhci_data_line_cmd(mrq->cmd))
1210		- del_timer(&host->data_timer);
1211		- else
1212		- del_timer(&host->timer);
1213		-}
1214		-
1215		-void sdhci_send_command(struct sdhci_host host, struct mmc_command cmd)
	1596	+static bool sdhci_send_command(struct sdhci_host host, struct mmc_command cmd)
1216	1597	{
1217	1598	int flags;
1218	1599	u32 mask;
..	..	@@ -1227,9 +1608,6 @@
1227	1608	cmd->opcode == MMC_STOP_TRANSMISSION)
1228	1609	cmd->flags \|= MMC_RSP_BUSY;
1229	1610
1230		- /* Wait max 10 ms */
1231		- timeout = 10;
1232		-
1233	1611	mask = SDHCI_CMD_INHIBIT;
1234	1612	if (sdhci_data_line_cmd(cmd))
1235	1613	mask \|= SDHCI_DATA_INHIBIT;
..	..	@@ -1239,37 +1617,36 @@
1239	1617	if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
1240	1618	mask &= ~SDHCI_DATA_INHIBIT;
1241	1619
1242		- while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1243		- if (timeout == 0) {
1244		- pr_err("%s: Controller never released inhibit bit(s).\n",
1245		- mmc_hostname(host->mmc));
1246		- sdhci_dumpregs(host);
1247		- cmd->error = -EIO;
1248		- sdhci_finish_mrq(host, cmd->mrq);
1249		- return;
1250		- }
1251		- timeout--;
1252		- mdelay(1);
1253		- }
	1620	+ if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
	1621	+ return false;
1254	1622
1255	1623	host->cmd = cmd;
	1624	+ host->data_timeout = 0;
1256	1625	if (sdhci_data_line_cmd(cmd)) {
1257	1626	WARN_ON(host->data_cmd);
1258	1627	host->data_cmd = cmd;
	1628	+ sdhci_set_timeout(host, cmd);
1259	1629	}
1260	1630
1261		- sdhci_prepare_data(host, cmd);
	1631	+ if (cmd->data) {
	1632	+ if (host->use_external_dma)
	1633	+ sdhci_external_dma_prepare_data(host, cmd);
	1634	+ else
	1635	+ sdhci_prepare_data(host, cmd);
	1636	+ }
1262	1637
1263	1638	sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1264	1639
1265	1640	sdhci_set_transfer_mode(host, cmd);
1266	1641
1267	1642	if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1268		- pr_err("%s: Unsupported response type!\n",
1269		- mmc_hostname(host->mmc));
1270		- cmd->error = -EINVAL;
1271		- sdhci_finish_mrq(host, cmd->mrq);
1272		- return;
	1643	+ WARN_ONCE(1, "Unsupported response type!\n");
	1644	+ /*
	1645	+ * This does not happen in practice because 136-bit response
	1646	+ * commands never have busy waiting, so rather than complicate
	1647	+ * the error path, just remove busy waiting and continue.
	1648	+ */
	1649	+ cmd->flags &= ~MMC_RSP_BUSY;
1273	1650	}
1274	1651
1275	1652	if (!(cmd->flags & MMC_RSP_PRESENT))
..	..	@@ -1300,9 +1677,65 @@
1300	1677	timeout += 10 * HZ;
1301	1678	sdhci_mod_timer(host, cmd->mrq, timeout);
1302	1679
	1680	+ if (host->use_external_dma)
	1681	+ sdhci_external_dma_pre_transfer(host, cmd);
	1682	+
1303	1683	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
	1684	+
	1685	+ return true;
1304	1686	}
1305		-EXPORT_SYMBOL_GPL(sdhci_send_command);
	1687	+
	1688	+static bool sdhci_present_error(struct sdhci_host *host,
	1689	+ struct mmc_command *cmd, bool present)
	1690	+{
	1691	+ if (!present \|\| host->flags & SDHCI_DEVICE_DEAD) {
	1692	+ cmd->error = -ENOMEDIUM;
	1693	+ return true;
	1694	+ }
	1695	+
	1696	+ return false;
	1697	+}
	1698	+
	1699	+static bool sdhci_send_command_retry(struct sdhci_host *host,
	1700	+ struct mmc_command *cmd,
	1701	+ unsigned long flags)
	1702	+ __releases(host->lock)
	1703	+ __acquires(host->lock)
	1704	+{
	1705	+ struct mmc_command *deferred_cmd = host->deferred_cmd;
	1706	+ int timeout = 10; /* Approx. 10 ms */
	1707	+ bool present;
	1708	+
	1709	+ while (!sdhci_send_command(host, cmd)) {
	1710	+ if (!timeout--) {
	1711	+ pr_err("%s: Controller never released inhibit bit(s).\n",
	1712	+ mmc_hostname(host->mmc));
	1713	+ sdhci_dumpregs(host);
	1714	+ cmd->error = -EIO;
	1715	+ return false;
	1716	+ }
	1717	+
	1718	+ spin_unlock_irqrestore(&host->lock, flags);
	1719	+
	1720	+ usleep_range(1000, 1250);
	1721	+
	1722	+ present = host->mmc->ops->get_cd(host->mmc);
	1723	+
	1724	+ spin_lock_irqsave(&host->lock, flags);
	1725	+
	1726	+ /* A deferred command might disappear, handle that */
	1727	+ if (cmd == deferred_cmd && cmd != host->deferred_cmd)
	1728	+ return true;
	1729	+
	1730	+ if (sdhci_present_error(host, cmd, present))
	1731	+ return false;
	1732	+ }
	1733	+
	1734	+ if (cmd == host->deferred_cmd)
	1735	+ host->deferred_cmd = NULL;
	1736	+
	1737	+ return true;
	1738	+}
1306	1739
1307	1740	static void sdhci_read_rsp_136(struct sdhci_host host, struct mmc_command cmd)
1308	1741	{
..	..	@@ -1363,7 +1796,10 @@
1363	1796
1364	1797	/* Finished CMD23, now send actual command. */
1365	1798	if (cmd == cmd->mrq->sbc) {
1366		- sdhci_send_command(host, cmd->mrq->cmd);
	1799	+ if (!sdhci_send_command(host, cmd->mrq->cmd)) {
	1800	+ WARN_ON(host->deferred_cmd);
	1801	+ host->deferred_cmd = cmd->mrq->cmd;
	1802	+ }
1367	1803	} else {
1368	1804
1369	1805	/* Processed actual command. */
..	..	@@ -1371,7 +1807,7 @@
1371	1807	sdhci_finish_data(host);
1372	1808
1373	1809	if (!cmd->data)
1374		- sdhci_finish_mrq(host, cmd->mrq);
	1810	+ __sdhci_finish_mrq(host, cmd->mrq);
1375	1811	}
1376	1812	}
1377	1813
..	..	@@ -1427,10 +1863,9 @@
1427	1863
1428	1864	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1429	1865	pre_val = sdhci_get_preset_value(host);
1430		- div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1431		- >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
	1866	+ div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
1432	1867	if (host->clk_mul &&
1433		- (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
	1868	+ (pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
1434	1869	clk = SDHCI_PROG_CLOCK_MODE;
1435	1870	real_div = div + 1;
1436	1871	clk_mul = host->clk_mul;
..	..	@@ -1513,8 +1948,8 @@
1513	1948	clk \|= SDHCI_CLOCK_INT_EN;
1514	1949	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1515	1950
1516		- /* Wait max 20 ms */
1517		- timeout = ktime_add_ms(ktime_get(), 20);
	1951	+ /* Wait max 150 ms */
	1952	+ timeout = ktime_add_ms(ktime_get(), 150);
1518	1953	while (1) {
1519	1954	bool timedout = ktime_after(ktime_get(), timeout);
1520	1955
..	..	@@ -1528,6 +1963,29 @@
1528	1963	return;
1529	1964	}
1530	1965	udelay(10);
	1966	+ }
	1967	+
	1968	+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
	1969	+ clk \|= SDHCI_CLOCK_PLL_EN;
	1970	+ clk &= ~SDHCI_CLOCK_INT_STABLE;
	1971	+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
	1972	+
	1973	+ /* Wait max 150 ms */
	1974	+ timeout = ktime_add_ms(ktime_get(), 150);
	1975	+ while (1) {
	1976	+ bool timedout = ktime_after(ktime_get(), timeout);
	1977	+
	1978	+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
	1979	+ if (clk & SDHCI_CLOCK_INT_STABLE)
	1980	+ break;
	1981	+ if (timedout) {
	1982	+ pr_err("%s: PLL clock never stabilised.\n",
	1983	+ mmc_hostname(host->mmc));
	1984	+ sdhci_dumpregs(host);
	1985	+ return;
	1986	+ }
	1987	+ udelay(10);
	1988	+ }
1531	1989	}
1532	1990
1533	1991	clk \|= SDHCI_CLOCK_CARD_EN;
..	..	@@ -1654,6 +2112,25 @@
1654	2112	}
1655	2113	EXPORT_SYMBOL_GPL(sdhci_set_power);
1656	2114
	2115	+/*
	2116	+ * Some controllers need to configure a valid bus voltage on their power
	2117	+ * register regardless of whether an external regulator is taking care of power
	2118	+ * supply. This helper function takes care of it if set as the controller's
	2119	+ * sdhci_ops.set_power callback.
	2120	+ */
	2121	+void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
	2122	+ unsigned char mode,
	2123	+ unsigned short vdd)
	2124	+{
	2125	+ if (!IS_ERR(host->mmc->supply.vmmc)) {
	2126	+ struct mmc_host *mmc = host->mmc;
	2127	+
	2128	+ mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
	2129	+ }
	2130	+ sdhci_set_power_noreg(host, mode, vdd);
	2131	+}
	2132	+EXPORT_SYMBOL_GPL(sdhci_set_power_and_bus_voltage);
	2133	+
1657	2134	/*****************************************************************************\
1658	2135	* *
1659	2136	* MMC callbacks *
..	..	@@ -1662,11 +2139,10 @@
1662	2139
1663	2140	void sdhci_request(struct mmc_host mmc, struct mmc_request mrq)
1664	2141	{
1665		- struct sdhci_host *host;
1666		- int present;
	2142	+ struct sdhci_host *host = mmc_priv(mmc);
	2143	+ struct mmc_command *cmd;
1667	2144	unsigned long flags;
1668		-
1669		- host = mmc_priv(mmc);
	2145	+ bool present;
1670	2146
1671	2147	/* Firstly check card presence */
1672	2148	present = mmc->ops->get_cd(mmc);
..	..	@@ -1675,31 +2151,57 @@
1675	2151
1676	2152	sdhci_led_activate(host);
1677	2153
1678		- /*
1679		- * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1680		- * requests if Auto-CMD12 is enabled.
1681		- */
1682		- if (sdhci_auto_cmd12(host, mrq)) {
1683		- if (mrq->stop) {
1684		- mrq->data->stop = NULL;
1685		- mrq->stop = NULL;
1686		- }
1687		- }
	2154	+ if (sdhci_present_error(host, mrq->cmd, present))
	2155	+ goto out_finish;
1688	2156
1689		- if (!present \|\| host->flags & SDHCI_DEVICE_DEAD) {
1690		- mrq->cmd->error = -ENOMEDIUM;
1691		- sdhci_finish_mrq(host, mrq);
1692		- } else {
1693		- if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1694		- sdhci_send_command(host, mrq->sbc);
1695		- else
1696		- sdhci_send_command(host, mrq->cmd);
1697		- }
	2157	+ cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
1698	2158
1699		- mmiowb();
	2159	+ if (!sdhci_send_command_retry(host, cmd, flags))
	2160	+ goto out_finish;
	2161	+
	2162	+ spin_unlock_irqrestore(&host->lock, flags);
	2163	+
	2164	+ return;
	2165	+
	2166	+out_finish:
	2167	+ sdhci_finish_mrq(host, mrq);
1700	2168	spin_unlock_irqrestore(&host->lock, flags);
1701	2169	}
1702	2170	EXPORT_SYMBOL_GPL(sdhci_request);
	2171	+
	2172	+int sdhci_request_atomic(struct mmc_host mmc, struct mmc_request mrq)
	2173	+{
	2174	+ struct sdhci_host *host = mmc_priv(mmc);
	2175	+ struct mmc_command *cmd;
	2176	+ unsigned long flags;
	2177	+ int ret = 0;
	2178	+
	2179	+ spin_lock_irqsave(&host->lock, flags);
	2180	+
	2181	+ if (sdhci_present_error(host, mrq->cmd, true)) {
	2182	+ sdhci_finish_mrq(host, mrq);
	2183	+ goto out_finish;
	2184	+ }
	2185	+
	2186	+ cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
	2187	+
	2188	+ /*
	2189	+ * The HSQ may send a command in interrupt context without polling
	2190	+ * the busy signaling, which means we should return BUSY if controller
	2191	+ * has not released inhibit bits to allow HSQ trying to send request
	2192	+ * again in non-atomic context. So we should not finish this request
	2193	+ * here.
	2194	+ */
	2195	+ if (!sdhci_send_command(host, cmd))
	2196	+ ret = -EBUSY;
	2197	+ else
	2198	+ sdhci_led_activate(host);
	2199	+
	2200	+out_finish:
	2201	+ spin_unlock_irqrestore(&host->lock, flags);
	2202	+ return ret;
	2203	+}
	2204	+EXPORT_SYMBOL_GPL(sdhci_request_atomic);
1703	2205
1704	2206	void sdhci_set_bus_width(struct sdhci_host *host, int width)
1705	2207	{
..	..	@@ -1883,8 +2385,8 @@
1883	2385
1884	2386	sdhci_enable_preset_value(host, true);
1885	2387	preset = sdhci_get_preset_value(host);
1886		- ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1887		- >> SDHCI_PRESET_DRV_SHIFT;
	2388	+ ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
	2389	+ preset);
1888	2390	}
1889	2391
1890	2392	/* Re-enable SD Clock */
..	..	@@ -1899,8 +2401,6 @@
1899	2401	*/
1900	2402	if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1901	2403	sdhci_do_reset(host, SDHCI_RESET_CMD \| SDHCI_RESET_DATA);
1902		-
1903		- mmiowb();
1904	2404	}
1905	2405	EXPORT_SYMBOL_GPL(sdhci_set_ios);
1906	2406
..	..	@@ -1908,6 +2408,7 @@
1908	2408	{
1909	2409	struct sdhci_host *host = mmc_priv(mmc);
1910	2410	int gpio_cd = mmc_gpio_get_cd(mmc);
	2411	+ bool allow = true;
1911	2412
1912	2413	if (host->flags & SDHCI_DEVICE_DEAD)
1913	2414	return 0;
..	..	@@ -1915,6 +2416,10 @@
1915	2416	/* If nonremovable, assume that the card is always present. */
1916	2417	if (!mmc_card_is_removable(host->mmc))
1917	2418	return 1;
	2419	+
	2420	+ trace_android_vh_sdhci_get_cd(host, &allow);
	2421	+ if (!allow)
	2422	+ return 0;
1918	2423
1919	2424	/*
1920	2425	* Try slot gpio detect, if defined it take precedence
..	..	@@ -1942,6 +2447,8 @@
1942	2447	is_readonly = 0;
1943	2448	else if (host->ops->get_ro)
1944	2449	is_readonly = host->ops->get_ro(host);
	2450	+ else if (mmc_can_gpio_ro(host->mmc))
	2451	+ is_readonly = mmc_gpio_get_ro(host->mmc);
1945	2452	else
1946	2453	is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1947	2454	& SDHCI_WRITE_PROTECT);
..	..	@@ -1992,7 +2499,6 @@
1992	2499
1993	2500	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1994	2501	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1995		- mmiowb();
1996	2502	}
1997	2503	}
1998	2504
..	..	@@ -2005,11 +2511,6 @@
2005	2511	pm_runtime_get_noresume(host->mmc->parent);
2006	2512
2007	2513	spin_lock_irqsave(&host->lock, flags);
2008		- if (enable)
2009		- host->flags \|= SDHCI_SDIO_IRQ_ENABLED;
2010		- else
2011		- host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
2012		-
2013	2514	sdhci_enable_sdio_irq_nolock(host, enable);
2014	2515	spin_unlock_irqrestore(&host->lock, flags);
2015	2516
..	..	@@ -2017,6 +2518,16 @@
2017	2518	pm_runtime_put_noidle(host->mmc->parent);
2018	2519	}
2019	2520	EXPORT_SYMBOL_GPL(sdhci_enable_sdio_irq);
	2521	+
	2522	+static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
	2523	+{
	2524	+ struct sdhci_host *host = mmc_priv(mmc);
	2525	+ unsigned long flags;
	2526	+
	2527	+ spin_lock_irqsave(&host->lock, flags);
	2528	+ sdhci_enable_sdio_irq_nolock(host, true);
	2529	+ spin_unlock_irqrestore(&host->lock, flags);
	2530	+}
2020	2531
2021	2532	int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
2022	2533	struct mmc_ios *ios)
..	..	@@ -2044,7 +2555,7 @@
2044	2555
2045	2556	if (!IS_ERR(mmc->supply.vqmmc)) {
2046	2557	ret = mmc_regulator_set_vqmmc(mmc, ios);
2047		- if (ret) {
	2558	+ if (ret < 0) {
2048	2559	pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
2049	2560	mmc_hostname(mmc));
2050	2561	return -EIO;
..	..	@@ -2058,7 +2569,7 @@
2058	2569	if (!(ctrl & SDHCI_CTRL_VDD_180))
2059	2570	return 0;
2060	2571
2061		- pr_warn("%s: 3.3V regulator output did not became stable\n",
	2572	+ pr_warn("%s: 3.3V regulator output did not become stable\n",
2062	2573	mmc_hostname(mmc));
2063	2574
2064	2575	return -EAGAIN;
..	..	@@ -2067,7 +2578,7 @@
2067	2578	return -EINVAL;
2068	2579	if (!IS_ERR(mmc->supply.vqmmc)) {
2069	2580	ret = mmc_regulator_set_vqmmc(mmc, ios);
2070		- if (ret) {
	2581	+ if (ret < 0) {
2071	2582	pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
2072	2583	mmc_hostname(mmc));
2073	2584	return -EIO;
..	..	@@ -2090,7 +2601,7 @@
2090	2601	if (ctrl & SDHCI_CTRL_VDD_180)
2091	2602	return 0;
2092	2603
2093		- pr_warn("%s: 1.8V regulator output did not became stable\n",
	2604	+ pr_warn("%s: 1.8V regulator output did not become stable\n",
2094	2605	mmc_hostname(mmc));
2095	2606
2096	2607	return -EAGAIN;
..	..	@@ -2099,7 +2610,7 @@
2099	2610	return -EINVAL;
2100	2611	if (!IS_ERR(mmc->supply.vqmmc)) {
2101	2612	ret = mmc_regulator_set_vqmmc(mmc, ios);
2102		- if (ret) {
	2613	+ if (ret < 0) {
2103	2614	pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
2104	2615	mmc_hostname(mmc));
2105	2616	return -EIO;
..	..	@@ -2179,7 +2690,7 @@
2179	2690	}
2180	2691	EXPORT_SYMBOL_GPL(sdhci_reset_tuning);
2181	2692
2182		-static void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
	2693	+void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2183	2694	{
2184	2695	sdhci_reset_tuning(host);
2185	2696
..	..	@@ -2190,6 +2701,7 @@
2190	2701
2191	2702	mmc_abort_tuning(host->mmc, opcode);
2192	2703	}
	2704	+EXPORT_SYMBOL_GPL(sdhci_abort_tuning);
2193	2705
2194	2706	/*
2195	2707	* We use sdhci_send_tuning() because mmc_send_tuning() is not a good fit. SDHCI
..	..	@@ -2232,7 +2744,11 @@
2232	2744	*/
2233	2745	sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2234	2746
2235		- sdhci_send_command(host, &cmd);
	2747	+ if (!sdhci_send_command_retry(host, &cmd, flags)) {
	2748	+ spin_unlock_irqrestore(&host->lock, flags);
	2749	+ host->tuning_done = 0;
	2750	+ return;
	2751	+ }
2236	2752
2237	2753	host->cmd = NULL;
2238	2754
..	..	@@ -2240,7 +2756,6 @@
2240	2756
2241	2757	host->tuning_done = 0;
2242	2758
2243		- mmiowb();
2244	2759	spin_unlock_irqrestore(&host->lock, flags);
2245	2760
2246	2761	/* Wait for Buffer Read Ready interrupt */
..	..	@@ -2250,15 +2765,15 @@
2250	2765	}
2251	2766	EXPORT_SYMBOL_GPL(sdhci_send_tuning);
2252	2767
2253		-static void __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
	2768	+static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2254	2769	{
2255	2770	int i;
2256	2771
2257	2772	/*
2258	2773	* Issue opcode repeatedly till Execute Tuning is set to 0 or the number
2259		- * of loops reaches 40 times.
	2774	+ * of loops reaches tuning loop count.
2260	2775	*/
2261		- for (i = 0; i < MAX_TUNING_LOOP; i++) {
	2776	+ for (i = 0; i < host->tuning_loop_count; i++) {
2262	2777	u16 ctrl;
2263	2778
2264	2779	sdhci_send_tuning(host, opcode);
..	..	@@ -2267,24 +2782,26 @@
2267	2782	pr_debug("%s: Tuning timeout, falling back to fixed sampling clock\n",
2268	2783	mmc_hostname(host->mmc));
2269	2784	sdhci_abort_tuning(host, opcode);
2270		- return;
2271		- }
2272		-
2273		- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2274		- if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
2275		- if (ctrl & SDHCI_CTRL_TUNED_CLK)
2276		- return; /* Success! */
2277		- break;
	2785	+ return -ETIMEDOUT;
2278	2786	}
2279	2787
2280	2788	/* Spec does not require a delay between tuning cycles */
2281	2789	if (host->tuning_delay > 0)
2282	2790	mdelay(host->tuning_delay);
	2791	+
	2792	+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
	2793	+ if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
	2794	+ if (ctrl & SDHCI_CTRL_TUNED_CLK)
	2795	+ return 0; /* Success! */
	2796	+ break;
	2797	+ }
	2798	+
2283	2799	}
2284	2800
2285	2801	pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
2286	2802	mmc_hostname(host->mmc));
2287	2803	sdhci_reset_tuning(host);
	2804	+ return -EAGAIN;
2288	2805	}
2289	2806
2290	2807	int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
..	..	@@ -2328,7 +2845,7 @@
2328	2845	case MMC_TIMING_UHS_SDR50:
2329	2846	if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2330	2847	break;
2331		- /* FALLTHROUGH */
	2848	+ fallthrough;
2332	2849
2333	2850	default:
2334	2851	goto out;
..	..	@@ -2346,7 +2863,7 @@
2346	2863
2347	2864	sdhci_start_tuning(host);
2348	2865
2349		- __sdhci_execute_tuning(host, opcode);
	2866	+ host->tuning_err = __sdhci_execute_tuning(host, opcode);
2350	2867
2351	2868	sdhci_end_tuning(host);
2352	2869	out:
..	..	@@ -2413,11 +2930,6 @@
2413	2930	sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2414	2931	}
2415	2932
2416		-static inline bool sdhci_has_requests(struct sdhci_host *host)
2417		-{
2418		- return host->cmd \|\| host->data_cmd;
2419		-}
2420		-
2421	2933	static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
2422	2934	{
2423	2935	if (host->data_cmd) {
..	..	@@ -2470,6 +2982,7 @@
2470	2982	.get_ro = sdhci_get_ro,
2471	2983	.hw_reset = sdhci_hw_reset,
2472	2984	.enable_sdio_irq = sdhci_enable_sdio_irq,
	2985	+ .ack_sdio_irq = sdhci_ack_sdio_irq,
2473	2986	.start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2474	2987	.prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2475	2988	.execute_tuning = sdhci_execute_tuning,
..	..	@@ -2479,7 +2992,7 @@
2479	2992
2480	2993	/*****************************************************************************\
2481	2994	* *
2482		- * Tasklets *
	2995	+ * Request done *
2483	2996	* *
2484	2997	\*****************************************************************************/
2485	2998
..	..	@@ -2502,7 +3015,36 @@
2502	3015	return true;
2503	3016	}
2504	3017
2505		- sdhci_del_timer(host, mrq);
	3018	+ /*
	3019	+ * The controller needs a reset of internal state machines
	3020	+ * upon error conditions.
	3021	+ */
	3022	+ if (sdhci_needs_reset(host, mrq)) {
	3023	+ /*
	3024	+ * Do not finish until command and data lines are available for
	3025	+ * reset. Note there can only be one other mrq, so it cannot
	3026	+ * also be in mrqs_done, otherwise host->cmd and host->data_cmd
	3027	+ * would both be null.
	3028	+ */
	3029	+ if (host->cmd \|\| host->data_cmd) {
	3030	+ spin_unlock_irqrestore(&host->lock, flags);
	3031	+ return true;
	3032	+ }
	3033	+
	3034	+ /* Some controllers need this kick or reset won't work here */
	3035	+ if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
	3036	+ /* This is to force an update */
	3037	+ host->ops->set_clock(host, host->clock);
	3038	+
	3039	+ /*
	3040	+ * Spec says we should do both at the same time, but Ricoh
	3041	+ * controllers do not like that.
	3042	+ */
	3043	+ sdhci_do_reset(host, SDHCI_RESET_CMD);
	3044	+ sdhci_do_reset(host, SDHCI_RESET_DATA);
	3045	+
	3046	+ host->pending_reset = false;
	3047	+ }
2506	3048
2507	3049	/*
2508	3050	* Always unmap the data buffers if they were mapped by
..	..	@@ -2511,6 +3053,17 @@
2511	3053	*/
2512	3054	if (host->flags & SDHCI_REQ_USE_DMA) {
2513	3055	struct mmc_data *data = mrq->data;
	3056	+
	3057	+ if (host->use_external_dma && data &&
	3058	+ (mrq->cmd->error \|\| data->error)) {
	3059	+ struct dma_chan *chan = sdhci_external_dma_channel(host, data);
	3060	+
	3061	+ host->mrqs_done[i] = NULL;
	3062	+ spin_unlock_irqrestore(&host->lock, flags);
	3063	+ dmaengine_terminate_sync(chan);
	3064	+ spin_lock_irqsave(&host->lock, flags);
	3065	+ sdhci_set_mrq_done(host, mrq);
	3066	+ }
2514	3067
2515	3068	if (data && data->host_cookie == COOKIE_MAPPED) {
2516	3069	if (host->bounce_buffer) {
..	..	@@ -2556,41 +3109,8 @@
2556	3109	}
2557	3110	}
2558	3111
2559		- /*
2560		- * The controller needs a reset of internal state machines
2561		- * upon error conditions.
2562		- */
2563		- if (sdhci_needs_reset(host, mrq)) {
2564		- /*
2565		- * Do not finish until command and data lines are available for
2566		- * reset. Note there can only be one other mrq, so it cannot
2567		- * also be in mrqs_done, otherwise host->cmd and host->data_cmd
2568		- * would both be null.
2569		- */
2570		- if (host->cmd \|\| host->data_cmd) {
2571		- spin_unlock_irqrestore(&host->lock, flags);
2572		- return true;
2573		- }
2574		-
2575		- /* Some controllers need this kick or reset won't work here */
2576		- if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2577		- /* This is to force an update */
2578		- host->ops->set_clock(host, host->clock);
2579		-
2580		- /* Spec says we should do both at the same time, but Ricoh
2581		- controllers do not like that. */
2582		- sdhci_do_reset(host, SDHCI_RESET_CMD);
2583		- sdhci_do_reset(host, SDHCI_RESET_DATA);
2584		-
2585		- host->pending_reset = false;
2586		- }
2587		-
2588		- if (!sdhci_has_requests(host))
2589		- sdhci_led_deactivate(host);
2590		-
2591	3112	host->mrqs_done[i] = NULL;
2592	3113
2593		- mmiowb();
2594	3114	spin_unlock_irqrestore(&host->lock, flags);
2595	3115
2596	3116	if (host->ops->request_done)
..	..	@@ -2601,9 +3121,10 @@
2601	3121	return false;
2602	3122	}
2603	3123
2604		-static void sdhci_tasklet_finish(unsigned long param)
	3124	+static void sdhci_complete_work(struct work_struct *work)
2605	3125	{
2606		- struct sdhci_host host = (struct sdhci_host )param;
	3126	+ struct sdhci_host *host = container_of(work, struct sdhci_host,
	3127	+ complete_work);
2607	3128
2608	3129	while (!sdhci_request_done(host))
2609	3130	;
..	..	@@ -2627,7 +3148,6 @@
2627	3148	sdhci_finish_mrq(host, host->cmd->mrq);
2628	3149	}
2629	3150
2630		- mmiowb();
2631	3151	spin_unlock_irqrestore(&host->lock, flags);
2632	3152	}
2633	3153
..	..	@@ -2648,7 +3168,8 @@
2648	3168
2649	3169	if (host->data) {
2650	3170	host->data->error = -ETIMEDOUT;
2651		- sdhci_finish_data(host);
	3171	+ __sdhci_finish_data(host, true);
	3172	+ queue_work(host->complete_wq, &host->complete_work);
2652	3173	} else if (host->data_cmd) {
2653	3174	host->data_cmd->error = -ETIMEDOUT;
2654	3175	sdhci_finish_mrq(host, host->data_cmd->mrq);
..	..	@@ -2658,7 +3179,6 @@
2658	3179	}
2659	3180	}
2660	3181
2661		- mmiowb();
2662	3182	spin_unlock_irqrestore(&host->lock, flags);
2663	3183	}
2664	3184
..	..	@@ -2715,7 +3235,7 @@
2715	3235	return;
2716	3236	}
2717	3237
2718		- sdhci_finish_mrq(host, host->cmd->mrq);
	3238	+ __sdhci_finish_mrq(host, host->cmd->mrq);
2719	3239	return;
2720	3240	}
2721	3241
..	..	@@ -2729,7 +3249,7 @@
2729	3249
2730	3250	if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
2731	3251	mrq->sbc->error = err;
2732		- sdhci_finish_mrq(host, mrq);
	3252	+ __sdhci_finish_mrq(host, mrq);
2733	3253	return;
2734	3254	}
2735	3255	}
..	..	@@ -2797,7 +3317,7 @@
2797	3317	if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2798	3318	host->data_cmd = NULL;
2799	3319	data_cmd->error = -ETIMEDOUT;
2800		- sdhci_finish_mrq(host, data_cmd->mrq);
	3320	+ __sdhci_finish_mrq(host, data_cmd->mrq);
2801	3321	return;
2802	3322	}
2803	3323	if (intmask & SDHCI_INT_DATA_END) {
..	..	@@ -2810,7 +3330,7 @@
2810	3330	if (host->cmd == data_cmd)
2811	3331	return;
2812	3332
2813		- sdhci_finish_mrq(host, data_cmd->mrq);
	3333	+ __sdhci_finish_mrq(host, data_cmd->mrq);
2814	3334	return;
2815	3335	}
2816	3336	}
..	..	@@ -2863,7 +3383,7 @@
2863	3383	* some controllers are faulty, don't trust them.
2864	3384	*/
2865	3385	if (intmask & SDHCI_INT_DMA_END) {
2866		- u32 dmastart, dmanow;
	3386	+ dma_addr_t dmastart, dmanow;
2867	3387
2868	3388	dmastart = sdhci_sdma_address(host);
2869	3389	dmanow = dmastart + host->data->bytes_xfered;
..	..	@@ -2871,12 +3391,12 @@
2871	3391	* Force update to the next DMA block boundary.
2872	3392	*/
2873	3393	dmanow = (dmanow &
2874		- ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
	3394	+ ~((dma_addr_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2875	3395	SDHCI_DEFAULT_BOUNDARY_SIZE;
2876	3396	host->data->bytes_xfered = dmanow - dmastart;
2877		- DBG("DMA base 0x%08x, transferred 0x%06x bytes, next 0x%08x\n",
2878		- dmastart, host->data->bytes_xfered, dmanow);
2879		- sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
	3397	+ DBG("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
	3398	+ &dmastart, host->data->bytes_xfered, &dmanow);
	3399	+ sdhci_set_sdma_addr(host, dmanow);
2880	3400	}
2881	3401
2882	3402	if (intmask & SDHCI_INT_DATA_END) {
..	..	@@ -2915,7 +3435,7 @@
2915	3435
2916	3436	spin_lock(&host->lock);
2917	3437
2918		- if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
	3438	+ if (host->runtime_suspended) {
2919	3439	spin_unlock(&host->lock);
2920	3440	return IRQ_NONE;
2921	3441	}
..	..	@@ -2986,8 +3506,7 @@
2986	3506	if ((intmask & SDHCI_INT_CARD_INT) &&
2987	3507	(host->ier & SDHCI_INT_CARD_INT)) {
2988	3508	sdhci_enable_sdio_irq_nolock(host, false);
2989		- host->thread_isr \|= SDHCI_INT_CARD_INT;
2990		- result = IRQ_WAKE_THREAD;
	3509	+ sdio_signal_irq(host->mmc);
2991	3510	}
2992	3511
2993	3512	intmask &= ~(SDHCI_INT_CARD_INSERT \| SDHCI_INT_CARD_REMOVE \|
..	..	@@ -3021,6 +3540,9 @@
3021	3540	}
3022	3541	}
3023	3542	out:
	3543	+ if (host->deferred_cmd)
	3544	+ result = IRQ_WAKE_THREAD;
	3545	+
3024	3546	spin_unlock(&host->lock);
3025	3547
3026	3548	/* Process mrqs ready for immediate completion */
..	..	@@ -3046,12 +3568,22 @@
3046	3568	static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
3047	3569	{
3048	3570	struct sdhci_host *host = dev_id;
	3571	+ struct mmc_command *cmd;
3049	3572	unsigned long flags;
3050	3573	u32 isr;
3051	3574
	3575	+ while (!sdhci_request_done(host))
	3576	+ ;
	3577	+
3052	3578	spin_lock_irqsave(&host->lock, flags);
	3579	+
3053	3580	isr = host->thread_isr;
3054	3581	host->thread_isr = 0;
	3582	+
	3583	+ cmd = host->deferred_cmd;
	3584	+ if (cmd && !sdhci_send_command_retry(host, cmd, flags))
	3585	+ sdhci_finish_mrq(host, cmd->mrq);
	3586	+
3055	3587	spin_unlock_irqrestore(&host->lock, flags);
3056	3588
3057	3589	if (isr & (SDHCI_INT_CARD_INSERT \| SDHCI_INT_CARD_REMOVE)) {
..	..	@@ -3061,16 +3593,7 @@
3061	3593	mmc_detect_change(mmc, msecs_to_jiffies(200));
3062	3594	}
3063	3595
3064		- if (isr & SDHCI_INT_CARD_INT) {
3065		- sdio_run_irqs(host->mmc);
3066		-
3067		- spin_lock_irqsave(&host->lock, flags);
3068		- if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
3069		- sdhci_enable_sdio_irq_nolock(host, true);
3070		- spin_unlock_irqrestore(&host->lock, flags);
3071		- }
3072		-
3073		- return isr ? IRQ_HANDLED : IRQ_NONE;
	3596	+ return IRQ_HANDLED;
3074	3597	}
3075	3598
3076	3599	/*****************************************************************************\
..	..	@@ -3182,7 +3705,6 @@
3182	3705	mmc->ops->set_ios(mmc, &mmc->ios);
3183	3706	} else {
3184	3707	sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
3185		- mmiowb();
3186	3708	}
3187	3709
3188	3710	if (host->irq_wake_enabled) {
..	..	@@ -3224,7 +3746,7 @@
3224	3746	}
3225	3747	EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
3226	3748
3227		-int sdhci_runtime_resume_host(struct sdhci_host *host)
	3749	+int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3228	3750	{
3229	3751	struct mmc_host *mmc = host->mmc;
3230	3752	unsigned long flags;
..	..	@@ -3235,7 +3757,7 @@
3235	3757	host->ops->enable_dma(host);
3236	3758	}
3237	3759
3238		- sdhci_init(host, 0);
	3760	+ sdhci_init(host, soft_reset);
3239	3761
3240	3762	if (mmc->ios.power_mode != MMC_POWER_UNDEFINED &&
3241	3763	mmc->ios.power_mode != MMC_POWER_OFF) {
..	..	@@ -3262,7 +3784,7 @@
3262	3784	host->runtime_suspended = false;
3263	3785
3264	3786	/* Enable SDIO IRQ */
3265		- if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
	3787	+ if (sdio_irq_claimed(mmc))
3266	3788	sdhci_enable_sdio_irq_nolock(host, true);
3267	3789
3268	3790	/* Enable Card Detection */
..	..	@@ -3292,7 +3814,14 @@
3292	3814
3293	3815	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3294	3816	ctrl &= ~SDHCI_CTRL_DMA_MASK;
3295		- if (host->flags & SDHCI_USE_64_BIT_DMA)
	3817	+ /*
	3818	+ * Host from V4.10 supports ADMA3 DMA type.
	3819	+ * ADMA3 performs integrated descriptor which is more suitable
	3820	+ * for cmd queuing to fetch both command and transfer descriptors.
	3821	+ */
	3822	+ if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
	3823	+ ctrl \|= SDHCI_CTRL_ADMA3;
	3824	+ else if (host->flags & SDHCI_USE_64_BIT_DMA)
3296	3825	ctrl \|= SDHCI_CTRL_ADMA64;
3297	3826	else
3298	3827	ctrl \|= SDHCI_CTRL_ADMA32;
..	..	@@ -3302,7 +3831,7 @@
3302	3831	SDHCI_BLOCK_SIZE);
3303	3832
3304	3833	/* Set maximum timeout */
3305		- sdhci_writeb(host, 0xE, SDHCI_TIMEOUT_CONTROL);
	3834	+ sdhci_set_timeout(host, NULL);
3306	3835
3307	3836	host->ier = host->cqe_ier;
3308	3837
..	..	@@ -3315,7 +3844,6 @@
3315	3844	mmc_hostname(mmc), host->ier,
3316	3845	sdhci_readl(host, SDHCI_INT_STATUS));
3317	3846
3318		- mmiowb();
3319	3847	spin_unlock_irqrestore(&host->lock, flags);
3320	3848	}
3321	3849	EXPORT_SYMBOL_GPL(sdhci_cqe_enable);
..	..	@@ -3340,7 +3868,6 @@
3340	3868	mmc_hostname(mmc), host->ier,
3341	3869	sdhci_readl(host, SDHCI_INT_STATUS));
3342	3870
3343		- mmiowb();
3344	3871	spin_unlock_irqrestore(&host->lock, flags);
3345	3872	}
3346	3873	EXPORT_SYMBOL_GPL(sdhci_cqe_disable);
..	..	@@ -3418,6 +3945,7 @@
3418	3945	host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
3419	3946
3420	3947	host->tuning_delay = -1;
	3948	+ host->tuning_loop_count = MAX_TUNING_LOOP;
3421	3949
3422	3950	host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
3423	3951
..	..	@@ -3463,7 +3991,8 @@
3463	3991	return ret;
3464	3992	}
3465	3993
3466		-void __sdhci_read_caps(struct sdhci_host host, u16 ver, u32 caps, u32 caps1)
	3994	+void __sdhci_read_caps(struct sdhci_host host, const u16 ver,
	3995	+ const u32 caps, const u32 caps1)
3467	3996	{
3468	3997	u16 v;
3469	3998	u64 dt_caps_mask = 0;
..	..	@@ -3482,10 +4011,13 @@
3482	4011
3483	4012	sdhci_do_reset(host, SDHCI_RESET_ALL);
3484	4013
3485		- of_property_read_u64(mmc_dev(host->mmc)->of_node,
3486		- "sdhci-caps-mask", &dt_caps_mask);
3487		- of_property_read_u64(mmc_dev(host->mmc)->of_node,
3488		- "sdhci-caps", &dt_caps);
	4014	+ if (host->v4_mode)
	4015	+ sdhci_do_enable_v4_mode(host);
	4016	+
	4017	+ device_property_read_u64_array(mmc_dev(host->mmc),
	4018	+ "sdhci-caps-mask", &dt_caps_mask, 1);
	4019	+ device_property_read_u64_array(mmc_dev(host->mmc),
	4020	+ "sdhci-caps", &dt_caps, 1);
3489	4021
3490	4022	v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
3491	4023	host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
..	..	@@ -3514,7 +4046,7 @@
3514	4046	}
3515	4047	EXPORT_SYMBOL_GPL(__sdhci_read_caps);
3516	4048
3517		-static int sdhci_allocate_bounce_buffer(struct sdhci_host *host)
	4049	+static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
3518	4050	{
3519	4051	struct mmc_host *mmc = host->mmc;
3520	4052	unsigned int max_blocks;
..	..	@@ -3552,7 +4084,7 @@
3552	4084	* Exiting with zero here makes sure we proceed with
3553	4085	* mmc->max_segs == 1.
3554	4086	*/
3555		- return 0;
	4087	+ return;
3556	4088	}
3557	4089
3558	4090	host->bounce_addr = dma_map_single(mmc->parent,
..	..	@@ -3562,7 +4094,7 @@
3562	4094	ret = dma_mapping_error(mmc->parent, host->bounce_addr);
3563	4095	if (ret)
3564	4096	/* Again fall back to max_segs == 1 */
3565		- return 0;
	4097	+ return;
3566	4098	host->bounce_buffer_size = bounce_size;
3567	4099
3568	4100	/* Lie about this since we're bouncing */
..	..	@@ -3572,8 +4104,19 @@
3572	4104
3573	4105	pr_info("%s bounce up to %u segments into one, max segment size %u bytes\n",
3574	4106	mmc_hostname(mmc), max_blocks, bounce_size);
	4107	+}
3575	4108
3576		- return 0;
	4109	+static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
	4110	+{
	4111	+ /*
	4112	+ * According to SD Host Controller spec v4.10, bit[27] added from
	4113	+ * version 4.10 in Capabilities Register is used as 64-bit System
	4114	+ * Address support for V4 mode.
	4115	+ */
	4116	+ if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
	4117	+ return host->caps & SDHCI_CAN_64BIT_V4;
	4118	+
	4119	+ return host->caps & SDHCI_CAN_64BIT;
3577	4120	}
3578	4121
3579	4122	int sdhci_setup_host(struct sdhci_host *host)
..	..	@@ -3583,7 +4126,8 @@
3583	4126	unsigned int ocr_avail;
3584	4127	unsigned int override_timeout_clk;
3585	4128	u32 max_clk;
3586		- int ret;
	4129	+ int ret = 0;
	4130	+ bool enable_vqmmc = false;
3587	4131
3588	4132	WARN_ON(host == NULL);
3589	4133	if (host == NULL)
..	..	@@ -3597,9 +4141,12 @@
3597	4141	* the host can take the appropriate action if regulators are not
3598	4142	* available.
3599	4143	*/
3600		- ret = mmc_regulator_get_supply(mmc);
3601		- if (ret)
3602		- return ret;
	4144	+ if (!mmc->supply.vqmmc) {
	4145	+ ret = mmc_regulator_get_supply(mmc);
	4146	+ if (ret)
	4147	+ return ret;
	4148	+ enable_vqmmc = true;
	4149	+ }
3603	4150
3604	4151	DBG("Version: 0x%08x \| Present: 0x%08x\n",
3605	4152	sdhci_readw(host, SDHCI_HOST_VERSION),
..	..	@@ -3612,13 +4159,10 @@
3612	4159
3613	4160	override_timeout_clk = host->timeout_clk;
3614	4161
3615		- if (host->version > SDHCI_SPEC_300) {
	4162	+ if (host->version > SDHCI_SPEC_420) {
3616	4163	pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
3617	4164	mmc_hostname(mmc), host->version);
3618	4165	}
3619		-
3620		- if (host->quirks & SDHCI_QUIRK_BROKEN_CQE)
3621		- mmc->caps2 &= ~MMC_CAP2_CQE;
3622	4166
3623	4167	if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
3624	4168	host->flags \|= SDHCI_USE_SDMA;
..	..	@@ -3643,18 +4187,29 @@
3643	4187	host->flags &= ~SDHCI_USE_ADMA;
3644	4188	}
3645	4189
3646		- /*
3647		- * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
3648		- * and must do 64-bit DMA. A driver has the opportunity to change
3649		- * that during the first call to ->enable_dma(). Similarly
3650		- * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
3651		- * implement.
3652		- */
3653		- if (host->caps & SDHCI_CAN_64BIT)
	4190	+ if (sdhci_can_64bit_dma(host))
3654	4191	host->flags \|= SDHCI_USE_64_BIT_DMA;
3655	4192
	4193	+ if (host->use_external_dma) {
	4194	+ ret = sdhci_external_dma_init(host);
	4195	+ if (ret == -EPROBE_DEFER)
	4196	+ goto unreg;
	4197	+ /*
	4198	+ * Fall back to use the DMA/PIO integrated in standard SDHCI
	4199	+ * instead of external DMA devices.
	4200	+ */
	4201	+ else if (ret)
	4202	+ sdhci_switch_external_dma(host, false);
	4203	+ /* Disable internal DMA sources */
	4204	+ else
	4205	+ host->flags &= ~(SDHCI_USE_SDMA \| SDHCI_USE_ADMA);
	4206	+ }
	4207	+
3656	4208	if (host->flags & (SDHCI_USE_SDMA \| SDHCI_USE_ADMA)) {
3657		- ret = sdhci_set_dma_mask(host);
	4209	+ if (host->ops->set_dma_mask)
	4210	+ ret = host->ops->set_dma_mask(host);
	4211	+ else
	4212	+ ret = sdhci_set_dma_mask(host);
3658	4213
3659	4214	if (!ret && host->ops->enable_dma)
3660	4215	ret = host->ops->enable_dma(host);
..	..	@@ -3668,27 +4223,30 @@
3668	4223	}
3669	4224	}
3670	4225
3671		- /* SDMA does not support 64-bit DMA */
3672		- if (host->flags & SDHCI_USE_64_BIT_DMA)
	4226	+ /* SDMA does not support 64-bit DMA if v4 mode not set */
	4227	+ if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
3673	4228	host->flags &= ~SDHCI_USE_SDMA;
3674	4229
3675	4230	if (host->flags & SDHCI_USE_ADMA) {
3676	4231	dma_addr_t dma;
3677	4232	void *buf;
3678	4233
3679		- if (host->flags & SDHCI_USE_64_BIT_DMA) {
3680		- host->adma_table_sz = host->adma_table_cnt *
3681		- SDHCI_ADMA2_64_DESC_SZ;
3682		- host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
3683		- } else {
3684		- host->adma_table_sz = host->adma_table_cnt *
3685		- SDHCI_ADMA2_32_DESC_SZ;
3686		- host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
3687		- }
	4234	+ if (!(host->flags & SDHCI_USE_64_BIT_DMA))
	4235	+ host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
	4236	+ else if (!host->alloc_desc_sz)
	4237	+ host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
	4238	+
	4239	+ host->desc_sz = host->alloc_desc_sz;
	4240	+ host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
3688	4241
3689	4242	host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
3690		- buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
3691		- host->adma_table_sz, &dma, GFP_KERNEL);
	4243	+ /*
	4244	+ * Use zalloc to zero the reserved high 32-bits of 128-bit
	4245	+ * descriptors so that they never need to be written.
	4246	+ */
	4247	+ buf = dma_alloc_coherent(mmc_dev(mmc),
	4248	+ host->align_buffer_sz + host->adma_table_sz,
	4249	+ &dma, GFP_KERNEL);
3692	4250	if (!buf) {
3693	4251	pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
3694	4252	mmc_hostname(mmc));
..	..	@@ -3720,11 +4278,9 @@
3720	4278	}
3721	4279
3722	4280	if (host->version >= SDHCI_SPEC_300)
3723		- host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK)
3724		- >> SDHCI_CLOCK_BASE_SHIFT;
	4281	+ host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
3725	4282	else
3726		- host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK)
3727		- >> SDHCI_CLOCK_BASE_SHIFT;
	4283	+ host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
3728	4284
3729	4285	host->max_clk *= 1000000;
3730	4286	if (host->max_clk == 0 \|\| host->quirks &
..	..	@@ -3742,8 +4298,7 @@
3742	4298	* In case of Host Controller v3.00, find out whether clock
3743	4299	* multiplier is supported.
3744	4300	*/
3745		- host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >>
3746		- SDHCI_CLOCK_MUL_SHIFT;
	4301	+ host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
3747	4302
3748	4303	/*
3749	4304	* In case the value in Clock Multiplier is 0, then programmable
..	..	@@ -3776,8 +4331,7 @@
3776	4331	mmc->f_max = max_clk;
3777	4332
3778	4333	if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3779		- host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >>
3780		- SDHCI_TIMEOUT_CLK_SHIFT;
	4334	+ host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
3781	4335
3782	4336	if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
3783	4337	host->timeout_clk *= 1000;
..	..	@@ -3807,16 +4361,19 @@
3807	4361	!host->ops->get_max_timeout_count)
3808	4362	mmc->max_busy_timeout = 0;
3809	4363
3810		- mmc->caps \|= MMC_CAP_SDIO_IRQ \| MMC_CAP_ERASE \| MMC_CAP_CMD23;
	4364	+ mmc->caps \|= MMC_CAP_SDIO_IRQ \| MMC_CAP_CMD23;
3811	4365	mmc->caps2 \|= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3812	4366
3813	4367	if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3814	4368	host->flags \|= SDHCI_AUTO_CMD12;
3815	4369
3816		- /* Auto-CMD23 stuff only works in ADMA or PIO. */
	4370	+ /*
	4371	+ * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
	4372	+ * For v4 mode, SDMA may use Auto-CMD23 as well.
	4373	+ */
3817	4374	if ((host->version >= SDHCI_SPEC_300) &&
3818	4375	((host->flags & SDHCI_USE_ADMA) \|\|
3819		- !(host->flags & SDHCI_USE_SDMA)) &&
	4376	+ !(host->flags & SDHCI_USE_SDMA) \|\| host->v4_mode) &&
3820	4377	!(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3821	4378	host->flags \|= SDHCI_AUTO_CMD23;
3822	4379	DBG("Auto-CMD23 available\n");
..	..	@@ -3846,7 +4403,10 @@
3846	4403	mmc->caps \|= MMC_CAP_NEEDS_POLL;
3847	4404
3848	4405	if (!IS_ERR(mmc->supply.vqmmc)) {
3849		- ret = regulator_enable(mmc->supply.vqmmc);
	4406	+ if (enable_vqmmc) {
	4407	+ ret = regulator_enable(mmc->supply.vqmmc);
	4408	+ host->sdhci_core_to_disable_vqmmc = !ret;
	4409	+ }
3850	4410
3851	4411	/* If vqmmc provides no 1.8V signalling, then there's no UHS */
3852	4412	if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
..	..	@@ -3865,6 +4425,7 @@
3865	4425	mmc_hostname(mmc), ret);
3866	4426	mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3867	4427	}
	4428	+
3868	4429	}
3869	4430
3870	4431	if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
..	..	@@ -3926,8 +4487,8 @@
3926	4487	mmc->caps \|= MMC_CAP_DRIVER_TYPE_D;
3927	4488
3928	4489	/* Initial value for re-tuning timer count */
3929		- host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3930		- SDHCI_RETUNING_TIMER_COUNT_SHIFT;
	4490	+ host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
	4491	+ host->caps1);
3931	4492
3932	4493	/*
3933	4494	* In case Re-tuning Timer is not disabled, the actual value of
..	..	@@ -3937,8 +4498,7 @@
3937	4498	host->tuning_count = 1 << (host->tuning_count - 1);
3938	4499
3939	4500	/* Re-tuning mode supported by the Host Controller */
3940		- host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >>
3941		- SDHCI_RETUNING_MODE_SHIFT;
	4501	+ host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
3942	4502
3943	4503	ocr_avail = 0;
3944	4504
..	..	@@ -3960,35 +4520,32 @@
3960	4520
3961	4521	curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3962	4522	max_current_caps =
3963		- (curr << SDHCI_MAX_CURRENT_330_SHIFT) \|
3964		- (curr << SDHCI_MAX_CURRENT_300_SHIFT) \|
3965		- (curr << SDHCI_MAX_CURRENT_180_SHIFT);
	4523	+ FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) \|
	4524	+ FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) \|
	4525	+ FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
3966	4526	}
3967	4527	}
3968	4528
3969	4529	if (host->caps & SDHCI_CAN_VDD_330) {
3970	4530	ocr_avail \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
3971	4531
3972		- mmc->max_current_330 = ((max_current_caps &
3973		- SDHCI_MAX_CURRENT_330_MASK) >>
3974		- SDHCI_MAX_CURRENT_330_SHIFT) *
3975		- SDHCI_MAX_CURRENT_MULTIPLIER;
	4532	+ mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
	4533	+ max_current_caps) *
	4534	+ SDHCI_MAX_CURRENT_MULTIPLIER;
3976	4535	}
3977	4536	if (host->caps & SDHCI_CAN_VDD_300) {
3978	4537	ocr_avail \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
3979	4538
3980		- mmc->max_current_300 = ((max_current_caps &
3981		- SDHCI_MAX_CURRENT_300_MASK) >>
3982		- SDHCI_MAX_CURRENT_300_SHIFT) *
3983		- SDHCI_MAX_CURRENT_MULTIPLIER;
	4539	+ mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
	4540	+ max_current_caps) *
	4541	+ SDHCI_MAX_CURRENT_MULTIPLIER;
3984	4542	}
3985	4543	if (host->caps & SDHCI_CAN_VDD_180) {
3986	4544	ocr_avail \|= MMC_VDD_165_195;
3987	4545
3988		- mmc->max_current_180 = ((max_current_caps &
3989		- SDHCI_MAX_CURRENT_180_MASK) >>
3990		- SDHCI_MAX_CURRENT_180_SHIFT) *
3991		- SDHCI_MAX_CURRENT_MULTIPLIER;
	4546	+ mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
	4547	+ max_current_caps) *
	4548	+ SDHCI_MAX_CURRENT_MULTIPLIER;
3992	4549	}
3993	4550
3994	4551	/* If OCR set by host, use it instead. */
..	..	@@ -4092,17 +4649,14 @@
4092	4649	*/
4093	4650	mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4094	4651
4095		- if (mmc->max_segs == 1) {
	4652	+ if (mmc->max_segs == 1)
4096	4653	/* This may alter mmc->_blk_ parameters */
4097		- ret = sdhci_allocate_bounce_buffer(host);
4098		- if (ret)
4099		- return ret;
4100		- }
	4654	+ sdhci_allocate_bounce_buffer(host);
4101	4655
4102	4656	return 0;
4103	4657
4104	4658	unreg:
4105		- if (!IS_ERR(mmc->supply.vqmmc))
	4659	+ if (host->sdhci_core_to_disable_vqmmc)
4106	4660	regulator_disable(mmc->supply.vqmmc);
4107	4661	undma:
4108	4662	if (host->align_buffer)
..	..	@@ -4120,13 +4674,17 @@
4120	4674	{
4121	4675	struct mmc_host *mmc = host->mmc;
4122	4676
4123		- if (!IS_ERR(mmc->supply.vqmmc))
	4677	+ if (host->sdhci_core_to_disable_vqmmc)
4124	4678	regulator_disable(mmc->supply.vqmmc);
4125	4679
4126	4680	if (host->align_buffer)
4127	4681	dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4128	4682	host->adma_table_sz, host->align_buffer,
4129	4683	host->align_addr);
	4684	+
	4685	+ if (host->use_external_dma)
	4686	+ sdhci_external_dma_release(host);
	4687	+
4130	4688	host->adma_table = NULL;
4131	4689	host->align_buffer = NULL;
4132	4690	}
..	..	@@ -4134,14 +4692,21 @@
4134	4692
4135	4693	int __sdhci_add_host(struct sdhci_host *host)
4136	4694	{
	4695	+ unsigned int flags = WQ_UNBOUND \| WQ_MEM_RECLAIM \| WQ_HIGHPRI;
4137	4696	struct mmc_host *mmc = host->mmc;
4138	4697	int ret;
4139	4698
4140		- /*
4141		- * Init tasklets.
4142		- */
4143		- tasklet_init(&host->finish_tasklet,
4144		- sdhci_tasklet_finish, (unsigned long)host);
	4699	+ if ((mmc->caps2 & MMC_CAP2_CQE) &&
	4700	+ (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
	4701	+ mmc->caps2 &= ~MMC_CAP2_CQE;
	4702	+ mmc->cqe_ops = NULL;
	4703	+ }
	4704	+
	4705	+ host->complete_wq = alloc_workqueue("sdhci", flags, 0);
	4706	+ if (!host->complete_wq)
	4707	+ return -ENOMEM;
	4708	+
	4709	+ INIT_WORK(&host->complete_work, sdhci_complete_work);
4145	4710
4146	4711	timer_setup(&host->timer, sdhci_timeout_timer, 0);
4147	4712	timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
..	..	@@ -4155,7 +4720,7 @@
4155	4720	if (ret) {
4156	4721	pr_err("%s: Failed to request IRQ %d: %d\n",
4157	4722	mmc_hostname(mmc), host->irq, ret);
4158		- goto untasklet;
	4723	+ goto unwq;
4159	4724	}
4160	4725
4161	4726	ret = sdhci_led_register(host);
..	..	@@ -4165,14 +4730,13 @@
4165	4730	goto unirq;
4166	4731	}
4167	4732
4168		- mmiowb();
4169		-
4170	4733	ret = mmc_add_host(mmc);
4171	4734	if (ret)
4172	4735	goto unled;
4173	4736
4174	4737	pr_info("%s: SDHCI controller on %s [%s] using %s\n",
4175	4738	mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
	4739	+ host->use_external_dma ? "External DMA" :
4176	4740	(host->flags & SDHCI_USE_ADMA) ?
4177	4741	(host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4178	4742	(host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
..	..	@@ -4188,8 +4752,8 @@
4188	4752	sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4189	4753	sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4190	4754	free_irq(host->irq, host);
4191		-untasklet:
4192		- tasklet_kill(&host->finish_tasklet);
	4755	+unwq:
	4756	+ destroy_workqueue(host->complete_wq);
4193	4757
4194	4758	return ret;
4195	4759	}
..	..	@@ -4251,9 +4815,9 @@
4251	4815	del_timer_sync(&host->timer);
4252	4816	del_timer_sync(&host->data_timer);
4253	4817
4254		- tasklet_kill(&host->finish_tasklet);
	4818	+ destroy_workqueue(host->complete_wq);
4255	4819
4256		- if (!IS_ERR(mmc->supply.vqmmc))
	4820	+ if (host->sdhci_core_to_disable_vqmmc)
4257	4821	regulator_disable(mmc->supply.vqmmc);
4258	4822
4259	4823	if (host->align_buffer)
..	..	@@ -4261,6 +4825,9 @@
4261	4825	host->adma_table_sz, host->align_buffer,
4262	4826	host->align_addr);
4263	4827
	4828	+ if (host->use_external_dma)
	4829	+ sdhci_external_dma_release(host);
	4830	+
4264	4831	host->adma_table = NULL;
4265	4832	host->align_buffer = NULL;
4266	4833	}