forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/mmc/host/sdhci-of-dwcmshc.c
....@@ -7,6 +7,7 @@
77  * Author: Jisheng Zhang <jszhang@kernel.org>
88  */
99 
10
+#include <linux/acpi.h>
1011 #include <linux/clk.h>
1112 #include <linux/dma-mapping.h>
1213 #include <linux/iopoll.h>
....@@ -26,11 +27,15 @@
2627 /* DWCMSHC specific Mode Select value */
2728 #define DWCMSHC_CTRL_HS400		0x7
2829 
29
-#define DWCMSHC_VER_ID			0x500
30
-#define DWCMSHC_VER_TYPE		0x504
31
-#define DWCMSHC_HOST_CTRL3		0x508
32
-#define DWCMSHC_EMMC_CONTROL		0x52c
33
-#define DWCMSHC_EMMC_ATCTRL		0x540
30
+/* DWC IP vendor area 1 pointer */
31
+#define DWCMSHC_P_VENDOR_AREA1		0xe8
32
+#define DWCMSHC_AREA1_MASK		GENMASK(11, 0)
33
+/* Offset inside the  vendor area 1 */
34
+#define DWCMSHC_HOST_CTRL3		0x8
35
+#define DWCMSHC_EMMC_CONTROL		0x2c
36
+#define DWCMSHC_CARD_IS_EMMC		BIT(0)
37
+#define DWCMSHC_ENHANCED_STROBE		BIT(8)
38
+#define DWCMSHC_EMMC_ATCTRL		0x40
3439 
3540 /* Rockchip specific Registers */
3641 #define DWCMSHC_EMMC_DLL_CTRL		0x800
....@@ -40,31 +45,30 @@
4045 #define DECMSHC_EMMC_DLL_CMDOUT		0x810
4146 #define DWCMSHC_EMMC_DLL_STATUS0	0x840
4247 #define DWCMSHC_EMMC_DLL_STATUS1	0x844
43
-
4448 #define DWCMSHC_EMMC_DLL_START		BIT(0)
4549 #define DWCMSHC_EMMC_DLL_LOCKED		BIT(8)
4650 #define DWCMSHC_EMMC_DLL_TIMEOUT	BIT(9)
51
+#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL	29
4752 #define DWCMSHC_EMMC_DLL_START_POINT	16
4853 #define DWCMSHC_EMMC_DLL_INC		8
4954 #define DWCMSHC_EMMC_DLL_BYPASS		BIT(24)
5055 #define DWCMSHC_EMMC_DLL_DLYENA		BIT(27)
51
-
5256 #define DLL_TAP_VALUE_SEL		BIT(25)
5357 #define DLL_TAP_VALUE_OFFSET		8
54
-
58
+#define DLL_TXCLK_TAPNUM_DEFAULT	0x10
59
+#define DLL_TXCLK_TAPNUM_90_DEGREES	0xA
5560 #define DLL_TXCLK_TAPNUM_FROM_SW	BIT(24)
56
-#define DLL_TXCLK_NO_INVERTER		BIT(29)
57
-
61
+#define DLL_STRBIN_TAPNUM_DEFAULT	0x8
5862 #define DLL_STRBIN_TAPNUM_FROM_SW	BIT(24)
5963 #define DLL_STRBIN_DELAY_NUM_SEL	BIT(26)
6064 #define DLL_STRBIN_DELAY_NUM_OFFSET	16
61
-
62
-#define DLL_RXCLK_NO_INVERTER		BIT(29)
65
+#define DLL_STRBIN_DELAY_NUM_DEFAULT	0x16
66
+#define DLL_RXCLK_NO_INVERTER		1
67
+#define DLL_RXCLK_INVERTER		0
68
+#define DLL_CMDOUT_TAPNUM_90_DEGREES	0x8
69
+#define DLL_RXCLK_TAPNUM_FROM_SW	BIT(24)
6370 #define DLL_RXCLK_ORI_GATE		BIT(31)
64
-
65
-#define DWCMSHC_CARD_IS_EMMC		BIT(0)
66
-#define DWCMSHC_ENHANCED_STROBE		BIT(8)
67
-
71
+#define DLL_RXCLK_MAX_TAP		32
6872 #define DLL_CMDOUT_TAPNUM_FROM_SW	BIT(24)
6973 #define DLL_CMDOUT_SRC_CLK_NEG		BIT(28)
7074 #define DLL_CMDOUT_EN_SRC_CLK_NEG	BIT(29)
....@@ -73,10 +77,15 @@
7377 #define DLL_LOCK_WO_TMOUT(x) \
7478 	((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \
7579 	(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
76
-#define ROCKCHIP_MAX_CLKS		3
80
+#define RK35xx_MAX_CLKS 3
7781 
7882 #define BOUNDARY_OK(addr, len) \
7983 	((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
84
+
85
+enum dwcmshc_rk_type {
86
+	DWCMSHC_RK3568,
87
+	DWCMSHC_RK3588,
88
+};
8089 
8190 struct dwcmshc_driver_data {
8291 	const struct sdhci_pltfm_data *pdata;
....@@ -93,15 +102,22 @@
93102 	u8 hs400_strbin_tap;
94103 };
95104 
96
-struct dwcmshc_priv {
97
-	struct clk	*bus_clk;
98
-	u32 cclk_rate;
99
-
105
+struct rk35xx_priv {
100106 	/* Rockchip specified optional clocks */
101
-	struct clk_bulk_data rockchip_clks[ROCKCHIP_MAX_CLKS];
107
+	struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS];
102108 	struct reset_control *reset;
109
+	enum dwcmshc_rk_type devtype;
110
+	u8 txclk_tapnum;
111
+	u32 cclk_rate;
103112 	unsigned int actual_clk;
104113 	const struct dwcmshc_driver_data *drv_data;
114
+	u32 acpi_en;
115
+};
116
+
117
+struct dwcmshc_priv {
118
+	struct clk	*bus_clk;
119
+	int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */
120
+	void *priv; /* pointer to SoC private stuff */
105121 };
106122 
107123 /*
....@@ -125,6 +141,16 @@
125141 	addr += tmplen;
126142 	len -= tmplen;
127143 	sdhci_adma_write_desc(host, desc, addr, len, cmd);
144
+}
145
+
146
+static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host)
147
+{
148
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
149
+
150
+	if (pltfm_host->clk)
151
+		return sdhci_pltfm_clk_get_max_clock(host);
152
+	else
153
+		return pltfm_host->clock;
128154 }
129155 
130156 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
....@@ -153,7 +179,9 @@
153179 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
154180 				      unsigned int timing)
155181 {
156
-	u16 ctrl_2, ctrl;
182
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
183
+	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
184
+	u16 ctrl, ctrl_2;
157185 
158186 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
159187 	/* Select Bus Speed Mode for host */
....@@ -173,9 +201,9 @@
173201 		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
174202 	else if (timing == MMC_TIMING_MMC_HS400) {
175203 		/* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */
176
-		ctrl = sdhci_readw(host, DWCMSHC_EMMC_CONTROL);
204
+		ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
177205 		ctrl |= DWCMSHC_CARD_IS_EMMC;
178
-		sdhci_writew(host, ctrl, DWCMSHC_EMMC_CONTROL);
206
+		sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL);
179207 
180208 		ctrl_2 |= DWCMSHC_CTRL_HS400;
181209 	}
....@@ -188,22 +216,27 @@
188216 {
189217 	u32 vendor;
190218 	struct sdhci_host *host = mmc_priv(mmc);
219
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
220
+	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
221
+	int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL;
191222 
192
-	vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL);
223
+	vendor = sdhci_readl(host, reg);
193224 	if (ios->enhanced_strobe)
194225 		vendor |= DWCMSHC_ENHANCED_STROBE;
195226 	else
196227 		vendor &= ~DWCMSHC_ENHANCED_STROBE;
197228 
198
-	sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL);
229
+	sdhci_writel(host, vendor, reg);
199230 }
200231 
201
-static void dwcmshc_rk_set_clock(struct sdhci_host *host, unsigned int clock)
232
+static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
202233 {
203234 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
204
-	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
235
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
236
+	struct rk35xx_priv *priv = dwc_priv->priv;
205237 	const struct dwcmshc_driver_data *drv_data = priv->drv_data;
206
-	u32 txclk_tapnum, extra, dll_lock_value;
238
+	u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
239
+	u32 extra, reg, dll_lock_value;
207240 	int err;
208241 
209242 	host->mmc->actual_clock = 0;
....@@ -218,16 +251,28 @@
218251 	if (clock <= 400000)
219252 		clock = 375000;
220253 
221
-	err = clk_set_rate(pltfm_host->clk, clock);
222
-	if (err)
223
-		dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
254
+	if (priv->acpi_en) {
255
+		union acpi_object params[1];
256
+		struct acpi_object_list param_objects;
257
+
258
+		params[0].type = ACPI_TYPE_INTEGER;
259
+		params[0].integer.value  = clock;
260
+		param_objects.count = 1;
261
+		param_objects.pointer = params;
262
+		acpi_evaluate_object(ACPI_HANDLE(mmc_dev(host->mmc)), "SCLK", &param_objects, NULL);
263
+	} else {
264
+		err = clk_set_rate(pltfm_host->clk, clock);
265
+		if (err)
266
+			dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock);
267
+	}
224268 
225269 	sdhci_set_clock(host, clock);
226270 
227271 	/* Disable cmd conflict check */
228
-	extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
272
+	reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
273
+	extra = sdhci_readl(host, reg);
229274 	extra &= ~BIT(0);
230
-	sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
275
+	sdhci_writel(host, extra, reg);
231276 
232277 	/* Disable output clock while config DLL */
233278 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
....@@ -262,6 +307,7 @@
262307 
263308 	/* Init DLL settings, clean start bit before resetting */
264309 	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
310
+	/* Init DLL settings */
265311 	extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
266312 		0x2 << DWCMSHC_EMMC_DLL_INC |
267313 		DWCMSHC_EMMC_DLL_START;
....@@ -279,11 +325,11 @@
279325 	extra = 0x1 << 16 | /* tune clock stop en */
280326 		0x3 << 17 | /* pre-change delay */
281327 		0x3 << 19;  /* post-change delay */
282
-	sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL);
328
+	sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
283329 
284330 	extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
285331 	if (drv_data->flags & RK_RXCLK_NO_INVERTER)
286
-		extra |= DLL_RXCLK_NO_INVERTER;
332
+		extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
287333 	if (drv_data->flags & RK_TAP_VALUE_SEL)
288334 		extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET;
289335 	sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
....@@ -305,7 +351,7 @@
305351 	}
306352 	extra = DWCMSHC_EMMC_DLL_DLYENA |
307353 		DLL_TXCLK_TAPNUM_FROM_SW |
308
-		DLL_RXCLK_NO_INVERTER |
354
+		DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL |
309355 		txclk_tapnum;
310356 	if (drv_data->flags & RK_TAP_VALUE_SEL)
311357 		extra |= DLL_TAP_VALUE_SEL | dll_lock_value << DLL_TAP_VALUE_OFFSET;
....@@ -323,19 +369,16 @@
323369 	sdhci_enable_clk(host, 0);
324370 }
325371 
326
-static void rockchip_sdhci_reset(struct sdhci_host *host, u8 mask)
372
+static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask)
327373 {
328
-	struct sdhci_pltfm_host *pltfm_host;
329
-	struct dwcmshc_priv *priv;
374
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
375
+	struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
376
+	struct rk35xx_priv *priv = dwc_priv->priv;
330377 
331
-	if (mask & SDHCI_RESET_ALL) {
332
-		pltfm_host = sdhci_priv(host);
333
-		priv = sdhci_pltfm_priv(pltfm_host);
334
-		if (!IS_ERR_OR_NULL(priv->reset)) {
335
-			reset_control_assert(priv->reset);
336
-			udelay(1);
337
-			reset_control_deassert(priv->reset);
338
-		}
378
+	if (mask & SDHCI_RESET_ALL && priv->reset) {
379
+		reset_control_assert(priv->reset);
380
+		udelay(1);
381
+		reset_control_deassert(priv->reset);
339382 	}
340383 
341384 	sdhci_reset(host, mask);
....@@ -353,17 +396,17 @@
353396 	.set_clock		= sdhci_set_clock,
354397 	.set_bus_width		= sdhci_set_bus_width,
355398 	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,
356
-	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
399
+	.get_max_clock		= dwcmshc_get_max_clock,
357400 	.reset			= sdhci_reset,
358401 	.adma_write_desc	= dwcmshc_adma_write_desc,
359402 };
360403 
361
-static const struct sdhci_ops sdhci_dwcmshc_rk_ops = {
362
-	.set_clock		= dwcmshc_rk_set_clock,
404
+static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = {
405
+	.set_clock		= dwcmshc_rk3568_set_clock,
363406 	.set_bus_width		= sdhci_set_bus_width,
364407 	.set_uhs_signaling	= dwcmshc_set_uhs_signaling,
365408 	.get_max_clock		= sdhci_pltfm_clk_get_max_clock,
366
-	.reset			= rockchip_sdhci_reset,
409
+	.reset			= rk35xx_sdhci_reset,
367410 	.adma_write_desc	= dwcmshc_adma_write_desc,
368411 	.request_done		= sdhci_dwcmshc_request_done,
369412 };
....@@ -374,12 +417,76 @@
374417 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
375418 };
376419 
377
-static const struct sdhci_pltfm_data sdhci_dwcmshc_rk_pdata = {
378
-	.ops = &sdhci_dwcmshc_rk_ops,
420
+#ifdef CONFIG_ACPI
421
+static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = {
422
+	.ops = &sdhci_dwcmshc_ops,
423
+	.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
424
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
425
+		   SDHCI_QUIRK2_ACMD23_BROKEN,
426
+};
427
+#endif
428
+
429
+static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
430
+	.ops = &sdhci_dwcmshc_rk35xx_ops,
379431 	.quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
380432 	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
381433 		   SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
382434 };
435
+
436
+static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
437
+{
438
+	int err;
439
+	struct rk35xx_priv *priv = dwc_priv->priv;
440
+
441
+	priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc));
442
+	if (IS_ERR(priv->reset)) {
443
+		err = PTR_ERR(priv->reset);
444
+		dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err);
445
+		return err;
446
+	}
447
+
448
+	priv->rockchip_clks[0].id = "axi";
449
+	priv->rockchip_clks[1].id = "block";
450
+	priv->rockchip_clks[2].id = "timer";
451
+	err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS,
452
+					 priv->rockchip_clks);
453
+	if (err) {
454
+		dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
455
+		return err;
456
+	}
457
+
458
+	err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks);
459
+	if (err) {
460
+		dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
461
+		return err;
462
+	}
463
+
464
+	if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum",
465
+				&priv->txclk_tapnum))
466
+		priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT;
467
+
468
+	/* Disable cmd conflict check */
469
+	sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3);
470
+	/* Reset previous settings */
471
+	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
472
+	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
473
+
474
+	return 0;
475
+}
476
+
477
+static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
478
+{
479
+	/*
480
+	 * Don't support highspeed bus mode with low clk speed as we
481
+	 * cannot use DLL for this condition.
482
+	 */
483
+	if (host->mmc->f_max <= 52000000) {
484
+		dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n",
485
+			 host->mmc->f_max);
486
+		host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
487
+		host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
488
+	}
489
+}
383490 
384491 static const struct dwcmshc_driver_data dwcmshc_drvdata = {
385492 	.pdata = &sdhci_dwcmshc_pdata,
....@@ -387,7 +494,7 @@
387494 };
388495 
389496 static const struct dwcmshc_driver_data rk3568_drvdata = {
390
-	.pdata = &sdhci_dwcmshc_rk_pdata,
497
+	.pdata = &sdhci_dwcmshc_rk35xx_pdata,
391498 	.flags = RK_PLATFROM | RK_RXCLK_NO_INVERTER,
392499 	.hs200_tx_tap = 16,
393500 	.hs400_tx_tap = 8,
....@@ -397,7 +504,7 @@
397504 };
398505 
399506 static const struct dwcmshc_driver_data rk3588_drvdata = {
400
-	.pdata = &sdhci_dwcmshc_rk_pdata,
507
+	.pdata = &sdhci_dwcmshc_rk35xx_pdata,
401508 	.flags = RK_PLATFROM | RK_DLL_CMD_OUT,
402509 	.hs200_tx_tap = 16,
403510 	.hs400_tx_tap = 9,
....@@ -407,7 +514,7 @@
407514 };
408515 
409516 static const struct dwcmshc_driver_data rk3528_drvdata = {
410
-	.pdata = &sdhci_dwcmshc_rk_pdata,
517
+	.pdata = &sdhci_dwcmshc_rk35xx_pdata,
411518 	.flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
412519 	.hs200_tx_tap = 12,
413520 	.hs400_tx_tap = 6,
....@@ -416,51 +523,23 @@
416523 	.ddr50_strbin_delay_num = 10,
417524 };
418525 
419
-static int rockchip_pltf_init(struct sdhci_host *host, struct dwcmshc_priv *priv)
420
-{
421
-	int err;
422
-
423
-	priv->rockchip_clks[0].id = "axi";
424
-	priv->rockchip_clks[1].id = "block";
425
-	priv->rockchip_clks[2].id = "timer";
426
-	err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), ROCKCHIP_MAX_CLKS,
427
-					 priv->rockchip_clks);
428
-	if (err) {
429
-		dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err);
430
-		return err;
431
-	}
432
-
433
-	err = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
434
-	if (err) {
435
-		dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err);
436
-		return err;
437
-	}
438
-
439
-	/* Disable cmd conflict check */
440
-	sdhci_writel(host, 0x0, DWCMSHC_HOST_CTRL3);
441
-	/* Reset previous settings */
442
-	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
443
-	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
444
-
445
-	/*
446
-	 * Don't support highspeed bus mode with low clk speed as we
447
-	 * cannot use DLL for this condition.
448
-	 */
449
-	if (host->mmc->f_max <= 52000000) {
450
-		host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400);
451
-		host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR);
452
-	}
453
-
454
-	return 0;
455
-}
526
+static const struct dwcmshc_driver_data rk3562_drvdata = {
527
+	.pdata = &sdhci_dwcmshc_rk35xx_pdata,
528
+	.flags = RK_PLATFROM | RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
529
+	.hs200_tx_tap = 12,
530
+	.hs400_tx_tap = 6,
531
+	.hs400_cmd_tap = 6,
532
+	.hs400_strbin_tap = 3,
533
+	.ddr50_strbin_delay_num = 10,
534
+};
456535 
457536 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
458537 	{
459
-		.compatible = "snps,dwcmshc-sdhci",
460
-		.data = &dwcmshc_drvdata,
538
+		.compatible = "rockchip,rk3588-dwcmshc",
539
+		.data = &rk3588_drvdata,
461540 	},
462541 	{
463
-		.compatible = "rockchip,dwcmshc-sdhci",
542
+		.compatible = "rockchip,rk3568-dwcmshc",
464543 		.data = &rk3568_drvdata,
465544 	},
466545 	{
....@@ -468,17 +547,35 @@
468547 		.data = &rk3528_drvdata,
469548 	},
470549 	{
471
-		.compatible = "rockchip,rk3588-dwcmshc",
472
-		.data = &rk3588_drvdata,
550
+		.compatible = "rockchip,rk3562-dwcmshc",
551
+		.data = &rk3562_drvdata,
552
+	},
553
+	{
554
+		.compatible = "snps,dwcmshc-sdhci",
555
+		.data = &dwcmshc_drvdata,
473556 	},
474557 	{},
475558 };
559
+MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
560
+
561
+#ifdef CONFIG_ACPI
562
+static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = {
563
+	{
564
+		.id = "MLNXBF30",
565
+		.driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata,
566
+	},
567
+	{}
568
+};
569
+#endif
476570 
477571 static int dwcmshc_probe(struct platform_device *pdev)
478572 {
573
+	struct device *dev = &pdev->dev;
479574 	struct sdhci_pltfm_host *pltfm_host;
480575 	struct sdhci_host *host;
481576 	struct dwcmshc_priv *priv;
577
+	struct rk35xx_priv *rk_priv = NULL;
578
+	const struct sdhci_pltfm_data *pltfm_data;
482579 	const struct dwcmshc_driver_data *drv_data;
483580 	struct mmc_hsq *hsq;
484581 	int err;
....@@ -489,8 +586,9 @@
489586 		dev_err(&pdev->dev, "Error: No device match data found\n");
490587 		return -ENODEV;
491588 	}
589
+	pltfm_data = drv_data->pdata;
492590 
493
-	host = sdhci_pltfm_init(pdev, drv_data->pdata,
591
+	host = sdhci_pltfm_init(pdev, pltfm_data,
494592 				sizeof(struct dwcmshc_priv));
495593 	if (IS_ERR(host))
496594 		return PTR_ERR(host);
....@@ -498,34 +596,38 @@
498596 	/*
499597 	 * extra adma table cnt for cross 128M boundary handling.
500598 	 */
501
-	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
599
+	extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M);
502600 	if (extra > SDHCI_MAX_SEGS)
503601 		extra = SDHCI_MAX_SEGS;
504602 	host->adma_table_cnt += extra;
505603 
506604 	pltfm_host = sdhci_priv(host);
507605 	priv = sdhci_pltfm_priv(pltfm_host);
508
-	priv->drv_data = drv_data;
509
-	priv->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
510
-	pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
511
-	if (IS_ERR(pltfm_host->clk)) {
512
-		err = PTR_ERR(pltfm_host->clk);
513
-		dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
514
-		goto free_pltfm;
515
-	}
516
-	err = clk_prepare_enable(pltfm_host->clk);
517
-	if (err)
518
-		goto free_pltfm;
519606 
520
-	priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
521
-	if (!IS_ERR(priv->bus_clk))
522
-		clk_prepare_enable(priv->bus_clk);
607
+	if (dev->of_node) {
608
+		pltfm_host->clk = devm_clk_get(dev, "core");
609
+		if (IS_ERR(pltfm_host->clk)) {
610
+			err = PTR_ERR(pltfm_host->clk);
611
+			dev_err(dev, "failed to get core clk: %d\n", err);
612
+			goto free_pltfm;
613
+		}
614
+		err = clk_prepare_enable(pltfm_host->clk);
615
+		if (err)
616
+			goto free_pltfm;
617
+
618
+		priv->bus_clk = devm_clk_get(dev, "bus");
619
+		if (!IS_ERR(priv->bus_clk))
620
+			clk_prepare_enable(priv->bus_clk);
621
+	}
523622 
524623 	err = mmc_of_parse(host->mmc);
525624 	if (err)
526625 		goto err_clk;
527626 
528627 	sdhci_get_of_property(pdev);
628
+
629
+	priv->vendor_specific_area1 =
630
+		sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK;
529631 
530632 	host->mmc_host_ops.request = dwcmshc_request;
531633 	host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe;
....@@ -540,29 +642,60 @@
540642 	if (err)
541643 		goto err_clk;
542644 
543
-	err = sdhci_add_host(host);
544
-	if (err)
545
-		goto err_clk;
546
-
547645 	if (drv_data->flags & RK_PLATFROM) {
548
-		err = rockchip_pltf_init(host, priv);
646
+		rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL);
647
+		if (!rk_priv) {
648
+			err = -ENOMEM;
649
+			goto err_clk;
650
+		}
651
+
652
+		rk_priv->drv_data = drv_data;
653
+		rk_priv->acpi_en = has_acpi_companion(&pdev->dev);
654
+
655
+		if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc"))
656
+			rk_priv->devtype = DWCMSHC_RK3588;
657
+		else
658
+			rk_priv->devtype = DWCMSHC_RK3568;
659
+
660
+		priv->priv = rk_priv;
661
+
662
+		err = dwcmshc_rk35xx_init(host, priv);
549663 		if (err)
550664 			goto err_clk;
551665 	}
552666 
553
-	pm_runtime_get_noresume(&pdev->dev);
554
-	pm_runtime_set_active(&pdev->dev);
555
-	pm_runtime_enable(&pdev->dev);
556
-	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
557
-	pm_runtime_use_autosuspend(&pdev->dev);
558
-	pm_runtime_put_autosuspend(&pdev->dev);
667
+	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
668
+
669
+	err = sdhci_setup_host(host);
670
+	if (err)
671
+		goto err_clk;
672
+
673
+	if (rk_priv)
674
+		dwcmshc_rk35xx_postinit(host, priv);
675
+
676
+	err = __sdhci_add_host(host);
677
+	if (err)
678
+		goto err_setup_host;
679
+
680
+	if (rk_priv && !rk_priv->acpi_en) {
681
+		pm_runtime_get_noresume(&pdev->dev);
682
+		pm_runtime_set_active(&pdev->dev);
683
+		pm_runtime_enable(&pdev->dev);
684
+		pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
685
+		pm_runtime_use_autosuspend(&pdev->dev);
686
+		pm_runtime_put_autosuspend(&pdev->dev);
687
+	}
559688 
560689 	return 0;
561690 
691
+err_setup_host:
692
+	sdhci_cleanup_host(host);
562693 err_clk:
563694 	clk_disable_unprepare(pltfm_host->clk);
564695 	clk_disable_unprepare(priv->bus_clk);
565
-	clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
696
+	if (rk_priv)
697
+		clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
698
+					   rk_priv->rockchip_clks);
566699 free_pltfm:
567700 	sdhci_pltfm_free(pdev);
568701 	return err;
....@@ -573,13 +706,15 @@
573706 	struct sdhci_host *host = platform_get_drvdata(pdev);
574707 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
575708 	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
709
+	struct rk35xx_priv *rk_priv = priv->priv;
576710 
577711 	sdhci_remove_host(host, 0);
578712 
579713 	clk_disable_unprepare(pltfm_host->clk);
580714 	clk_disable_unprepare(priv->bus_clk);
581
-	clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
582
-
715
+	if (rk_priv)
716
+		clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
717
+					   rk_priv->rockchip_clks);
583718 	sdhci_pltfm_free(pdev);
584719 
585720 	return 0;
....@@ -591,6 +726,7 @@
591726 	struct sdhci_host *host = dev_get_drvdata(dev);
592727 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
593728 	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
729
+	struct rk35xx_priv *rk_priv = priv->priv;
594730 	int ret;
595731 
596732 	mmc_hsq_suspend(host->mmc);
....@@ -603,7 +739,10 @@
603739 	if (!IS_ERR(priv->bus_clk))
604740 		clk_disable_unprepare(priv->bus_clk);
605741 
606
-	clk_bulk_disable_unprepare(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
742
+	if (rk_priv)
743
+		clk_bulk_disable_unprepare(RK35xx_MAX_CLKS,
744
+					   rk_priv->rockchip_clks);
745
+
607746 	return ret;
608747 }
609748 
....@@ -612,6 +751,7 @@
612751 	struct sdhci_host *host = dev_get_drvdata(dev);
613752 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
614753 	struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
754
+	struct rk35xx_priv *rk_priv = priv->priv;
615755 	int ret;
616756 
617757 	ret = clk_prepare_enable(pltfm_host->clk);
....@@ -624,9 +764,12 @@
624764 			return ret;
625765 	}
626766 
627
-	ret = clk_bulk_prepare_enable(ROCKCHIP_MAX_CLKS, priv->rockchip_clks);
628
-	if (ret)
629
-		return ret;
767
+	if (rk_priv) {
768
+		ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS,
769
+					      rk_priv->rockchip_clks);
770
+		if (ret)
771
+			return ret;
772
+	}
630773 
631774 	ret = sdhci_resume_host(host);
632775 	if (ret)
....@@ -664,13 +807,13 @@
664807 	SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume)
665808 	SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, dwcmshc_runtime_resume, NULL)
666809 };
667
-MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
668810 
669811 static struct platform_driver sdhci_dwcmshc_driver = {
670812 	.driver	= {
671813 		.name	= "sdhci-dwcmshc",
672814 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
673815 		.of_match_table = sdhci_dwcmshc_dt_ids,
816
+		.acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids),
674817 		.pm = &dwcmshc_pmops,
675818 	},
676819 	.probe	= dwcmshc_probe,