forked from ~ljy/RK356X_SDK_RELEASE
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2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e 
 kernel/drivers/mmc/host/dw_mmc.c
....@@ -1,14 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Synopsys DesignWare Multimedia Card Interface driver
34  *  (Based on NXP driver for lpc 31xx)
45  *
56  * Copyright (C) 2009 NXP Semiconductors
67  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
128  */
139 
1410 #include <linux/blkdev.h>
....@@ -40,6 +36,7 @@
4036 #include <linux/of.h>
4137 #include <linux/of_gpio.h>
4238 #include <linux/mmc/slot-gpio.h>
39
+#include <linux/soc/rockchip/rk_sdmmc.h>
4340 #include <linux/soc/rockchip/rockchip_decompress.h>
4441 
4542 #include "dw_mmc.h"
....@@ -109,6 +106,26 @@
109106 /* Each descriptor can transfer up to 4KB of data in chained mode */
110107 #define DW_MCI_DESC_DATA_LENGTH	0x1000
111108 
109
+#if IS_ENABLED(CONFIG_CPU_RV1106)
110
+static spinlock_t *g_sdmmc_ispvicap_lock;
111
+
112
+void rv1106_sdmmc_get_lock(void)
113
+{
114
+	if (g_sdmmc_ispvicap_lock)
115
+		spin_lock(g_sdmmc_ispvicap_lock);
116
+}
117
+EXPORT_SYMBOL(rv1106_sdmmc_get_lock);
118
+
119
+void rv1106_sdmmc_put_lock(void)
120
+{
121
+	if (g_sdmmc_ispvicap_lock)
122
+		spin_unlock(g_sdmmc_ispvicap_lock);
123
+}
124
+EXPORT_SYMBOL(rv1106_sdmmc_put_lock);
125
+#endif
126
+
127
+#define RV1106_RAMDON_DATA_SIZE 508
128
+
112129 #if defined(CONFIG_DEBUG_FS)
113130 static int dw_mci_req_show(struct seq_file *s, void *v)
114131 {
....@@ -175,40 +192,18 @@
175192 	struct mmc_host	*mmc = slot->mmc;
176193 	struct dw_mci *host = slot->host;
177194 	struct dentry *root;
178
-	struct dentry *node;
179195 
180196 	root = mmc->debugfs_root;
181197 	if (!root)
182198 		return;
183199 
184
-	node = debugfs_create_file("regs", S_IRUSR, root, host,
185
-				   &dw_mci_regs_fops);
186
-	if (!node)
187
-		goto err;
188
-
189
-	node = debugfs_create_file("req", S_IRUSR, root, slot,
190
-				   &dw_mci_req_fops);
191
-	if (!node)
192
-		goto err;
193
-
194
-	node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
195
-	if (!node)
196
-		goto err;
197
-
198
-	node = debugfs_create_x32("pending_events", S_IRUSR, root,
199
-				  (u32 *)&host->pending_events);
200
-	if (!node)
201
-		goto err;
202
-
203
-	node = debugfs_create_x32("completed_events", S_IRUSR, root,
204
-				  (u32 *)&host->completed_events);
205
-	if (!node)
206
-		goto err;
207
-
208
-	return;
209
-
210
-err:
211
-	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
200
+	debugfs_create_file("regs", S_IRUSR, root, host, &dw_mci_regs_fops);
201
+	debugfs_create_file("req", S_IRUSR, root, slot, &dw_mci_req_fops);
202
+	debugfs_create_u32("state", S_IRUSR, root, &host->state);
203
+	debugfs_create_xul("pending_events", S_IRUSR, root,
204
+			   &host->pending_events);
205
+	debugfs_create_xul("completed_events", S_IRUSR, root,
206
+			   &host->completed_events);
212207 }
213208 #endif /* defined(CONFIG_DEBUG_FS) */
214209 
....@@ -246,8 +241,9 @@
246241 	 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
247242 	 * expected.
248243 	 */
249
-#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
250
-	if (host->slot->mmc->restrict_caps & RESTRICT_CARD_TYPE_EMMC)
244
+#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT_MMC
245
+	if (host->slot->mmc->caps2 & MMC_CAP2_NO_SD &&
246
+	    host->slot->mmc->caps2 & MMC_CAP2_NO_SDIO)
251247 		delay = 0;
252248 #endif
253249 	if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
....@@ -488,14 +484,20 @@
488484 
489485 	/* Disable and reset the IDMAC interface */
490486 	temp = mci_readl(host, CTRL);
491
-	temp &= ~SDMMC_CTRL_USE_IDMAC;
487
+	if (!host->is_rv1106_sd)
488
+		temp &= ~SDMMC_CTRL_USE_IDMAC;
489
+
492490 	temp |= SDMMC_CTRL_DMA_RESET;
493491 	mci_writel(host, CTRL, temp);
494492 
495493 	/* Stop the IDMAC running */
496494 	temp = mci_readl(host, BMOD);
497
-	temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
498
-	temp |= SDMMC_IDMAC_SWRESET;
495
+	if (host->is_rv1106_sd) {
496
+		temp |= SDMMC_IDMAC_SWRESET;
497
+	} else {
498
+		temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
499
+		temp |= SDMMC_IDMAC_SWRESET;
500
+	}
499501 	mci_writel(host, BMOD, temp);
500502 }
501503 
....@@ -525,8 +527,7 @@
525527 		tasklet_schedule(&host->tasklet);
526528 	}
527529 
528
-	if (host->need_xfer_timer &&
529
-	    host->dir_status == DW_MCI_RECV_STATUS)
530
+	if (host->need_xfer_timer)
530531 		del_timer(&host->xfer_timer);
531532 }
532533 
....@@ -736,6 +737,13 @@
736737 		}
737738 	}
738739 
740
+	if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE)) {
741
+		desc->des0 = desc_last->des0;
742
+		desc->des2 = desc_last->des2;
743
+		desc->des1 = RV1106_RAMDON_DATA_SIZE; /* Random dirty data for last one desc */
744
+		desc_last = desc;
745
+	}
746
+
739747 	/* Set first descriptor */
740748 	desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
741749 
....@@ -871,12 +879,14 @@
871879 	if (!host->dms)
872880 		return -ENOMEM;
873881 
874
-	host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
875
-	if (!host->dms->ch) {
882
+	host->dms->ch = dma_request_chan(host->dev, "rx-tx");
883
+	if (IS_ERR(host->dms->ch)) {
884
+		int ret = PTR_ERR(host->dms->ch);
885
+
876886 		dev_err(host->dev, "Failed to get external DMA channel.\n");
877887 		kfree(host->dms);
878888 		host->dms = NULL;
879
-		return -ENXIO;
889
+		return ret;
880890 	}
881891 
882892 	return 0;
....@@ -918,7 +928,7 @@
918928 	 * non-word-aligned buffers or lengths. Also, we don't bother
919929 	 * with all the DMA setup overhead for short transfers.
920930 	 */
921
-	if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
931
+	if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD && !host->is_rv1106_sd)
922932 		return -EINVAL;
923933 
924934 	if (data->blksz & 3)
....@@ -976,39 +986,12 @@
976986 	data->host_cookie = COOKIE_UNMAPPED;
977987 }
978988 
979
-static int dw_mci_set_sdio_status(struct mmc_host *mmc, int val)
980
-{
981
-	struct dw_mci_slot *slot = mmc_priv(mmc);
982
-	struct dw_mci *host = slot->host;
983
-
984
-	if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO))
985
-		return 0;
986
-
987
-	spin_lock_bh(&host->lock);
988
-
989
-	if (val)
990
-		set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
991
-	else
992
-		clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
993
-
994
-	spin_unlock_bh(&host->lock);
995
-
996
-	mmc_detect_change(slot->mmc, 20);
997
-
998
-	return 0;
999
-}
1000
-
1001989 static int dw_mci_get_cd(struct mmc_host *mmc)
1002990 {
1003991 	int present;
1004992 	struct dw_mci_slot *slot = mmc_priv(mmc);
1005993 	struct dw_mci *host = slot->host;
1006994 	int gpio_cd = mmc_gpio_get_cd(mmc);
1007
-
1008
-#ifdef CONFIG_SDIO_KEEPALIVE
1009
-	if (mmc->logic_remove_card)
1010
-		return test_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1011
-#endif
1012995 
1013996 	/* Use platform get_cd function, else try onboard card detect */
1014997 	if (((mmc->caps & MMC_CAP_NEEDS_POLL)
....@@ -1358,10 +1341,16 @@
13581341 	host->data_status = 0;
13591342 	host->dir_status = 0;
13601343 
1344
+	if (host->is_rv1106_sd)
1345
+		mci_writel(host, CTYPE, (slot->ctype << slot->id));
1346
+
13611347 	data = cmd->data;
13621348 	if (data) {
13631349 		mci_writel(host, TMOUT, 0xFFFFFFFF);
1364
-		mci_writel(host, BYTCNT, data->blksz*data->blocks);
1350
+		if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE))
1351
+			mci_writel(host, BYTCNT, 0);
1352
+		else
1353
+			mci_writel(host, BYTCNT, data->blksz*data->blocks);
13651354 		mci_writel(host, BLKSIZ, data->blksz);
13661355 	}
13671356 
....@@ -1439,6 +1428,7 @@
14391428 	}
14401429 }
14411430 
1431
+static bool dw_mci_reset(struct dw_mci *host);
14421432 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
14431433 {
14441434 	struct dw_mci_slot *slot = mmc_priv(mmc);
....@@ -1460,6 +1450,9 @@
14601450 
14611451 	spin_lock_bh(&host->lock);
14621452 
1453
+	if (host->is_rv1106_sd)
1454
+		dw_mci_reset(host);
1455
+
14631456 	dw_mci_queue_request(host, slot, mrq);
14641457 
14651458 	spin_unlock_bh(&host->lock);
....@@ -1469,7 +1462,7 @@
14691462 {
14701463 	struct dw_mci_slot *slot = mmc_priv(mmc);
14711464 	const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1472
-	u32 regs;
1465
+	u32 regs, power_off_delay;
14731466 	int ret;
14741467 
14751468 	switch (ios->bus_width) {
....@@ -1508,6 +1501,15 @@
15081501 
15091502 	switch (ios->power_mode) {
15101503 	case MMC_POWER_UP:
1504
+		if (dw_mci_get_cd(mmc) && !IS_ERR_OR_NULL(slot->host->pinctrl)) {
1505
+			if (!pinctrl_select_state(slot->host->pinctrl, slot->host->idle_state)) {
1506
+				if (device_property_read_u32(slot->host->dev, "power-off-delay-ms",
1507
+				    &power_off_delay))
1508
+					power_off_delay = 200;
1509
+				msleep(power_off_delay);
1510
+			}
1511
+		}
1512
+
15111513 		if (!IS_ERR(mmc->supply.vmmc)) {
15121514 			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
15131515 					ios->vdd);
....@@ -1524,6 +1526,9 @@
15241526 		mci_writel(slot->host, PWREN, regs);
15251527 		break;
15261528 	case MMC_POWER_ON:
1529
+		if (!IS_ERR_OR_NULL(slot->host->pinctrl))
1530
+			pinctrl_select_state(slot->host->pinctrl, slot->host->normal_state);
1531
+
15271532 		if (!slot->host->vqmmc_enabled) {
15281533 			if (!IS_ERR(mmc->supply.vqmmc)) {
15291534 				ret = regulator_enable(mmc->supply.vqmmc);
....@@ -1538,9 +1543,11 @@
15381543 				slot->host->vqmmc_enabled = true;
15391544 			}
15401545 
1546
+#ifndef CONFIG_ROCKCHIP_THUNDER_BOOT_MMC
15411547 			/* Reset our state machine after powering on */
15421548 			dw_mci_ctrl_reset(slot->host,
15431549 					  SDMMC_CTRL_ALL_RESET_FLAGS);
1550
+#endif
15441551 		}
15451552 
15461553 		/* Adjust clock / bus width after power is up */
....@@ -1548,17 +1555,17 @@
15481555 
15491556 		break;
15501557 	case MMC_POWER_OFF:
1558
+		if (!IS_ERR_OR_NULL(slot->host->pinctrl))
1559
+			pinctrl_select_state(slot->host->pinctrl, slot->host->idle_state);
1560
+
15511561 		/* Turn clock off before power goes down */
15521562 		dw_mci_setup_bus(slot, false);
15531563 
15541564 		if (!IS_ERR(mmc->supply.vmmc))
15551565 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
15561566 
1557
-		if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) {
1558
-			ios->signal_voltage = MMC_SIGNAL_VOLTAGE_330;
1559
-			mmc_regulator_set_vqmmc(mmc, ios);
1567
+		if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
15601568 			regulator_disable(mmc->supply.vqmmc);
1561
-		}
15621569 		slot->host->vqmmc_enabled = false;
15631570 
15641571 		regs = mci_readl(slot->host, PWREN);
....@@ -1612,8 +1619,7 @@
16121619 
16131620 	if (!IS_ERR(mmc->supply.vqmmc)) {
16141621 		ret = mmc_regulator_set_vqmmc(mmc, ios);
1615
-
1616
-		if (ret) {
1622
+		if (ret < 0) {
16171623 			dev_dbg(&mmc->class_dev,
16181624 					 "Regulator set error %d - %s V\n",
16191625 					 ret, uhs & v18 ? "1.8" : "3.3");
....@@ -1843,7 +1849,6 @@
18431849 	.pre_req		= dw_mci_pre_req,
18441850 	.post_req		= dw_mci_post_req,
18451851 	.set_ios		= dw_mci_set_ios,
1846
-	.set_sdio_status	= dw_mci_set_sdio_status,
18471852 	.get_ro			= dw_mci_get_ro,
18481853 	.get_cd			= dw_mci_get_cd,
18491854 	.hw_reset               = dw_mci_hw_reset,
....@@ -1865,6 +1870,9 @@
18651870 
18661871 	WARN_ON(host->cmd || host->data);
18671872 
1873
+	if (host->need_xfer_timer)
1874
+		del_timer(&host->xfer_timer);
1875
+
18681876 	host->slot->mrq = NULL;
18691877 	host->mrq = NULL;
18701878 	if (!list_empty(&host->queue)) {
....@@ -1885,6 +1893,7 @@
18851893 	}
18861894 
18871895 	spin_unlock(&host->lock);
1896
+
18881897 	mmc_request_done(prev_mmc, mrq);
18891898 	spin_lock(&host->lock);
18901899 }
....@@ -1926,6 +1935,9 @@
19261935 {
19271936 	u32 status = host->data_status;
19281937 
1938
+	if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE) && (status & SDMMC_INT_DATA_OVER))
1939
+		goto finish;
1940
+
19291941 	if (status & DW_MCI_DATA_ERROR_FLAGS) {
19301942 		if (status & SDMMC_INT_DRTO) {
19311943 			data->error = -ETIMEDOUT;
....@@ -1958,6 +1970,7 @@
19581970 		 */
19591971 		dw_mci_reset(host);
19601972 	} else {
1973
+finish:
19611974 		data->bytes_xfered = data->blocks * data->blksz;
19621975 		data->error = 0;
19631976 	}
....@@ -2005,8 +2018,10 @@
20052018 				   host->bus_hz);
20062019 
20072020 	/* add a bit spare time */
2008
-	xfer_ms += 100;
2009
-
2021
+	if (host->dir_status == DW_MCI_RECV_STATUS)
2022
+		xfer_ms += 100;
2023
+	else
2024
+		xfer_ms += 2500;
20102025 	spin_lock_irqsave(&host->irq_lock, irqflags);
20112026 	if (!test_bit(EVENT_XFER_COMPLETE, &host->pending_events))
20122027 		mod_timer(&host->xfer_timer,
....@@ -2123,7 +2138,7 @@
21232138 			}
21242139 
21252140 			prev_state = state = STATE_SENDING_DATA;
2126
-			/* fall through */
2141
+			fallthrough;
21272142 
21282143 		case STATE_SENDING_DATA:
21292144 			/*
....@@ -2141,6 +2156,13 @@
21412156 					send_stop_abort(host, data);
21422157 				dw_mci_stop_dma(host);
21432158 				state = STATE_DATA_ERROR;
2159
+				if (host->dir_status == DW_MCI_SEND_STATUS) {
2160
+					data->bytes_xfered = 0;
2161
+					data->error = -ETIMEDOUT;
2162
+					host->data = NULL;
2163
+					dw_mci_request_end(host, mrq);
2164
+					goto unlock;
2165
+				}
21442166 				break;
21452167 			}
21462168 
....@@ -2152,8 +2174,7 @@
21522174 				 */
21532175 				if (host->dir_status == DW_MCI_RECV_STATUS)
21542176 					dw_mci_set_drto(host);
2155
-				if (host->need_xfer_timer &&
2156
-				    host->dir_status == DW_MCI_RECV_STATUS)
2177
+				if (host->need_xfer_timer)
21572178 					dw_mci_set_xfer_timeout(host);
21582179 				break;
21592180 			}
....@@ -2184,7 +2205,7 @@
21842205 			}
21852206 			prev_state = state = STATE_DATA_BUSY;
21862207 
2187
-			/* fall through */
2208
+			fallthrough;
21882209 
21892210 		case STATE_DATA_BUSY:
21902211 			if (!dw_mci_clear_pending_data_complete(host)) {
....@@ -2195,6 +2216,8 @@
21952216 				 */
21962217 				if (host->dir_status == DW_MCI_RECV_STATUS)
21972218 					dw_mci_set_drto(host);
2219
+				if (host->need_xfer_timer && host->dir_status == DW_MCI_SEND_STATUS)
2220
+					dw_mci_set_xfer_timeout(host);
21982221 				break;
21992222 			}
22002223 
....@@ -2211,8 +2234,19 @@
22112234 				}
22122235 
22132236 				/* stop command for open-ended transfer*/
2214
-				if (data->stop)
2237
+				if (data->stop) {
2238
+					if (host->is_rv1106_sd && (data->flags & MMC_DATA_WRITE)) {
2239
+						int fifo_count;
2240
+
2241
+						if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, fifo_count,
2242
+								((fifo_count >> 17) & 0x7FF) <= RV1106_RAMDON_DATA_SIZE / 4,
2243
+								0, 5000 * USEC_PER_MSEC))
2244
+							data->error = -ETIMEDOUT;
2245
+						udelay(1);
2246
+						dw_mci_reset(host);
2247
+					}
22152248 					send_stop_abort(host, data);
2249
+				}
22162250 			} else {
22172251 				/*
22182252 				 * If we don't have a command complete now we'll
....@@ -2237,7 +2271,7 @@
22372271 			 */
22382272 			prev_state = state = STATE_SENDING_STOP;
22392273 
2240
-			/* fall through */
2274
+			fallthrough;
22412275 
22422276 		case STATE_SENDING_STOP:
22432277 			if (!dw_mci_clear_pending_cmd_complete(host))
....@@ -2743,8 +2777,7 @@
27432777 			del_timer(&host->cto_timer);
27442778 			mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
27452779 			host->cmd_status = pending;
2746
-			if ((host->need_xfer_timer) &&
2747
-			     host->dir_status == DW_MCI_RECV_STATUS)
2780
+			if (host->need_xfer_timer)
27482781 				del_timer(&host->xfer_timer);
27492782 			smp_wmb(); /* drain writebuffer */
27502783 			set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
....@@ -2762,11 +2795,14 @@
27622795 		}
27632796 
27642797 		if (pending & SDMMC_INT_DATA_OVER) {
2798
+rv1106_sd:
27652799 			spin_lock_irqsave(&host->irq_lock, irqflags);
27662800 
27672801 			del_timer(&host->dto_timer);
27682802 
27692803 			mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2804
+			if (host->is_rv1106_sd)
2805
+				pending |= SDMMC_INT_DATA_OVER;
27702806 			if (!host->data_status)
27712807 				host->data_status = pending;
27722808 			smp_wmb(); /* drain writebuffer */
....@@ -2836,6 +2872,9 @@
28362872 			mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
28372873 			if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
28382874 				host->dma_ops->complete((void *)host);
2875
+
2876
+			if (host->is_rv1106_sd && (pending & SDMMC_IDMAC_INT_TI))
2877
+				goto rv1106_sd;
28392878 		}
28402879 	}
28412880 
....@@ -2851,12 +2890,6 @@
28512890 
28522891 	if (host->pdata->caps)
28532892 		mmc->caps = host->pdata->caps;
2854
-
2855
-	/*
2856
-	 * Support MMC_CAP_ERASE by default.
2857
-	 * It needs to use trim/discard/erase commands.
2858
-	 */
2859
-	mmc->caps |= MMC_CAP_ERASE;
28602893 
28612894 	if (host->pdata->pm_caps)
28622895 		mmc->pm_caps = host->pdata->pm_caps;
....@@ -2875,15 +2908,7 @@
28752908 				ctrl_id);
28762909 			return -EINVAL;
28772910 		}
2878
-		/*
2879
-		 * Some sd cards violate the spec. They claim to support
2880
-		 * CMD23 but actually not. We don't have a good method to
2881
-		 * work around them except for adding MMC_QUIRK_BLK_NO_CMD23
2882
-		 * one by one. But it's not a acceptable way for our custmors.
2883
-		 * So removing CMD23 support for all sd cards to solve it.
2884
-		 */
2885
-		if (!(mmc->restrict_caps & RESTRICT_CARD_TYPE_SD))
2886
-			mmc->caps |= drv_data->caps[ctrl_id];
2911
+		mmc->caps |= drv_data->caps[ctrl_id];
28872912 	}
28882913 
28892914 	if (host->pdata->caps2)
....@@ -2937,6 +2962,10 @@
29372962 
29382963 	/* Useful defaults if platform data is unset. */
29392964 	if (host->use_dma == TRANS_MODE_IDMAC) {
2965
+		/* Reserve last desc for dirty data */
2966
+		if (host->is_rv1106_sd)
2967
+			host->ring_size--;
2968
+
29402969 		mmc->max_segs = host->ring_size;
29412970 		mmc->max_blk_size = 65535;
29422971 		mmc->max_seg_size = 0x1000;
....@@ -2960,11 +2989,6 @@
29602989 	}
29612990 
29622991 	dw_mci_get_cd(mmc);
2963
-
2964
-#ifdef CONFIG_SDIO_KEEPALIVE
2965
-	if (mmc->logic_remove_card)
2966
-		clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2967
-#endif
29682992 
29692993 	ret = mmc_add_host(mmc);
29702994 	if (ret)
....@@ -3272,6 +3296,22 @@
32723296 			return ERR_PTR(ret);
32733297 	}
32743298 
3299
+	host->pinctrl = devm_pinctrl_get(host->dev);
3300
+	if (!IS_ERR(host->pinctrl)) {
3301
+		host->normal_state = pinctrl_lookup_state(host->pinctrl, "normal");
3302
+		if (IS_ERR(host->normal_state))
3303
+			dev_warn(dev, "No normal pinctrl state\n");
3304
+
3305
+		host->idle_state = pinctrl_lookup_state(host->pinctrl, "idle");
3306
+		if (IS_ERR(host->idle_state))
3307
+			dev_warn(dev, "No idle pinctrl state\n");
3308
+
3309
+		if (!IS_ERR(host->normal_state) && !IS_ERR(host->idle_state))
3310
+			pinctrl_select_state(host->pinctrl, host->idle_state);
3311
+		else
3312
+			host->pinctrl = NULL;
3313
+	}
3314
+
32753315 	return pdata;
32763316 }
32773317 
....@@ -3311,12 +3351,9 @@
33113351 
33123352 	if (!host->pdata) {
33133353 		host->pdata = dw_mci_parse_dt(host);
3314
-		if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3315
-			return -EPROBE_DEFER;
3316
-		} else if (IS_ERR(host->pdata)) {
3317
-			dev_err(host->dev, "platform data not available\n");
3318
-			return -EINVAL;
3319
-		}
3354
+		if (IS_ERR(host->pdata))
3355
+			return dev_err_probe(host->dev, PTR_ERR(host->pdata),
3356
+					     "platform data not available\n");
33203357 	}
33213358 
33223359 	host->biu_clk = devm_clk_get(host->dev, "biu");
....@@ -3329,8 +3366,10 @@
33293366 			return ret;
33303367 		}
33313368 	}
3332
-#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
3333
-	if (device_property_read_bool(host->dev, "supports-emmc")) {
3369
+
3370
+#ifdef CONFIG_ROCKCHIP_THUNDER_BOOT_MMC
3371
+	if (device_property_read_bool(host->dev, "no-sd") &&
3372
+	    device_property_read_bool(host->dev, "no-sdio")) {
33343373 		if (readl_poll_timeout(host->regs + SDMMC_STATUS,
33353374 				fifo_size,
33363375 				!(fifo_size & (BIT(10) | GENMASK(7, 4))),
....@@ -3507,6 +3546,24 @@
35073546 		goto err_dmaunmap;
35083547 	}
35093548 
3549
+	if (host->is_rv1106_sd) {
3550
+#if IS_ENABLED(CONFIG_CPU_RV1106)
3551
+		g_sdmmc_ispvicap_lock = &host->lock;
3552
+#endif
3553
+		/* Select IDMAC interface */
3554
+		fifo_size = mci_readl(host, CTRL);
3555
+		fifo_size |= SDMMC_CTRL_USE_IDMAC;
3556
+		mci_writel(host, CTRL, fifo_size);
3557
+
3558
+		fifo_size = mci_readl(host, INTMASK);
3559
+		fifo_size &= ~SDMMC_INT_HTO;
3560
+		mci_writel(host, INTMASK, fifo_size);
3561
+
3562
+		host->slot->mmc->caps &= ~(MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 |
3563
+					   MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25 |
3564
+					   MMC_CAP_UHS_SDR12);
3565
+	}
3566
+
35103567 	/* Now that slots are all setup, we can enable card detect */
35113568 	dw_mci_enable_cd(host);
35123569 
....@@ -3604,20 +3661,28 @@
36043661 	 * Restore the initial value at FIFOTH register
36053662 	 * And Invalidate the prev_blksz with zero
36063663 	 */
3607
-	 mci_writel(host, FIFOTH, host->fifoth_val);
3608
-	 host->prev_blksz = 0;
3664
+	mci_writel(host, FIFOTH, host->fifoth_val);
3665
+	host->prev_blksz = 0;
36093666 
36103667 	/* Put in max timeout */
36113668 	mci_writel(host, TMOUT, 0xFFFFFFFF);
36123669 
36133670 	mci_writel(host, RINTSTS, 0xFFFFFFFF);
3614
-	mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3615
-		   SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3616
-		   DW_MCI_ERROR_FLAGS);
3671
+	mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | DW_MCI_ERROR_FLAGS);
36173672 	mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
36183673 
3674
+	if (host->is_rv1106_sd) {
3675
+		/* Select IDMAC interface */
3676
+		ret = mci_readl(host, CTRL);
3677
+		ret |= SDMMC_CTRL_USE_IDMAC;
3678
+		mci_writel(host, CTRL, ret);
36193679 
3620
-	if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3680
+		ret = mci_readl(host, INTMASK);
3681
+		ret &= ~SDMMC_INT_HTO;
3682
+		mci_writel(host, INTMASK, ret);
3683
+	}
3684
+
3685
+	if (host->slot && host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
36213686 		dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
36223687 
36233688 	/* Force setup bus to guarantee available clock output */