modify sin led gpio

hc

2024-05-13 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e

 kernel/drivers/mfd/rkx110_x120/rkx120_combtxphy.c
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@@ -111,9 +111,10 @@
111
111
 #define GRF_MIPI_STATUS		0x0080
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 #define PHYLOCK			BIT(0)
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113
 
114
-static void rkx120_combtxphy_dsi_timing_init(struct rk_serdes *des, u8 remote_id)
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+static void rkx120_combtxphy_dsi_timing_init(struct rk_serdes *des,
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+					     struct rkx120_combtxphy *combtxphy,
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+					     u8 dev_id)
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 {
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-	struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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 	const struct configure_opts_combphy cfg = combtxphy->mipi_dphy_cfg;
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 	u32 byte_clk = DIV_ROUND_CLOSEST_ULL(combtxphy->rate, 8);
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 	u32 esc_div = DIV_ROUND_UP(byte_clk, 20 * USEC_PER_SEC);
..
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@@ -123,30 +124,30 @@
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 	u32 t_tago, t_tasure, t_taget;
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 	u32 base = RKX120_MIPI_LVDS_TX_PHY0_BASE;
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126
 
126
-	serdes_combphy_write(des, remote_id, base + INTERFACE_PARA,
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+	serdes_combphy_write(des, dev_id, base + INTERFACE_PARA,
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 			     TXREADYESC_VLD(esc_div - 2) |
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 			     RXVALIDESC_VLD(esc_div - 2));
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-	serdes_combphy_write(des, remote_id, base + COMMON_PARA0, esc_div);
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-	serdes_combphy_update_bits(des, remote_id, base + TEST_PARA0, FSET_EN, FSET_EN);
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+	serdes_combphy_write(des, dev_id, base + COMMON_PARA0, esc_div);
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+	serdes_combphy_update_bits(des, dev_id, base + TEST_PARA0, FSET_EN, FSET_EN);
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 	t_init = DIV_ROUND_UP(cfg.init, t_byte_clk) - 1;
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-	serdes_combphy_write(des, remote_id, base + CLANE_PARA1, T_INITTIME_C(t_init));
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-	serdes_combphy_write(des, remote_id, base + DLANE0_PARA1, T_INITTIME_D(t_init));
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-	serdes_combphy_write(des, remote_id, base + DLANE_PARA1(1), T_INITTIME_D(t_init));
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-	serdes_combphy_write(des, remote_id, base + DLANE_PARA1(2), T_INITTIME_D(t_init));
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-	serdes_combphy_write(des, remote_id, base + DLANE_PARA1(3), T_INITTIME_D(t_init));
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+	serdes_combphy_write(des, dev_id, base + CLANE_PARA1, T_INITTIME_C(t_init));
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+	serdes_combphy_write(des, dev_id, base + DLANE0_PARA1, T_INITTIME_D(t_init));
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA1(1), T_INITTIME_D(t_init));
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA1(2), T_INITTIME_D(t_init));
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA1(3), T_INITTIME_D(t_init));
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139
 
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 	t_clkprepare = DIV_ROUND_UP(cfg.clk_prepare, t_byte_clk) - 1;
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 	t_clkzero = DIV_ROUND_UP(cfg.clk_zero, t_byte_clk) - 1;
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 	t_clkpre = DIV_ROUND_UP(cfg.clk_pre, t_byte_clk) - 1;
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-	serdes_combphy_write(des, remote_id, base + CLANE_PARA2,
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+	serdes_combphy_write(des, dev_id, base + CLANE_PARA2,
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 			     T_CLKPREPARE_C(t_clkprepare) |
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 			     T_CLKZERO_C(t_clkzero) | T_CLKPRE_C(t_clkpre));
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 	t_clkpost = DIV_ROUND_UP(cfg.clk_post, t_byte_clk) - 1;
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 	t_clktrail = DIV_ROUND_UP(cfg.clk_trail, t_byte_clk) - 1;
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 	t_hsexit = DIV_ROUND_UP(cfg.hs_exit, t_byte_clk) - 1;
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-	serdes_combphy_write(des, remote_id, base + CLANE_PARA3,
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+	serdes_combphy_write(des, dev_id, base + CLANE_PARA3,
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 			     T_CLKPOST_C(t_clkpost) |
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 			     T_CLKTRAIL_C(t_clktrail) |
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 			     T_HSEXIT_C(t_hsexit));
..
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@@ -154,62 +155,63 @@
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 	t_hsprepare = DIV_ROUND_UP(cfg.hs_prepare, t_byte_clk) - 1;
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 	t_hszero = DIV_ROUND_UP(cfg.hs_zero, t_byte_clk) - 1;
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 	t_hstrail = DIV_ROUND_UP(cfg.hs_trail, t_byte_clk) - 1;
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-	serdes_combphy_write(des, remote_id, base + DLANE0_PARA2,
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+	serdes_combphy_write(des, dev_id, base + DLANE0_PARA2,
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 			     T_HSPREPARE_D(t_hsprepare) |
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 			     T_HSZERO_D(t_hszero) |
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 			     T_HSTRAIL_D(t_hstrail) |
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 			     T_HSEXIT_D(t_hsexit));
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163
 
163
-	serdes_combphy_write(des, remote_id, base + DLANE_PARA2(1),
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA2(1),
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 			     T_HSPREPARE_D(t_hsprepare) |
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 			     T_HSZERO_D(t_hszero) |
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 			     T_HSTRAIL_D(t_hstrail) |
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 			     T_HSEXIT_D(t_hsexit));
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169
 
169
-	serdes_combphy_write(des, remote_id, base + DLANE_PARA2(2),
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA2(2),
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 			     T_HSPREPARE_D(t_hsprepare) |
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 			     T_HSZERO_D(t_hszero) |
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 			     T_HSTRAIL_D(t_hstrail) |
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 			     T_HSEXIT_D(t_hsexit));
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175
 
175
-	serdes_combphy_write(des, remote_id, base + DLANE_PARA2(3),
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA2(3),
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 			     T_HSPREPARE_D(t_hsprepare) |
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 			     T_HSZERO_D(t_hszero) |
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 			     T_HSTRAIL_D(t_hstrail) |
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 			     T_HSEXIT_D(t_hsexit));
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181
 
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 	t_wakeup = DIV_ROUND_UP(cfg.wakeup, t_byte_clk) - 1;
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-	serdes_combphy_write(des, remote_id, base + DLANE0_PARA3, T_WAKEUP_D(t_wakeup));
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-	serdes_combphy_write(des, remote_id, base + DLANE_PARA3(1), T_WAKEUP_D(t_wakeup));
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-	serdes_combphy_write(des, remote_id, base + DLANE_PARA3(2), T_WAKEUP_D(t_wakeup));
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-	serdes_combphy_write(des, remote_id, base + DLANE_PARA3(3), T_WAKEUP_D(t_wakeup));
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-	serdes_combphy_write(des, remote_id, base + CLANE_PARA4, T_WAKEUP_D(t_wakeup));
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+	serdes_combphy_write(des, dev_id, base + DLANE0_PARA3, T_WAKEUP_D(t_wakeup));
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA3(1), T_WAKEUP_D(t_wakeup));
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA3(2), T_WAKEUP_D(t_wakeup));
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+	serdes_combphy_write(des, dev_id, base + DLANE_PARA3(3), T_WAKEUP_D(t_wakeup));
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+	serdes_combphy_write(des, dev_id, base + CLANE_PARA4, T_WAKEUP_D(t_wakeup));
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 	t_tago = DIV_ROUND_UP(cfg.ta_go, t_byte_clk) - 1;
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 	t_tasure = DIV_ROUND_UP(cfg.ta_sure, t_byte_clk) - 1;
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 	t_taget = DIV_ROUND_UP(cfg.ta_get, t_byte_clk) - 1;
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-	serdes_combphy_write(des, remote_id, base + DLANE0_PARA4,
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+	serdes_combphy_write(des, dev_id, base + DLANE0_PARA4,
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 			     T_TAGO_D0(t_tago) |
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 			     T_TASURE_D0(t_tasure) |
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 			     T_TAGET_D0(t_taget));
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 }
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197
-static void rkx120_combtxphy_dsi_pll_set(struct rk_serdes *des, u8 remote_id)
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+static void rkx120_combtxphy_dsi_pll_set(struct rk_serdes *des,
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+					 struct rkx120_combtxphy *combtxphy, u8 dev_id)
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 {
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-	struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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 	u32 base = RKX120_MIPI_LVDS_TX_PHY0_BASE;
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202
 
202
-	serdes_combphy_update_bits(des, remote_id, base + PLL_CTRL_PARA0,
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+	serdes_combphy_update_bits(des, dev_id, base + PLL_CTRL_PARA0,
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 				   RATE_MASK | REFCLK_DIV_MASK | PLL_DIV_MASK,
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 				   RATE(combtxphy->rate_factor) |
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 				   REFCLK_DIV(combtxphy->ref_div - 1) |
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 				   PLL_DIV(combtxphy->fb_div));
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 }
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209
 
209
-static void rkx120_combtxphy_dsi_power_on(struct rk_serdes *des, u8 remote_id)
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+static void rkx120_combtxphy_dsi_power_on(struct rk_serdes *des,
211
+					  struct rkx120_combtxphy *combtxphy,
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+					  u8 dev_id)
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213
 {
211
-	struct rkx120_combtxphy *combtxphy = &des->combtxphy;
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-	struct i2c_client *client = des->chip[remote_id].client;
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+	struct i2c_client *client = des->chip[dev_id].client;
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 	u32 grf_base = RKX120_GRF_MIPI0_BASE;
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 	u32 val;
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 	int ret;
..
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@@ -218,8 +220,8 @@
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 			   PHY_MODE(COMBTX_PHY_MODE_VIDEO_MIPI));
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221
 
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 	serdes_combphy_get_default_config(combtxphy->rate, &combtxphy->mipi_dphy_cfg);
221
-	rkx120_combtxphy_dsi_timing_init(des, remote_id);
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-	rkx120_combtxphy_dsi_pll_set(des, remote_id);
223
+	rkx120_combtxphy_dsi_timing_init(des, combtxphy, dev_id);
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+	rkx120_combtxphy_dsi_pll_set(des, combtxphy, dev_id);
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225
 
224
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 	des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON0, PHYSHUTDWN(1));
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 	des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON1, PWON_PLL(1));
..
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@@ -233,19 +235,20 @@
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 		dev_err(des->dev, "PLL is not locked\n");
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 }
235
237
 
236
-static void rkx120_combtxphy_dsi_power_off(struct rk_serdes *des, u8 remote_id)
238
+static void rkx120_combtxphy_dsi_power_off(struct rk_serdes *des, u8 dev_id)
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 {
238
-	struct i2c_client *client = des->chip[remote_id].client;
240
+	struct i2c_client *client = des->chip[dev_id].client;
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241
 	u32 grf_base = RKX120_GRF_MIPI0_BASE;
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242
 
241
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 	des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON0, PHYSHUTDWN(0));
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 	des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON1, PWON_PLL(0));
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 }
244
246
 
245
-static void rkx120_combtxphy_lvds_power_on(struct rk_serdes *des, u8 remote_id, u8 phy_id)
247
+static void rkx120_combtxphy_lvds_power_on(struct rk_serdes *des,
248
+					   struct rkx120_combtxphy *combtxphy,
249
+					   u8 dev_id, u8 phy_id)
246
250
 {
247
-	struct rkx120_combtxphy *combtxphy = &des->combtxphy;
248
-	struct i2c_client *client = des->chip[remote_id].client;
251
+	struct i2c_client *client = des->chip[dev_id].client;
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252
 	u32 grf_base = (phy_id == 0) ?
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 			RKX120_GRF_MIPI0_BASE : RKX120_GRF_MIPI1_BASE;
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254
 	const struct {
..
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@@ -304,29 +307,27 @@
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 	des->i2c_write_reg(client, grf_base + GRF_MIPITX_CON13, TX_IDLE(0));
305
308
 }
306
309
 
307
-void rkx120_combtxphy_power_on(struct rk_serdes *des, u8 remote_id, u8 phy_id)
310
+void rkx120_combtxphy_power_on(struct rk_serdes *des, struct rkx120_combtxphy *combtxphy,
311
+			       u8 dev_id, u8 phy_id)
308
312
 {
309
-	struct rkx120_combtxphy *combtxphy = &des->combtxphy;
310
-
311
313
 	switch (combtxphy->mode) {
312
314
 	case COMBTX_PHY_MODE_VIDEO_MIPI:
313
-		rkx120_combtxphy_dsi_power_on(des, remote_id);
315
+		rkx120_combtxphy_dsi_power_on(des, combtxphy, dev_id);
314
316
 		break;
315
317
 	case COMBTX_PHY_MODE_VIDEO_LVDS:
316
-		rkx120_combtxphy_lvds_power_on(des, remote_id, phy_id);
318
+		rkx120_combtxphy_lvds_power_on(des, combtxphy, dev_id, phy_id);
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 		break;
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320
 	default:
319
321
 		break;
320
322
 	}
321
323
 }
322
324
 
323
-void rkx120_combtxphy_power_off(struct rk_serdes *des, u8 remote_id)
325
+void rkx120_combtxphy_power_off(struct rk_serdes *des, struct rkx120_combtxphy *combtxphy,
326
+				u8 dev_id, u8 phy_id)
324
327
 {
325
-	struct rkx120_combtxphy *combtxphy = &des->combtxphy;
326
-
327
328
 	switch (combtxphy->mode) {
328
329
 	case COMBTX_PHY_MODE_VIDEO_MIPI:
329
-		rkx120_combtxphy_dsi_power_off(des, remote_id);
330
+		rkx120_combtxphy_dsi_power_off(des, dev_id);
330
331
 		break;
331
332
 	case COMBTX_PHY_MODE_VIDEO_LVDS:
332
333
 		break;
..
..
@@ -385,10 +386,8 @@
385
386
 {
386
387
 }
387
388
 
388
-void rkx120_combtxphy_set_rate(struct rk_serdes *des, u64 rate)
389
+void rkx120_combtxphy_set_rate(struct rkx120_combtxphy *combtxphy, u64 rate)
389
390
 {
390
-	struct rkx120_combtxphy *combtxphy = &des->combtxphy;
391
-
392
391
 	switch (combtxphy->mode) {
393
392
 	case COMBTX_PHY_MODE_VIDEO_MIPI:
394
393
 		rkx120_combtxphy_dsi_pll_calc_rate(combtxphy, rate);
..
..
@@ -403,14 +402,12 @@
403
402
 	combtxphy->rate = rate;
404
403
 }
405
404
 
406
-u64 rkx120_combtxphy_get_rate(struct rk_serdes *des)
405
+u64 rkx120_combtxphy_get_rate(struct rkx120_combtxphy *combtxphy)
407
406
 {
408
-	return des->combtxphy.rate;
407
+	return combtxphy->rate;
409
408
 }
410
409
 
411
-void rkx120_combtxphy_set_mode(struct rk_serdes *des, enum combtx_phy_mode mode)
410
+void rkx120_combtxphy_set_mode(struct rkx120_combtxphy *combtxphy, enum combtx_phy_mode mode)
412
411
 {
413
-	struct rkx120_combtxphy *combtxphy = &des->combtxphy;
414
-
415
412
 	combtxphy->mode = mode;
416
413
 }