~hc/RK356X_SDK_RELEASE.git

..	..	@@ -55,6 +55,7 @@
55	55	#define SER_EN BIT(0)
56	56
57	57	#define RKLINK_TX_VIDEO_CTRL LINK_REG(0x0004)
	58	+#define VIDEO_REPKT_LENGTH_MASK GENMASK(29, 16)
58	59	#define VIDEO_REPKT_LENGTH(x) UPDATE(x, 29, 16)
59	60	#define DUAL_LVDS_CYCLE_DIFF(x) UPDATE(x, 13, 4)
60	61	#define PIXEL_VSYNC_SEL BIT(3)
..	..	@@ -86,11 +87,13 @@
86	87	#define DSI_CHANNEL_SWAP UPDATE(2, 31, 30)
87	88	#define DSI0_SPLIT_MODE UPDATE(0, 31, 30)
88	89	#define DSI1_SPLIT_MODE UPDATE(3, 31, 30)
	90	+#define DSI_DST_VPORCH_MASK GENMASK(29, 0)
89	91	#define DSI_VFP(x) UPDATE(x, 29, 20)
90	92	#define DSI_VBP(x) UPDATE(x, 19, 10)
91	93	#define DSI_VSA(x) UPDATE(x, 9, 0)
92	94
93	95	#define SER_RKLINK_DSI_REC3(x) LINK_REG(0x0014 + 0x10 * x)
	96	+ #define DSI_DELAY_LENGTH_MASK GENMASK(31, 12)
94	97	#define DSI_DELAY_LENGTH(x) UPDATE(x, 31, 12)
95	98	#define DSI_HSA(x) UPDATE(x, 11, 0)
96	99
..	..	@@ -101,7 +104,33 @@
101	104	#define SER_RKLINK_AUDIO_RECOVER LINK_REG(0x0034)
102	105	#define SER_RKLINK_AUDIO_FM_STATUS LINK_REG(0x0038)
103	106	#define SER_RKLINK_FIFO_STATUS LINK_REG(0x003C)
	107	+ #define CH1_CMD_FIFO_UNDERRUN BIT(24)
	108	+ #define CH0_CMD_FIFO_UNDERRUN BIT(23)
	109	+ #define DATA1_FIFO_UNDERRUN BIT(22)
	110	+ #define DATA0_FIFO_UNDERRUN BIT(21)
	111	+ #define AUDIO_FIFO_UNDERRUN BIT(20)
	112	+ #define LVDS1_FIFO_UNDERRUN BIT(19)
	113	+ #define LVDS0_FIFO_UNDERRUN BIT(18)
	114	+ #define DSI_CH1_FIFO_UNDERRUN BIT(17)
	115	+ #define DSI_CH0_FIFO_UNDERRUN BIT(16)
	116	+ #define CH1_CMD_FIFO_OVERFLOW BIT(8)
	117	+ #define CH0_CMD_FIFO_OVERFLOW BIT(7)
	118	+ #define DATA0_FIFO_OVERFLOW BIT(6)
	119	+ #define DATA1_FIFO_OVERFLOW BIT(5)
	120	+ #define AUDIO_FIFO_OVERFLOW BIT(4)
	121	+ #define LVDS1_FIFO_OVERFLOW BIT(3)
	122	+ #define LVDS0_FIFO_OVERFLOW BIT(2)
	123	+ #define DSI_CH1_FIFO_OVERFLOW BIT(1)
	124	+ #define DSI_CH0_FIFO_OVERFLOW BIT(0)
104	125	#define SER_RKLINK_SOURCE_IRQ_EN LINK_REG(0x0040)
	126	+ #define TRAIN_DONE_IRQ_FLAG BIT(19)
	127	+ #define FIFO_UNDERRUN_IRQ_FLAG BIT(18)
	128	+ #define FIFO_OVERFLOW_IRQ_FLAG BIT(17)
	129	+ #define AUDIO_FM_IRQ_OUTPUT_FLAG BIT(16)
	130	+ #define TRAIN_DONE_IRQ_OUTPUT_EN BIT(3)
	131	+ #define FIFO_UNDERRUN_IRQ_OUTPUT_EN BIT(2)
	132	+ #define FIFO_OVERFLOW_IRQ_OUTPUT_EN BIT(1)
	133	+ #define AUDIO_FM_IRQ_OUTPUT_EN BIT(0)
105	134
106	135	#define SER_RKLINK_TRAIN_CTRL LINK_REG(0x0044)
107	136	#define SER_RKLINK_I2C_CFG LINK_REG(0x00C0)
..	..	@@ -144,7 +173,9 @@
144	173	#define PCS_REG24(id) PCS_REG(id, 0x24)
145	174	#define PCS_REG28(id) PCS_REG(id, 0x28)
146	175	#define PCS_REG30(id) PCS_REG(id, 0x30)
	176	+#define PCS_INT_STARTUP(x) HIWORD_UPDATE(x, GENMASK(15, 0), 0)
147	177	#define PCS_REG34(id) PCS_REG(id, 0x34)
	178	+#define PCS_INT_REMOTE_MODE(x) HIWORD_UPDATE(x, GENMASK(15, 0), 0)
148	179	#define PCS_REG40(id) PCS_REG(id, 0x40)
149	180
150	181	#define PMA_REG(id, x) ((x) + RKX110_SER_PMA0_BASE + (id) * RKX110_SER_PMA_OFFSET)
..	..	@@ -194,6 +225,15 @@
194	225	#define SER_PMA_LOAD0A(id) PMA_REG(id, 0x38)
195	226	#define PMA_CLK_8X_DIV_MASK HIWORD_MASK(7, 1)
196	227	#define PMA_CLK_8X_DIV(x) HIWORD_UPDATE(x, GENMASK(7, 1), 1)
	228	+
	229	+#define SER_PMA_IRQ_EN(id) PMA_REG(id, 0xF0)
	230	+ #define FORCE_INITIAL_IRQ_EN HIWORD_UPDATE(1, BIT(3), 3)
	231	+ #define RTERM_ONCE_TIMEOUT_IRQ_EN HIWORD_UPDATE(1, BIT(1), 1)
	232	+ #define PLL_LOCK_TIMEOUT_IRQ_EN HIWORD_UPDATE(1, BIT(0), 0)
	233	+#define SER_PMA_IRQ_STATUS(id) PMA_REG(id, 0xF4)
	234	+ #define FORCE_INITIAL_PULSE_STATUS BIT(3)
	235	+ #define RTERM_ONCE_TIMEOUT_STATUS BIT(1)
	236	+ #define PLL_LOCK_TIMEOUT_STATUS BIT(0)
197	237
198	238	enum {
199	239	SER_LINK_CH_ID0 = 0,
..	..	@@ -422,53 +462,124 @@
422	462	serdes->i2c_write_reg(client, RKLINK_TX_VIDEO_CTRL, val);
423	463	}
424	464
425		-static int rk_serdes_link_tx_ctrl_enable(struct rk_serdes *serdes,
426		- struct rk_serdes_route *route,
427		- u8 remote_id)
	465	+static int rkx110_linktx_ser_enable(struct rk_serdes *serdes, u8 dev_id, bool enable)
428	466	{
429		- struct hwclk *hwclk = serdes->chip[remote_id].hwclk;
430		- struct i2c_client *client;
431		- u32 ctrl_val, val;
432		- u32 rx_src;
433		- u32 stream_type;
	467	+ struct i2c_client *client = serdes->chip[dev_id].client;
434	468
435		- if (route->stream_type == STREAM_DISPLAY) {
436		- client = serdes->chip[DEVICE_LOCAL].client;
437		- stream_type = SER_STREAM_DISPLAY;
438		- } else {
439		- client = serdes->chip[remote_id].client;
440		- stream_type = SER_STREAM_CAMERA;
441		- }
	469	+ serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, SER_EN, enable ? SER_EN : 0);
442	470
443		- serdes->i2c_read_reg(client, RKLINK_TX_SERDES_CTRL, &ctrl_val);
	471	+ return 0;
	472	+}
444	473
445		- ctrl_val &= ~(SER_EN \| SERDES_DUAL_LANE_EN \| SER_CH1_EN \| SERDES_MIRROR_EN \|
446		- CH1_LVDS_SEL_EN);
447		- ctrl_val \|= stream_type;
448		- if (serdes->route_flag & ROUTE_MULTI_LANE)
449		- ctrl_val \|= SERDES_DUAL_LANE_EN;
450		- if (serdes->route_flag & ROUTE_MULTI_CHANNEL)
451		- ctrl_val \|= SER_CH1_EN;
452		- if (serdes->route_flag & ROUTE_MULTI_MIRROR)
453		- ctrl_val \|= SERDES_MIRROR_EN;
454		- if (serdes->route_flag & ROUTE_MULTI_LVDS_INPUT)
455		- ctrl_val \|= CH1_LVDS_SEL_EN;
	474	+static int rk110_linktx_dual_lane_enable(struct rk_serdes *serdes, u8 dev_id, bool enable)
	475	+{
	476	+ struct i2c_client *client = serdes->chip[dev_id].client;
456	477
457		- serdes->i2c_write_reg(client, RKLINK_TX_SERDES_CTRL, ctrl_val);
	478	+ serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, SERDES_DUAL_LANE_EN,
	479	+ enable ? SERDES_DUAL_LANE_EN : 0);
458	480
459		- serdes->i2c_read_reg(client, RKLINK_TX_VIDEO_CTRL, &val);
460		- rx_src = rk_serdes_get_stream_source(serdes, route->local_port0);
461		- val \|= rx_src;
462		- serdes->i2c_write_reg(client, RKLINK_TX_VIDEO_CTRL, val);
	481	+ return 0;
	482	+}
463	483
464		- if (route->local_port0 & RK_SERDES_DUAL_LVDS_RX) {
465		- hwclk_set_rate(hwclk, RKX110_CPS_CLK_2X_LVDS_RKLINK_TX, route->vm.pixelclock);
466		- dev_info(serdes->dev, "RKX110_CPS_CLK_2X_LVDS_RKLINK_TX:%d\n",
467		- hwclk_get_rate(hwclk, RKX110_CPS_CLK_2X_LVDS_RKLINK_TX));
468		- }
	484	+void rkx110_linktx_video_enable(struct rk_serdes *serdes, u8 dev_id, bool enable)
	485	+{
	486	+ struct i2c_client *client = serdes->chip[dev_id].client;
469	487
470		- ctrl_val \|= SER_EN;
471		- serdes->i2c_write_reg(client, RKLINK_TX_SERDES_CTRL, ctrl_val);
	488	+ serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, VIDEO_EN, enable ? VIDEO_EN : 0);
	489	+}
	490	+
	491	+static int rk110_linktx_dual_channel_enable(struct rk_serdes *serdes, u8 dev_id, bool enable)
	492	+{
	493	+ struct i2c_client *client = serdes->chip[dev_id].client;
	494	+
	495	+ serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, SER_CH1_EN,
	496	+ enable ? SER_CH1_EN : 0);
	497	+
	498	+ return 0;
	499	+}
	500	+
	501	+static int rk110_linktx_config_pkg_length(struct rk_serdes *serdes, u8 dev_id, u32 length)
	502	+{
	503	+ struct i2c_client *client = serdes->chip[dev_id].client;
	504	+
	505	+ serdes->i2c_update_bits(client, RKLINK_TX_VIDEO_CTRL, VIDEO_REPKT_LENGTH_MASK,
	506	+ VIDEO_REPKT_LENGTH(length));
	507	+
	508	+ return 0;
	509	+}
	510	+
	511	+static int rk110_linktx_stream_type_cfg(struct rk_serdes *serdes, u8 dev_id)
	512	+{
	513	+ struct i2c_client *client = serdes->chip[dev_id].client;
	514	+
	515	+ if (serdes->stream_type == STREAM_DISPLAY)
	516	+ serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, STREAM_TYPE_MASK,
	517	+ SER_STREAM_DISPLAY);
	518	+ else
	519	+ serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, STREAM_TYPE_MASK,
	520	+ SER_STREAM_CAMERA);
	521	+
	522	+ return 0;
	523	+}
	524	+
	525	+static int rk110_linktx_replicate_enable(struct rk_serdes *serdes, u8 dev_id, bool enable)
	526	+{
	527	+ struct i2c_client *client = serdes->chip[dev_id].client;
	528	+
	529	+ serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, SERDES_MIRROR_EN,
	530	+ enable ? SERDES_MIRROR_EN : 0);
	531	+
	532	+ return 0;
	533	+}
	534	+
	535	+static int rkx110_linktx_dual_input_cfg(struct rk_serdes *serdes, u8 dev_id, bool is_lvds)
	536	+{
	537	+ struct i2c_client *client = serdes->chip[dev_id].client;
	538	+
	539	+ serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, CH1_LVDS_SEL_EN,
	540	+ is_lvds ? CH1_LVDS_SEL_EN : 0);
	541	+
	542	+ return 0;
	543	+}
	544	+
	545	+static int rkx110_linktx_input_port_cfg(struct rk_serdes *serdes, u8 dev_id, u32 port)
	546	+{
	547	+ struct i2c_client *client = serdes->chip[dev_id].client;
	548	+ u32 val;
	549	+
	550	+ val = rk_serdes_get_stream_source(serdes, port);
	551	+ serdes->i2c_update_bits(client, RKLINK_TX_VIDEO_CTRL, SOURCE_ID_MASK, val);
	552	+
	553	+ return 0;
	554	+}
	555	+
	556	+int rkx110_linktx_dsi_rec_start(struct rk_serdes *serdes, u8 dev_id, u8 dsi_id, bool enable)
	557	+{
	558	+ struct i2c_client *client = serdes->chip[dev_id].client;
	559	+
	560	+ serdes->i2c_update_bits(client, SER_RKLINK_DSI_REC0(dsi_id), DSI_REC_START,
	561	+ enable ? DSI_REC_START : 0);
	562	+
	563	+ return 0;
	564	+}
	565	+
	566	+int rkx110_linktx_dsi_type_select(struct rk_serdes *serdes, u8 dev_id, u8 dsi_id, bool is_cmd)
	567	+{
	568	+ struct i2c_client *client = serdes->chip[dev_id].client;
	569	+
	570	+ serdes->i2c_update_bits(client, SER_RKLINK_DSI_REC0(dsi_id), DSI_CMD_TYPE,
	571	+ is_cmd ? DSI_CMD_TYPE : 0);
	572	+
	573	+ return 0;
	574	+}
	575	+
	576	+int rkx110_linktx_dsi_deley_length_config(struct rk_serdes *serdes, u8 dev_id, u8 dsi_id,
	577	+ u32 length)
	578	+{
	579	+ struct i2c_client *client = serdes->chip[dev_id].client;
	580	+
	581	+ serdes->i2c_update_bits(client, SER_RKLINK_DSI_REC3(dsi_id), DSI_DELAY_LENGTH_MASK,
	582	+ DSI_DELAY_LENGTH(length));
472	583
473	584	return 0;
474	585	}
..	..	@@ -479,22 +590,22 @@
479	590	struct videomode *vm = &route->vm;
480	591	struct i2c_client *client = serdes->chip[DEVICE_LOCAL].client;
481	592	struct hwclk *hwclk = serdes->chip[DEVICE_LOCAL].hwclk;
	593	+ struct rk_serdes_panel *sd_panel = container_of(route, struct rk_serdes_panel, route);
	594	+ struct rkx110_dsi_rx *dsi = &sd_panel->dsi_rx;
482	595	int delay_length;
483	596	u32 value, type;
484	597
485		- if (id == 0) {
486		- hwclk_set_rate(hwclk, RKX110_CPS_DCLK_D_DSI_0_REC_RKLINK_TX,
487		- route->vm.pixelclock);
488		- dev_info(serdes->dev, "RKX110_CPS_DCLK_D_DSI_0_REC_RKLINK_TX:%d\n",
489		- hwclk_get_rate(hwclk, RKX110_CPS_DCLK_D_DSI_0_REC_RKLINK_TX));
490		- } else if (id == 1) {
	598	+ if (id) {
491	599	hwclk_set_rate(hwclk, RKX110_CPS_DCLK_D_DSI_1_REC_RKLINK_TX,
492	600	route->vm.pixelclock);
493	601	dev_info(serdes->dev, "RKX110_CPS_DCLK_D_DSI_1_REC_RKLINK_TX:%d\n",
494	602	hwclk_get_rate(hwclk, RKX110_CPS_DCLK_D_DSI_1_REC_RKLINK_TX));
495	603
496	604	} else {
497		- return 0;
	605	+ hwclk_set_rate(hwclk, RKX110_CPS_DCLK_D_DSI_0_REC_RKLINK_TX,
	606	+ route->vm.pixelclock);
	607	+ dev_info(serdes->dev, "RKX110_CPS_DCLK_D_DSI_0_REC_RKLINK_TX:%d\n",
	608	+ hwclk_get_rate(hwclk, RKX110_CPS_DCLK_D_DSI_0_REC_RKLINK_TX));
498	609	}
499	610
500	611	/* config SER_RKLINK_DSI_REC1 */
..	..	@@ -507,17 +618,25 @@
507	618	value = DSI_VFP(vm->vfront_porch);
508	619	value \|= DSI_VBP(vm->vback_porch);
509	620	value \|= DSI_VSA(vm->vsync_len);
510		- serdes->i2c_write_reg(client, SER_RKLINK_DSI_REC2(id), value);
	621	+ serdes->i2c_update_bits(client, SER_RKLINK_DSI_REC2(id), DSI_DST_VPORCH_MASK, value);
511	622
512		- if (id)
513		- type = (serdes->route_flag & ROUTE_MULTI_CHANNEL) ? DSI_0_DST(0) : DSI_0_DST(2);
514		- else
515		- type = (serdes->route_flag & ROUTE_MULTI_CHANNEL) ? DSI_0_DST(3) : DSI_0_DST(1);
	623	+ if (route->local_port0) {
	624	+ if (serdes->route_nr == 2) {
	625	+ type = id ? DSI_0_DST(2) : DSI_0_DST(1);
	626	+ } else {
	627	+ if (id)
	628	+ type = (serdes->channel_nr == 2) ? DSI_0_DST(0) : DSI_0_DST(2);
	629	+ else
	630	+ type = (serdes->channel_nr == 2) ? DSI_0_DST(3) : DSI_0_DST(1);
	631	+ }
	632	+ } else {
	633	+ type = id ? DSI_0_DST(1) : DSI_0_DST(2);
	634	+ }
516	635
517	636	serdes->i2c_update_bits(client, SER_RKLINK_DSI_REC2(0), DSI_0_DST_MASK, type);
518	637
519	638	/* config SER_RKLINK_DSI_REC3 */
520		- if (serdes->dsi_rx.mode_flags & SERDES_MIPI_DSI_MODE_VIDEO)
	639	+ if (dsi->mode_flags & SERDES_MIPI_DSI_MODE_VIDEO)
521	640	delay_length = vm->hsync_len + vm->hback_porch +
522	641	vm->hactive + vm->hfront_porch;
523	642	else
..	..	@@ -531,33 +650,12 @@
531	650
532	651	/* config SER_RKLINK_DSI_REC0 */
533	652	value = DSI_REC_START;
534		- if (!(serdes->dsi_rx.mode_flags & SERDES_MIPI_DSI_MODE_VIDEO))
	653	+ if (!(dsi->mode_flags & SERDES_MIPI_DSI_MODE_VIDEO))
535	654	value \|= DSI_CMD_TYPE;
536	655
537	656	value \|= DSI_HACT(vm->hactive);
538	657	value \|= DSI_VACT(vm->vactive);
539	658	serdes->i2c_write_reg(client, SER_RKLINK_DSI_REC0(id), value);
540		-
541		- return 0;
542		-}
543		-
544		-static int rk110_linktx_cfg(struct rk_serdes serdes, struct rk_serdes_route route)
545		-{
546		- u8 remote_id = 0;
547		-
548		- rk_serdes_link_tx_ctrl_enable(serdes, route, remote_id);
549		-
550		- if (route->local_port0 & RK_SERDES_DSI_RX0) {
551		- rk_serdes_link_tx_dsi_enable(serdes, route, 0);
552		- if (serdes->route_flag & ROUTE_MULTI_DSI_INPUT)
553		- rk_serdes_link_tx_dsi_enable(serdes, route, 1);
554		- }
555		-
556		- if (route->local_port0 & RK_SERDES_DSI_RX1) {
557		- rk_serdes_link_tx_dsi_enable(serdes, route, 1);
558		- if (serdes->route_flag & ROUTE_MULTI_DSI_INPUT)
559		- rk_serdes_link_tx_dsi_enable(serdes, route, 0);
560		- }
561	659
562	660	return 0;
563	661	}
..	..	@@ -583,24 +681,96 @@
583	681	return 0;
584	682	}
585	683
586		-int rkx110_linktx_enable(struct rk_serdes serdes, struct rk_serdes_route route)
	684	+static int rkx110_display_linktx_ctrl_enable(struct rk_serdes *serdes,
	685	+ struct rk_serdes_route *route,
	686	+ u8 dev_id)
587	687	{
588		- rk110_linktx_cfg(serdes, route);
	688	+ struct hwclk *hwclk = serdes->chip[dev_id].hwclk;
	689	+ bool enable;
	690	+ bool is_lvds = false;
	691	+
	692	+ rk110_linktx_stream_type_cfg(serdes, dev_id);
	693	+
	694	+ enable = (serdes->lane_nr == 2) ? true : false;
	695	+ rk110_linktx_dual_lane_enable(serdes, dev_id, enable);
	696	+
	697	+ enable = (serdes->channel_nr == 2) ? true : false;
	698	+ rk110_linktx_dual_channel_enable(serdes, dev_id, enable);
	699	+
	700	+ enable = (route->route_flag & ROUTE_MULTI_MIRROR) ? true : false;
	701	+ rk110_linktx_replicate_enable(serdes, dev_id, enable);
	702	+
	703	+ if (((route->local_port0 == RK_SERDES_LVDS_RX0) \|\|
	704	+ (route->local_port0 == RK_SERDES_LVDS_RX1) \|\|
	705	+ (route->local_port1 == RK_SERDES_LVDS_RX0) \|\|
	706	+ (route->local_port1 == RK_SERDES_LVDS_RX1)) &&
	707	+ (serdes->route_nr == 2))
	708	+ is_lvds = true;
	709	+ rkx110_linktx_dual_input_cfg(serdes, dev_id, is_lvds);
	710	+
	711	+ if (route->local_port0) {
	712	+ rkx110_linktx_input_port_cfg(serdes, dev_id, route->local_port0);
	713	+ } else {
	714	+ if (route->local_port1 == RK_SERDES_LVDS_RX0)
	715	+ rkx110_linktx_input_port_cfg(serdes, dev_id, RK_SERDES_LVDS_RX1);
	716	+ else if (route->local_port1 == RK_SERDES_LVDS_RX1)
	717	+ rkx110_linktx_input_port_cfg(serdes, dev_id, RK_SERDES_LVDS_RX0);
	718	+ else if (route->local_port1 == RK_SERDES_DSI_RX0)
	719	+ rkx110_linktx_input_port_cfg(serdes, dev_id, RK_SERDES_DSI_RX1);
	720	+ else if (route->local_port1 == RK_SERDES_DSI_RX1)
	721	+ rkx110_linktx_input_port_cfg(serdes, dev_id, RK_SERDES_DSI_RX0);
	722	+
	723	+ }
	724	+
	725	+ if (route->local_port0 & RK_SERDES_DUAL_LVDS_RX) {
	726	+ hwclk_set_rate(hwclk, RKX110_CPS_CLK_2X_LVDS_RKLINK_TX, route->vm.pixelclock);
	727	+ dev_info(serdes->dev, "RKX110_CPS_CLK_2X_LVDS_RKLINK_TX:%d\n",
	728	+ hwclk_get_rate(hwclk, RKX110_CPS_CLK_2X_LVDS_RKLINK_TX));
	729	+ }
	730	+
	731	+ if (serdes->version == SERDES_V1) {
	732	+ /*
	733	+ * The serdes v1 have a bug when enable video suspend function, which
	734	+ * is used to enhance the i2c frequency. A workaround ways to do it is
	735	+ * reducing the video packet length:
	736	+ * length = ((hactive x 24 / 32 / 16) + 15) / 16 * 16
	737	+ */
	738	+ u32 length;
	739	+
	740	+ length = route->vm.hactive * 24 / 32 / 16;
	741	+ length = (length + 15) / 16 * 16;
	742	+ rk110_linktx_config_pkg_length(serdes, dev_id, length);
	743	+ }
	744	+
	745	+ rkx110_linktx_ser_enable(serdes, dev_id, true);
	746	+
	747	+ return 0;
	748	+}
	749	+
	750	+int rkx110_display_linktx_enable(struct rk_serdes serdes, struct rk_serdes_route route)
	751	+{
	752	+ rkx110_display_linktx_ctrl_enable(serdes, route, DEVICE_LOCAL);
	753	+
	754	+ if (route->local_port0 & RK_SERDES_DSI_RX0)
	755	+ rk_serdes_link_tx_dsi_enable(serdes, route, 0);
	756	+
	757	+ if (route->local_port0 & RK_SERDES_DSI_RX1)
	758	+ rk_serdes_link_tx_dsi_enable(serdes, route, 1);
	759	+
	760	+ if (route->local_port1 & RK_SERDES_DSI_RX0)
	761	+ rk_serdes_link_tx_dsi_enable(serdes, route, 0);
	762	+
	763	+ if (route->local_port1 & RK_SERDES_DSI_RX1)
	764	+ rk_serdes_link_tx_dsi_enable(serdes, route, 1);
	765	+
589	766	rk110_ser_pcs_cfg(serdes, route, 0);
590	767	rk110_ser_pma_cfg(serdes, route, 0);
591		- if (serdes->route_flag & ROUTE_MULTI_LANE) {
	768	+ if (serdes->lane_nr == 2) {
592	769	rk110_ser_pcs_cfg(serdes, route, 1);
593	770	rk110_ser_pma_cfg(serdes, route, 1);
594	771	}
595	772
596	773	return 0;
597		-}
598		-
599		-void rkx110_linktx_video_enable(struct rk_serdes *serdes, u8 dev_id, bool enable)
600		-{
601		- struct i2c_client *client = serdes->chip[dev_id].client;
602		-
603		- serdes->i2c_update_bits(client, RKLINK_TX_SERDES_CTRL, VIDEO_EN, enable ? VIDEO_EN : 0);
604	774	}
605	775
606	776	void rkx110_linktx_channel_enable(struct rk_serdes *serdes, u8 ch_id, u8 dev_id, bool enable)
..	..	@@ -636,7 +806,7 @@
636	806	}
637	807	}
638	808
639		-void rkx110_linktx_wait_link_ready(struct rk_serdes *serdes, u8 id)
	809	+int rkx110_linktx_wait_link_ready(struct rk_serdes *serdes, u8 id)
640	810	{
641	811	struct i2c_client *client = serdes->chip[DEVICE_LOCAL].client;
642	812	u32 val;
..	..	@@ -656,6 +826,8 @@
656	826	dev_err(&client->dev, "wait link ready timeout: 0x%08x\n", val);
657	827	else
658	828	dev_info(&client->dev, "link success: 0x%08x\n", val);
	829	+
	830	+ return ret;
659	831	}
660	832
661	833	void rkx110_pma_set_rate(struct rk_serdes serdes, struct rk_serdes_pma_pll pll,
..	..	@@ -736,3 +908,346 @@
736	908
737	909	serdes->i2c_update_bits(client, SER_GRF_SOC_CON7, mask, val);
738	910	}
	911	+
	912	+static void rkx110_linktx_irq_enable(struct rk_serdes *serdes, u8 dev_id)
	913	+{
	914	+ struct i2c_client *client = serdes->chip[dev_id].client;
	915	+
	916	+ serdes->i2c_write_reg(client, SER_GRF_IRQ_EN, SER_IRQ_LINK_EN);
	917	+
	918	+ serdes->i2c_write_reg(client, SER_RKLINK_SOURCE_IRQ_EN, TRAIN_DONE_IRQ_OUTPUT_EN \|
	919	+ FIFO_UNDERRUN_IRQ_OUTPUT_EN \| FIFO_OVERFLOW_IRQ_OUTPUT_EN);
	920	+}
	921	+
	922	+static void rkx110_linktx_irq_disable(struct rk_serdes *serdes, u8 dev_id)
	923	+{
	924	+ struct i2c_client *client = serdes->chip[dev_id].client;
	925	+ u32 val = 0;
	926	+
	927	+ serdes->i2c_write_reg(client, SER_GRF_IRQ_EN, SER_IRQ_LINK_DIS);
	928	+ serdes->i2c_read_reg(client, SER_RKLINK_SOURCE_IRQ_EN, &val);
	929	+ val &= ~(SER_RKLINK_SOURCE_IRQ_EN \| TRAIN_DONE_IRQ_OUTPUT_EN \|
	930	+ FIFO_UNDERRUN_IRQ_OUTPUT_EN \| FIFO_OVERFLOW_IRQ_OUTPUT_EN);
	931	+ serdes->i2c_write_reg(client, SER_RKLINK_SOURCE_IRQ_EN, val);
	932	+}
	933	+
	934	+static void rkx110_linktx_fifo_handler(struct rk_serdes *serdes, u8 dev_id)
	935	+{
	936	+ struct i2c_client *client = serdes->chip[dev_id].client;
	937	+ u32 value;
	938	+
	939	+ serdes->i2c_read_reg(client, SER_RKLINK_FIFO_STATUS, &value);
	940	+ dev_err(serdes->dev, "ser rklink fifo status:0x%x\n", value);
	941	+
	942	+ if (value & CH1_CMD_FIFO_UNDERRUN)
	943	+ dev_err(serdes->dev, "linktx ch1 cmd fifo underrun\n");
	944	+ if (value & CH0_CMD_FIFO_UNDERRUN)
	945	+ dev_err(serdes->dev, "linktx ch0 cmd fifo underrun\n");
	946	+ if (value & DATA1_FIFO_UNDERRUN)
	947	+ dev_err(serdes->dev, "linktx data1 fifo underrun\n");
	948	+ if (value & DATA0_FIFO_UNDERRUN)
	949	+ dev_err(serdes->dev, "linktx data0 fifo underrun\n");
	950	+ if (value & AUDIO_FIFO_UNDERRUN)
	951	+ dev_err(serdes->dev, "linktx audio fifo underrun\n");
	952	+ if (value & LVDS1_FIFO_UNDERRUN)
	953	+ dev_err(serdes->dev, "linktx lvds1 fifo underrun\n");
	954	+ if (value & LVDS0_FIFO_UNDERRUN)
	955	+ dev_err(serdes->dev, "linktx lvds0 fifo underrun\n");
	956	+ if (value & DSI_CH1_FIFO_UNDERRUN)
	957	+ dev_err(serdes->dev, "linktx dsi ch1 fifo underrun\n");
	958	+ if (value & DSI_CH0_FIFO_UNDERRUN)
	959	+ dev_err(serdes->dev, "linktx dsi ch0 fifo underrun\n");
	960	+ if (value & CH1_CMD_FIFO_OVERFLOW)
	961	+ dev_err(serdes->dev, "linktx ch1 cmd fifo overflow\n");
	962	+ if (value & CH0_CMD_FIFO_OVERFLOW)
	963	+ dev_err(serdes->dev, "linktx ch0 cmd fifo overflow\n");
	964	+ if (value & DATA1_FIFO_OVERFLOW)
	965	+ dev_err(serdes->dev, "linktx data1 fifo overflow\n");
	966	+ if (value & DATA0_FIFO_OVERFLOW)
	967	+ dev_err(serdes->dev, "linktx data0 fifo overflow\n");
	968	+ if (value & AUDIO_FIFO_OVERFLOW)
	969	+ dev_err(serdes->dev, "linktx audio fifo overflow\n");
	970	+ if (value & LVDS1_FIFO_OVERFLOW)
	971	+ dev_err(serdes->dev, "linktx lvds1 fifo overflow\n");
	972	+ if (value & LVDS0_FIFO_OVERFLOW)
	973	+ dev_err(serdes->dev, "linktx lvds0 fifo overflow\n");
	974	+ if (value & DSI_CH1_FIFO_OVERFLOW)
	975	+ dev_err(serdes->dev, "linktx dsi ch1 fifo overflow\n");
	976	+ if (value & DSI_CH0_FIFO_OVERFLOW)
	977	+ dev_err(serdes->dev, "linktx dsi ch0 fifo overflow\n");
	978	+
	979	+ /* clear fifo status */
	980	+ serdes->i2c_write_reg(client, SER_RKLINK_FIFO_STATUS, value);
	981	+}
	982	+
	983	+static void rkx110_linktx_irq_handler(struct rk_serdes *serdes, u8 dev_id)
	984	+{
	985	+ struct i2c_client *client = serdes->chip[dev_id].client;
	986	+ u32 flag, value;
	987	+ int i = 0;
	988	+
	989	+ serdes->i2c_read_reg(client, SER_RKLINK_SOURCE_IRQ_EN, &flag);
	990	+ flag &= TRAIN_DONE_IRQ_FLAG \| FIFO_UNDERRUN_IRQ_FLAG \| FIFO_OVERFLOW_IRQ_FLAG \|
	991	+ AUDIO_FM_IRQ_OUTPUT_FLAG;
	992	+ dev_info(serdes->dev, "linktx irq flag:0x%08x\n", flag);
	993	+ while (flag) {
	994	+ switch (flag & BIT(i)) {
	995	+ case TRAIN_DONE_IRQ_FLAG:
	996	+ serdes->i2c_read_reg(client, SER_RKLINK_TRAIN_CTRL, &value);
	997	+ dev_info(serdes->dev, "linktx train done, status:0x%08x\n", value);
	998	+ /* write any thing to train ctrl will clear the train done irq flag */
	999	+ serdes->i2c_write_reg(client, SER_RKLINK_TRAIN_CTRL, value);
	1000	+ break;
	1001	+ case FIFO_UNDERRUN_IRQ_FLAG:
	1002	+ case FIFO_OVERFLOW_IRQ_FLAG:
	1003	+ flag &= ~(FIFO_UNDERRUN_IRQ_FLAG \| FIFO_OVERFLOW_IRQ_FLAG);
	1004	+ rkx110_linktx_fifo_handler(serdes, dev_id);
	1005	+ break;
	1006	+ case AUDIO_FM_IRQ_OUTPUT_FLAG:
	1007	+ break;
	1008	+ default:
	1009	+ break;
	1010	+ }
	1011	+ flag &= ~BIT(i);
	1012	+ i++;
	1013	+ }
	1014	+}
	1015	+
	1016	+static void rkx110_pcs_irq_enable(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
	1017	+{
	1018	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1019	+ u32 val;
	1020	+
	1021	+ val = pcs_id ? SER_IRQ_PCS1_EN : SER_IRQ_PCS0_EN;
	1022	+ serdes->i2c_write_reg(client, SER_GRF_IRQ_EN, val);
	1023	+
	1024	+ serdes->i2c_write_reg(client, PCS_REG30(pcs_id), PCS_INT_STARTUP(0xffff));
	1025	+ serdes->i2c_write_reg(client, PCS_REG34(pcs_id), PCS_INT_REMOTE_MODE(0xffff));
	1026	+}
	1027	+
	1028	+static void rkx110_pcs_irq_disable(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
	1029	+{
	1030	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1031	+ u32 val;
	1032	+
	1033	+ val = pcs_id ? SER_IRQ_PCS1_DIS : SER_IRQ_PCS0_DIS;
	1034	+ serdes->i2c_write_reg(client, SER_GRF_IRQ_EN, val);
	1035	+
	1036	+ serdes->i2c_write_reg(client, PCS_REG30(pcs_id), PCS_INT_STARTUP(0));
	1037	+ serdes->i2c_write_reg(client, PCS_REG34(pcs_id), PCS_INT_REMOTE_MODE(0));
	1038	+}
	1039	+
	1040	+static void rkx110_pcs_irq_handler(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
	1041	+{
	1042	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1043	+ u32 value;
	1044	+
	1045	+ serdes->i2c_read_reg(client, PCS_REG24(pcs_id), &value);
	1046	+ dev_info(serdes->dev, "ser pcs%d startup fatal status:0x%08x\n", pcs_id, value);
	1047	+
	1048	+ serdes->i2c_read_reg(client, PCS_REG28(pcs_id), &value);
	1049	+ dev_info(serdes->dev, "ser pcs%d remote mode fatal status:0x%08x\n", pcs_id, value);
	1050	+
	1051	+ /* clear startup fatal status */
	1052	+ serdes->i2c_write_reg(client, PCS_REG1C(pcs_id), 0xffffffff);
	1053	+ serdes->i2c_write_reg(client, PCS_REG1C(pcs_id), 0xffff0000);
	1054	+
	1055	+ /* clear remote fatal status */
	1056	+ serdes->i2c_write_reg(client, PCS_REG14(pcs_id), 0xffffffff);
	1057	+ serdes->i2c_write_reg(client, PCS_REG14(pcs_id), 0xffff0000);
	1058	+}
	1059	+
	1060	+static void rkx110_pma_irq_enable(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
	1061	+{
	1062	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1063	+ u32 val;
	1064	+
	1065	+ val = pcs_id ? SER_IRQ_PMA_ADAPT1_EN : SER_IRQ_PMA_ADAPT0_EN;
	1066	+ serdes->i2c_write_reg(client, SER_GRF_IRQ_EN, val);
	1067	+
	1068	+ serdes->i2c_write_reg(client, SER_PMA_IRQ_EN(pcs_id), FORCE_INITIAL_IRQ_EN \|
	1069	+ RTERM_ONCE_TIMEOUT_IRQ_EN \| PLL_LOCK_TIMEOUT_IRQ_EN);
	1070	+}
	1071	+
	1072	+static void rkx110_pma_irq_disable(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
	1073	+{
	1074	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1075	+ u32 val;
	1076	+
	1077	+ val = pcs_id ? SER_IRQ_PMA_ADAPT1_DIS : SER_IRQ_PMA_ADAPT0_DIS;
	1078	+ serdes->i2c_write_reg(client, SER_GRF_IRQ_EN, val);
	1079	+
	1080	+ serdes->i2c_write_reg(client, SER_PMA_IRQ_EN(pcs_id), 0);
	1081	+}
	1082	+
	1083	+static void rkx110_pma_irq_handler(struct rk_serdes *serdes, u8 pcs_id, u8 dev_id)
	1084	+{
	1085	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1086	+ u32 value;
	1087	+
	1088	+ serdes->i2c_read_reg(client, SER_PMA_IRQ_STATUS(pcs_id), &value);
	1089	+ dev_info(serdes->dev, "ser pma%d irq status:0x%08x\n", pcs_id, value);
	1090	+
	1091	+ if (value & FORCE_INITIAL_PULSE_STATUS)
	1092	+ dev_info(serdes->dev, "ser pma trig force initial pulse status\n");
	1093	+ else if (value & RTERM_ONCE_TIMEOUT_STATUS)
	1094	+ dev_info(serdes->dev, "ser pma trig rterm once timeout status\n");
	1095	+ else if (value & PLL_LOCK_TIMEOUT_STATUS)
	1096	+ dev_info(serdes->dev, "ser pma trig pll lock timeout status\n");
	1097	+
	1098	+ /* clear pma irq status */
	1099	+ serdes->i2c_write_reg(client, SER_PMA_IRQ_STATUS(pcs_id), value);
	1100	+}
	1101	+
	1102	+static void rkx110_remote_irq_enable(struct rk_serdes *serdes, u8 dev_id)
	1103	+{
	1104	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1105	+
	1106	+ if (serdes->stream_type == STREAM_DISPLAY) {
	1107	+ serdes->i2c_write_reg(client, SER_GRF_IRQ_EN, SER_IRQ_REMOTE_EN);
	1108	+ rkx120_irq_enable(serdes, DEVICE_REMOTE0);
	1109	+ }
	1110	+}
	1111	+
	1112	+
	1113	+static void rkx110_remote_irq_disable(struct rk_serdes *serdes, u8 dev_id)
	1114	+{
	1115	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1116	+
	1117	+ if (serdes->stream_type == STREAM_DISPLAY) {
	1118	+ serdes->i2c_write_reg(client, SER_GRF_IRQ_EN, SER_IRQ_REMOTE_DIS);
	1119	+ rkx120_irq_disable(serdes, DEVICE_REMOTE0);
	1120	+ }
	1121	+}
	1122	+
	1123	+static void rkx110_remote_irq_handler(struct rk_serdes *serdes, u8 dev_id)
	1124	+{
	1125	+ if (serdes->stream_type == STREAM_DISPLAY)
	1126	+ rkx120_irq_handler(serdes, DEVICE_REMOTE0);
	1127	+}
	1128	+
	1129	+void rkx110_irq_enable(struct rk_serdes *serdes, u8 dev_id)
	1130	+{
	1131	+ /* enable pcs irq */
	1132	+ rkx110_pcs_irq_enable(serdes, 0, dev_id);
	1133	+
	1134	+ /* enable dsirx irq */
	1135	+
	1136	+ /* enable gpio irq */
	1137	+
	1138	+ /* enable csihost irq */
	1139	+
	1140	+ /* enable pma_adapt irq */
	1141	+ rkx110_pma_irq_enable(serdes, 0, dev_id);
	1142	+
	1143	+ /* enable efuse irq */
	1144	+
	1145	+ /* enable vicap irq */
	1146	+
	1147	+ /* enable remote irq */
	1148	+ rkx110_remote_irq_enable(serdes, dev_id);
	1149	+
	1150	+ /* enable ext irq */
	1151	+
	1152	+ /* enable link irq */
	1153	+ rkx110_linktx_irq_enable(serdes, dev_id);
	1154	+}
	1155	+
	1156	+void rkx110_irq_disable(struct rk_serdes *serdes, u8 dev_id)
	1157	+{
	1158	+ /* disable pcs irq */
	1159	+ rkx110_pcs_irq_disable(serdes, 0, dev_id);
	1160	+
	1161	+ /* disable dsirx irq */
	1162	+
	1163	+ /* disable gpio irq */
	1164	+
	1165	+ /* disable csihost irq */
	1166	+
	1167	+ /* disable pma_adapt irq */
	1168	+ rkx110_pma_irq_disable(serdes, 0, dev_id);
	1169	+
	1170	+ /* disable efuse irq */
	1171	+
	1172	+ /* disable vicap irq */
	1173	+
	1174	+ /* disable remote irq and other lane irq*/
	1175	+ rkx110_remote_irq_disable(serdes, dev_id);
	1176	+
	1177	+ /* disable ext irq */
	1178	+
	1179	+ /* disable link irq */
	1180	+ rkx110_linktx_irq_disable(serdes, dev_id);
	1181	+}
	1182	+
	1183	+int rkx110_irq_handler(struct rk_serdes *serdes, u8 dev_id)
	1184	+{
	1185	+ struct i2c_client *client = serdes->chip[dev_id].client;
	1186	+ u32 status, mask;
	1187	+ u32 i = 0;
	1188	+
	1189	+ serdes->i2c_read_reg(client, SER_GRF_IRQ_EN, &mask);
	1190	+ serdes->i2c_read_reg(client, SER_GRF_IRQ_STATUS, &status);
	1191	+ dev_info(serdes->dev, "dev%d get the ser irq status:0x%08x\n", dev_id, status);
	1192	+
	1193	+ status &= mask;
	1194	+
	1195	+ while (status) {
	1196	+ switch (status & BIT(i)) {
	1197	+ case SER_IRQ_PCS0:
	1198	+ rkx110_pcs_irq_handler(serdes, 0, dev_id);
	1199	+ break;
	1200	+ case SER_IRQ_PCS1:
	1201	+ rkx110_pcs_irq_handler(serdes, 1, dev_id);
	1202	+ break;
	1203	+ case SER_IRQ_DSIRX0:
	1204	+ /* TBD */
	1205	+ break;
	1206	+ case SER_IRQ_DSIRX1:
	1207	+ /* TBD */
	1208	+ break;
	1209	+ case SER_IRQ_GPIO0:
	1210	+ /* TBD */
	1211	+ break;
	1212	+ case SER_IRQ_GPIO1:
	1213	+ /* TBD */
	1214	+ break;
	1215	+ case SER_IRQ_CSIHOST0:
	1216	+ /* TBD */
	1217	+ break;
	1218	+ case SER_IRQ_CSIHOST1:
	1219	+ /* TBD */
	1220	+ break;
	1221	+ case SER_IRQ_PMA_ADAPT0:
	1222	+ rkx110_pma_irq_handler(serdes, 0, dev_id);
	1223	+ break;
	1224	+ case SER_IRQ_PMA_ADAPT1:
	1225	+ rkx110_pma_irq_handler(serdes, 1, dev_id);
	1226	+ break;
	1227	+ case SER_IRQ_EFUSE:
	1228	+ /* TBD */
	1229	+ break;
	1230	+ case SER_IRQ_VICAP:
	1231	+ /* TBD */
	1232	+ break;
	1233	+ case SER_IRQ_REMOTE:
	1234	+ rkx110_remote_irq_handler(serdes, dev_id);
	1235	+ break;
	1236	+ case SER_IRQ_EXT:
	1237	+ /* TBD */
	1238	+ break;
	1239	+ case SER_IRQ_LINK:
	1240	+ rkx110_linktx_irq_handler(serdes, dev_id);
	1241	+ break;
	1242	+ case SER_IRQ_OTHER_LANE:
	1243	+ /* TBD */
	1244	+ break;
	1245	+ default:
	1246	+ break;
	1247	+ }
	1248	+ status &= ~BIT(i);
	1249	+ i++;
	1250	+ }
	1251	+
	1252	+ return 0;
	1253	+}